DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment/Argument
Applicant's arguments filed 01/16/2026 with respect to the rejections of claims 1-17 and 19-20 have been fully considered but they are not persuasive. The prior art of record can be broadly reinterpreted to read upon the amended claims, and the amended rejection is fully outlined below. However, Examiner will note that the inventive concept depicted in Figure 2 that Examiner believes the applicant is trying to capture appears to be allowable, pending complete search and consideration.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-7 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 4, it is indefinite because the claim requires two separate components to be in the same place, which is not possible for a single embodiment. Claim 1 requires a recess to be filled with a molding resin and claim 4, which depends from claim 1, requires the same recess to be filled with a dam structure. While the terms “molding resin” and “dam structure” can broadly describe the same singular object, this interpretation is inconsistent with the specification and drawings. Correction or clarifying amendments are required.
Claims 5-7 are also rejected under 35 U.S.C. 112(b) for depending from rejected claim 4.
Regarding claim 17, it is indefinite because the claim requires two separate components to be in the same place, which is not possible for a single embodiment. Claim 12 requires a recess to be filled with a molding resin and claim 17, which depends from claim 12, requires the same recess to be filled with a dam structure. While the terms “molding resin” and “dam structure” can broadly describe the same singular object, this interpretation is inconsistent with the specification and drawings. Correction or clarifying amendments are required.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-2 and 4-7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (US-20200135605-A1 – hereinafter Yu).
Regarding claim 1, Yu teaches a semiconductor device (Fig.11 1001; ¶0011) comprising:
a plurality of semiconductor chips (Fig.7 201; ¶0024) stacked on a substrate (Fig.11 105; ¶0024) in a vertical direction;
a filler structure (Fig.11 701; ¶0031) including a plurality of horizontal underfill layers (Fig.11 layers of 701 in between each instance of 201) formed between adjacent semiconductor chips (201) of the plurality of semiconductor chips (201) and between the substrate (105) and the stack of semiconductor chips (201), and including underfill sidewalls (Fig.11 outer sides of 701) formed around the horizontal underfill layers and the plurality of semiconductor chips (201); and
a molding resin (Fig.11 501 can be made of a molding resin; ¶0029) surrounding the plurality of semiconductor chips (201) at least on side surfaces of the semiconductor chips (201), wherein the underfill sidewalls (outer sides of 701) comprise a recess pattern (Fig.11 the space occupied by 501), which is disposed on and along the side surfaces of at least one of the plurality of semiconductor chips (201), and is recessed in a direction parallel to an upper surface of the substrate (105) at locations where the recess pattern (the space occupied by 501) meets the substrate (105), wherein the molding resin (501) fills the recess pattern (the space occupied by 501).
Regarding claim 2, Yu teaches the semiconductor device of claim 1, wherein the recess pattern (the space occupied by 501) comprises a first surface (top surface) facing the substrate (105) and extending toward the plurality of semiconductor chips (201), and a second surface (inside vertical surface) connecting the first surface (top surface of the recess) to the upper surface of the substrate (105), and
wherein the recess pattern (the space occupied by 501) extends along a periphery of a lowermost semiconductor chip (lowest 201) among the plurality of semiconductor chips (201).
Regarding claim 4, Yu teaches the semiconductor device of claim 2, further comprising a dam structure (501 is also a dam structure that can be formed with a molding resin; ¶0029) provided on the substrate (105), the dam structure (501) contacting the first surface (top surface of the recess) and the second surface (inside vertical surface of the recess).
Regarding claim 5, Yu teaches the semiconductor device of claim 4, wherein the dam structure (501) has four sides from a plan view (Fig.5A), a width of one side is between 200 μm and 1200 μm (¶0029) in a direction parallel to the upper surface of the substrate (105).
Regarding claim 6, Yu teaches the semiconductor device of claim 4, wherein an upper surface of the dam structure (501) is on the same plane as the first surface (top surface of the recess).
Regarding claim 7, Yu teaches the semiconductor device of claim 4, wherein the dam structure (501) comprises a metal, silicon oxide, silicon nitride, or a polymer (¶0029).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu.
Regarding claim 8, Yu teaches the semiconductor device of claim 2.
Yu does not explicitly teach wherein a vertical distance between the first surface and the substrate is 0.5 times to 1.8 times a vertical distance between an upper surface of the lowermost semiconductor chip among the plurality of semiconductor chips and the upper surface of the substrate.
However, it would have been obvious to form the claimed vertical distances within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu.
Regarding claim 11, Yu teaches the semiconductor device of claim 2, wherein the second surface is a flat surface (inside vertical surface of the recess is flat), and the first surface is a flat surface (top surface of the recess is a flat surface) and comprises a width, measured between the second surface and an outside surface of the underfill sidewalls (sidewalls of 701).
Yu does not explicitly teach wherein the width is between 3 μm and 40 μm, and a horizontal distance between the outside surface and a side surface of the lowermost semiconductor chip is between 40 μm and 300 μm.
However, it would have been obvious to form the width and distance within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Du et al. (US-20220093559-A1 – hereinafter Du).
Regarding claim 3, Yu teaches the semiconductor device of claim 2, wherein a vertical distance between the first surface (top surface of the recess) and the substrate (105) is between 20 μm and 100 μm (¶0029).
Yu does not teach wherein the first surface is lying within a plane that intersects the lowermost semiconductor chip.
Du teaches a dam structure (Fig.1 106; ¶0018 of Du) that has a top surface in a plane intersecting a single semiconductor chip (Fig.1 104; ¶0018 of Du).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, for the top surface of the recess (the space occupied by dam 501 of Yu) to be within a plane intersecting the lowermost semiconductor chip (bottom 201 of Yu) to arrive at the claimed invention. This modification is obvious because shorter die stacks would require shorter dam structures, potentially in a plane intersecting the lowest semiconductor chip.
Claim(s) 9-10, 12-14, 19-20 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Jeng et al. (US-20230352463-A1 – hereinafter Jeng).
Regarding claim 9, Yu teaches a semiconductor device (Fig.11 1001; ¶0011) comprising:
a plurality of semiconductor chips (Fig.7 201; ¶0024) stacked on a substrate (Fig.11 105; ¶0024) in a vertical direction;
a filler structure (Fig.11 701; ¶0031) including a plurality of horizontal underfill layers (Fig.11 layers of 701 in between each instance of 201) formed between adjacent semiconductor chips (201) of the plurality of semiconductor chips (201) and between the substrate (105) and the stack of semiconductor chips (201), and including underfill sidewalls (Fig.11 outer sides of 701) formed around the horizontal underfill layers and the plurality of semiconductor chips (201); and
a molding resin (Fig.11 501 and 801 comprise similar materials; ¶0029 and ¶0032) surrounding the plurality of semiconductor chips (201) at least on side surfaces of the semiconductor chips,
wherein the underfill sidewalls (outer sides of 701) comprise a recess pattern (Fig.11 the space occupied by 501), which is disposed on and along the side surfaces of at least one of the plurality of semiconductor chips (201), and is recessed in a direction parallel to an upper surface of the substrate (105) at locations where the recess pattern (the space occupied by 501) meets the substrate (105),
wherein the recess pattern (the space occupied by 501) comprises a first surface (top surface) facing the substrate (105) and extending toward the plurality of semiconductor chips (201), and a second surface (inside vertical surface) connecting the first surface (top surface) to the upper surface of the substrate (105),
wherein the recess pattern (the space occupied by 501) extends along a periphery of a lowermost semiconductor chip (lowest 201) among the plurality of semiconductor chips (201),
wherein the underfill sidewalls (outer sides of 701) comprise an outside surface (the surface of 701 that contacts 801) contacting the molding resin (501 and 801), over the recess pattern (the space occupied by 501), and
wherein the outside surface (the surface of 701 that contacts 801) is substantially vertical with respect to the upper surface of the substrate (105), the first surface (top surface) is parallel to the upper surface of the substrate (105).
Yu does not teach wherein the outside surface is connected to, and extends perpendicular to, the first surface.
Jeng teaches a die stack (Fig.2 52; ¶0027 of Jeng) with a filler structure (Fig.2 53; ¶0027 of Jeng) having an outside surface (interface between 53 and 62) interfacing with a molding resin (Fig.4 62; ¶0029 of Jeng) that is perpendicular to a lower die (Fig.4 20; ¶0014 of Jeng).
It would have been obvious to one of ordinary skill for the interface between the underfill (701 of Yu) and the molding resin (501 and 801 of Yu) to be vertical as taught by Jeng (53 and 62 of Jeng) to arrive at the claimed invention. This change is obvious because it is a matter of design choice.
Regarding claim 10, the aforementioned combination of Yu in view of Jeng from claim 9 teaches the semiconductor device of claim 9.
The aforementioned combination does not explicitly teach wherein a horizontal distance between the outside surface and the side surfaces of the plurality of semiconductor chips is between 40 μm and 300 μm.
However, it would have been obvious to form the horizontal distance within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 12, Yu teaches a semiconductor package (Fig.11 1001; ¶0011) comprising:
an interposer substrate (Fig.11 1101; ¶0035);
a first semiconductor device (1001 is a first device) arranged on the interposer substrate (1101); and
a molding resin (Fig.11 501 and 801 comprise similar materials; ¶0029 and ¶0032) surrounding side surfaces of the first semiconductor device (1101), wherein the first semiconductor device (1101) comprises:
a buffer chip (Fig.11 105; ¶0024);
a plurality of memory devices (Fig.7 201; ¶0024) stacked on the buffer chip (105) and connected to each other via through-substrate vias (TSVs) (Fig.3 203; ¶0021); and
an underfill fillet (Fig.11 701; ¶0031) on side surfaces of the plurality of memory devices (201), wherein the underfill fillet (701) comprises a recess pattern (Fig.11 the space occupied by 501), which is disposed on and along the side surfaces of at least one of the plurality of memory devices (201), and is recessed in a direction parallel to an upper surface of the buffer chip (105) at locations where the recess pattern (the space occupied by 501) meets the buffer chip (105), wherein the molding resin (501 and 801) fills the recess pattern, and wherein the recess pattern (the space occupied by 501) comprises:
a first surface (top surface of the recess) facing the buffer chip (105) and extending toward the plurality of memory devices (201);
and a second surface (inside vertical surface of the recess) connecting the first surface (top surface of the recess) to the upper surface of the buffer chip (105).
Yu does not teach the package comprising a package substrate;
wherein the interposer substrate is stacked on the package substrate;
a second semiconductor device;
wherein the first and second semiconductor devices are spaced apart from each other in a lateral direction;
and wherein the molding resin surrounds side surfaces of the second semiconductor device.
Jeng teaches a package substrate (Fig.9 102; ¶0040 of Jeng) with a plurality of semiconductor components (Fig.9 50; ¶0040 of Jeng) spaced apart laterally.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to fabricate a device having a package substrate (102 of Jeng) and a plurality of semiconductor components (50 of Jeng), with the individual semiconductor devices fabricated as taught by Yu (Fig.11 of Yu) to arrive at the claimed invention. A practitioner of ordinary skill would have been motivated to make this modification for applications requiring larger chip packages with multiple semiconductor components for increased memory.
Regarding claim 13, the aforementioned combination of Yu in view of Jeng from claim 12 teaches the semiconductor package of claim 12, wherein the first surface (top surface of the recess of Yu) is substantially parallel to the upper surface of the buffer chip (105 of Yu).
Yu does not teach wherein an outside surface of the underfill fillet is connected to, and extends perpendicular to, the first surface.
Jeng teaches a die stack (Fig.2 52; ¶0027 of Jeng) with a filler structure (Fig.2 53; ¶0027 of Jeng) having an outside surface (interface between 53 and 62) interfacing with a molding resin (Fig.4 62; ¶0029 of Jeng) that is perpendicular to a lower die (Fig.4 20; ¶0014 of Jeng).
It would have been obvious to one of ordinary skill for the interface between the underfill (701 of Yu) and the molding resin (501 and 801 of Yu) to be vertical as taught by Jeng (53 and 62 of Jeng) to arrive at the claimed invention. This change is obvious because it is a matter of design choice.
Regarding claim 14, the aforementioned combination of Yu in view of Jeng from claim 12 teaches the semiconductor package of claim 12, wherein the second surface (inside vertical surface of the recess of Yu) is substantially vertical with respect to the upper surface of the buffer chip (105 of Yu).
Regarding claim 19, the aforementioned combination of Yu in view of Jeng from claim 12 teaches the semiconductor package of claim 12.
The aforementioned combination does not explicitly teach wherein a vertical distance between the first surface and the buffer chip is 0.5 times to 1.8 times a vertical distance between an upper surface of a lowermost memory device among the plurality of memory devices and the upper surface of the buffer chip.
However, it would have been obvious to form the claimed vertical distances within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 20, the aforementioned combination of Yu in view of Jeng from claim 12 teaches the semiconductor package of claim 12, wherein the underfill fillet (701 of Yu) comprises underfill sidewalls formed around the first semiconductor device (201 of Yu), and a plurality of horizontal underfill layers connected to the underfill fillet (701 of Yu) are formed between adjacent memory devices of the plurality of memory devices (201 of Yu) and between the buffer chip (105 of Yu) and the plurality of memory devices (201 of Yu).
Regarding claim 22, the aforementioned combination of Yu in view of Jeng from claim 9 teaches the semiconductor package of claim 9, wherein the molding resin (501 and 801 of Yu) is in contact with the first surface and the second surface.
Claim(s) 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Jeng, and further in view of Du.
Regarding claim 15, the aforementioned combination of Yu in view of Jeng from claim 12 teaches the semiconductor package of claim 12, wherein the recess pattern (the space occupied 501 of Yu) extends along a periphery of a lowermost memory device (lowermost 201 of Yu) among the plurality of memory devices (201 of Yu).
The aforementioned combination does not teach wherein the first surface lies within a plane that intersects the lowermost memory device.
Du teaches a dam structure (Fig.1 106; ¶0018 of Du) that has a top surface in a plane intersecting a single semiconductor chip (Fig.1 104; ¶0018 of Du).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, for the top surface of the recess (the space occupied by dam 501 of Yu) to be within a plane intersecting the lowermost semiconductor chip (bottom 201 of Yu) to arrive at the claimed invention. This modification is obvious because shorter die stacks would require shorter dam structures, potentially in a plane intersecting the lowest semiconductor chip.
Regarding claim 16, the aforementioned combination of Yu in view of Jeng, and further in view of Du from claim 15 teaches the semiconductor package of claim 15.
The aforementioned combination does not explicitly teach wherein a width of the first surface is between 3 μm and 40 μm, and a horizontal distance between an outside surface of the underfill fillet and a side surface of the lowermost memory device is between 40 μm and 300 μm.
However, it would have been obvious to form the claimed widths within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 17, the aforementioned combination of Yu in view of Jeng, and further in view of Du from claim 15 teaches the semiconductor package of claim 15, further comprising a dam structure (501 is also a dam structure that can be formed with a molding resin; ¶0029) provided on the buffer chip (105 of Yu) and contacting the first surface (top surface of the recess of Yu) and the second surface (inside vertical surface of the recess of Yu).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J KOLB whose telephone number is (571)272-0276. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/T.J.K./ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817