DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 07/30/2026 has been entered. Claims 1 and 6 have been amended. Claims 9-12 and 16-20 are withdrawn under 37 CFR 1.142(b) as being directed to a nonelected invention. Therefore, claims 1-8 and 13-15 have been fully considered in examination.
Response to Arguments
Applicant’s arguments with respect to claims 1-8 and 13-15 have been fully considered. In view of Applicant’s amendment and upon further consideration of the record, the rejections set forth in the Office action mailed 05/12/2026 are withdrawn, and new grounds of rejection over Lin (US20200194443A1) in view of Maeng (US20220416055A1), and further in view of Kang (US20240313040A1) are set forth below. Applicant’s arguments directed to the previous combination of Kang and Maeng are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US20200194443A1, hereinafter ‘Lin’) in view of Maeng et al. (US20220416055A1, hereinafter ‘Maeng’).
Regarding claim 1, Lin teaches a semiconductor device (Fig. 1, ferroelectric memory 10), comprising:
a first electrode (Fig. 1, first electrode 12);
a second electrode on the first electrode (Fig. 1, second electrode 14 disposed on the first electrode 12);
a ferroelectric layer between the first electrode and the second electrode (Fig. 1, ferroelectric layer 16 disposed between the first electrode 12 and second electrode 14);
an anti-ferroelectric layer in contact with the ferroelectric layer (Fig. 1, antiferroelctric layer 18 in contact with the ferroelectric layer 16), wherein the ferroelectric layer and the anti-ferroelectric layer have different crystalline structures (Para [0025]-[0029] ferroelectric layer 16 is hafnium zirconium oxide (HfZrOx) in which the hafnium content is higher than the zirconium content, and anti-ferroelectric layer 18 is hafnium zirconium oxide (HfZrOx) in which the zirconium content is higher than the hafnium content). Although Lin does not expressly recite crystalline structure, ferroelectricity requires a non-centrosymmetric polar phase while anti-ferroelectricity arises from an anti-parallel dipole arrangement of a different phase; the two behaviors cannot arise from the same crystalline structure. The claimed difference is therefore inherent in the layers Lin discloses. See MPEP § 2112.01; and
wherein the second electrode, the ferroelectric layer, and the anti-ferroelectric layer are in consecutive order (Para [0023], second electrode 14, ferroelectric layer 16, and the anti-ferroelectric layer 18 arranged in that order with no intervening layer).
But Lin does not specify an insertion layer spaced apart from the ferroelectric layer and in direct contact with the anti-ferroelectric layer, wherein the insertion layer comprises silicon oxide, silicon nitride, or silicon oxynitride, and wherein the second electrode, the ferroelectric layer, the anti-ferroelectric layer, the insertion layer, and the first electrode are in consecutive order.
However, Maeng teaches an insertion layer spaced apart from the ferroelectric layer and in direct contact with the anti-ferroelectric layer (Fig. 5, additional interface layer 332 in direct contact with the anti-ferroelectric layer 321 and spaced apart from the ferroelectric layer 323 thereby),
wherein the insertion layer comprises silicon oxide, silicon nitride, or silicon oxynitride (Para [0084], additional interface layer 332 may include silicon oxide).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to dispose an insertion layer as taught by Maeng between Lin's anti-ferroelectric layer 18 and first electrode 12, such that the second electrode, ferroelectric layer, anti-ferroelectric layer, insertion layer, and first electrode are in consecutive order. The semiconductor device that involves the combination of familiar elements would suppress leakage current and prevent oxygen loss from the dielectric layers, as Maeng teaches of its interface layer 332 (Para [0080]). See MPEP § 2143(I)(C).
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Regarding claim 2, Lin in view of Maeng teaches the semiconductor device of claim 1, wherein
the anti-ferroelectric layer contains a first element (Lin, Para [0027], anti-ferroelectric layer 18 may include hafnium zirconium oxide (HfZrOx). Maeng, Para [0069], anti-ferroelectric layer 321 may include (Hf) hafnium and zirconium (Zr)),
the insertion layer contains a second element (Maeng, Para [0084], additional interface layer 332 may include silicon oxide (SiO₂) containing silicon), and the second element is different from the first element (silicon is different from both hafnium and zirconium; therefore, the second element is different from the first element).
As an inherent property of the disclosed oxides, hafnium, zirconium and silicon are each tetravalent. The first element and the second element therefore have the same valence. See MPEP § 2112.01.
Regarding claim 3, Lin in view of Maeng teaches the semiconductor device of claim 1, wherein an energy band gap of the insertion layer is greater than an energy band gap of the anti-ferroelectric layer (Maeng, Paras. [0080], [0082], the additional interface layer 332 serves as a leakage current barrier having a large conduction band offset (CBO) relative to the dielectric layer stack 320 and has a greater Pauling electronegativity than the first anti-ferroelectric layer 321). A layer presenting a large CBO while possessing a deeper valence band necessarily possesses an energy band gap greater than that of the anti-ferroelectric layer. The claimed relationship is therefore inherent. See MPEP § 2112.01.
Regarding claim 4, Lin in view of Maeng teaches the semiconductor device of claim 1, wherein the ferroelectric layer comprises an oxide material containing hafnium (Hf) or zirconium (Zr) (Lin, Paras [0025], ferroelectric layer 16 may include hafnium zirconium oxide (HfZrOx)).
Regarding claim 5, Lin in view of Maeng teaches the semiconductor device of claim 1, wherein the ferroelectric layer has a crystal structure of tetragonal phase (Lin, Para [0025], ferroelectric layer 16 may include barium titanate (BaTiO₃)). Although Lin does not expressly recite crystal structure, barium titanate possesses a tetragonal ferroelectric phase at room temperature. The claimed crystal structure is therefore an inherent property of the material Lin discloses. See MPEP § 2112.01.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select barium titanate from the ferroelectric materials expressly enumerated by Lin, as selecting a known material for its intended use is within the level of ordinary skill. See MPEP § 2144.07.
Regarding claim 6, Lin in view of Maeng teaches the semiconductor device of claim 1, wherein the anti-ferroelectric layer comprises zirconium or hafnium (Lin, Para [0027], anti-ferroelectric layer 18 may include hafnium zirconium oxide (HfZrOx)).
Regarding claim 7, Lin in view of Maeng teaches the semiconductor device of claim 1, wherein a thickness of the insertion layer is smaller than a thickness of the anti-ferroelectric layer (Maeng, Para [0081], the additional interface layer 332 may be thinner than the first anti-ferroelectric layer 321).
Regarding claim 8, Lin in view of Maeng teaches the semiconductor device of claim 1, wherein the insertion layer is between the anti-ferroelectric layer and the first electrode (Maeng, Para [0076] and Fig. 5, additional interface layer 332 disposed between the anti-ferroelectric layer 321 and first electrode 101).
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US20200194443A1) in view of Maeng (US20220416055A1), and further in view of Kang (US20240313040A1)
Regarding claim 13, Lin teaches a semiconductor device (Fig. 1, ferroelectric memory 10), comprising:
a first electrode (Fig. 1, first electrode 12);
a second electrode on the first electrode (Fig. 1, second electrode 14 disposed on the first electrode 12);
a ferroelectric layer between the first electrode and the second electrode (Fig. 1, ferroelectric layer 16 disposed between the first electrode 12 and second electrode 14); and
an anti-ferroelectric layer between the ferroelectric layer and the first electrode (Fig. 1, anti-ferroelectric layer 18 disposed between the ferroelectric layer 16 and the first electrode 12).
But Lin does not specify an insertion layer between the anti-ferroelectric layer and the first electrode, wherein the insertion layer is in direct contact with the first electrode, an energy band gap of the insertion layer being greater than an energy band gap of the anti-ferroelectric layer, wherein the ferroelectric layer has a first thickness, the anti-ferroelectric layer has a second thickness smaller than the first thickness, and the insertion layer has a third thickness smaller than the second thickness.
However, Maeng teaches an insertion layer between the anti-ferroelectric layer and the first electrode, wherein the insertion layer is in direct contact with the first electrode (Fig. 5, additional interface layer 332 disposed between the anti-ferroelectric layer 321 and first electrode 101, wherein the additional interface layer 332 is in direct contact with the first electrode 101; Para [0076]; see MPEP § 2125),
an energy band gap of the insertion layer being greater than an energy band gap of the anti-ferroelectric layer (Paras. [0080], [0082], the additional interface layer 332 serves as a leakage current barrier having a large conduction band offset (CBO) relative to the dielectric layer stack 320 and has a greater Pauling electronegativity than the first anti-ferroelectric layer 321). A layer presenting a large CBO while possessing a deeper valence band necessarily possesses an energy band gap greater than that of the anti-ferroelectric layer. The claimed relationship is therefore inherent. See MPEP § 2112.01.
and the insertion layer has a third thickness smaller than the second thickness of the anti-ferroelectric layer (Para [0081], the additional interface layer 332 may be thinner than the first anti-ferroelectric layers 321 and the ferroelectric layer 323).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to dispose an insertion layer as taught by Maeng between Lin's anti-ferroelectric layer 18 and first electrode 12, in direct contact with the first electrode 12. The semiconductor device that involves the combination of familiar elements would suppress leakage current and prevent oxygen loss from the dielectric layers, as Maeng teaches of its additional interface layer 332 (Para [0080]). See MPEP § 2143(I)(C).
Lin in view of Maeng does not specify that the ferroelectric layer has a first thickness, the anti-ferroelectric layer has a second thickness smaller than the first thickness.
However, Kang teaches a ferroelectric layer having a first thickness and an anti-ferroelectric layer having a second thickness smaller than the first thickness (Para [0062], the first and second high-k dielectric layers HK1 and HK2 may be thicker than the first and second anti-ferroelectric layers AFE1 and AFE2; Para [0061], the first high-k dielectric layer HK1 and the second high-k dielectric layer HK2 may be ferroelectric hafnium oxides).
Kang further teaches that the thickness of a hafnium zirconium oxide layer determines whether that layer exhibits a ferroelectric or an anti-ferroelectric characteristic, the critical thickness varying with the hafnium and zirconium contents (Para [0189]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form Lin's anti-ferroelectric layer 18 thinner than Lin's ferroelectric layer 16, as taught by Kang. The motivation would have been to ensure that each layer exhibits its intended polarization characteristic, which Kang teaches is governed by layer thickness. See MPEP § 2143(I)(C); MPEP § 2144.05(II)(B).
Regarding claim 14, Lin in view of Maeng and Kang teaches the semiconductor device of claim 13, wherein the ferroelectric layer has a crystal structure of tetragonal phase (Lin, Paras. [0025], ferroelectric layer 16 may include barium titanate (BaTiO₃)). Although Lin does not expressly recite crystal structure, barium titanate possesses a tetragonal ferroelectric phase at room temperature. The claimed crystal structure is therefore an inherent property of the material Lin discloses. See MPEP § 2112.01.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select barium titanate from the ferroelectric materials expressly enumerated by Lin, as selecting a known material for its intended use is within the level of ordinary skill. See MPEP § 2144.07.
Regarding claim 15, Lin in view of Maeng and Kang teaches the semiconductor device of claim 13, wherein
the anti-ferroelectric layer contains a first element (Lin, Para [0027], anti-ferroelectric layer 18 may include hafnium zirconium oxide (HfZrOx). Maeng, Para [0069], anti-ferroelectric layer 321 may include (Hf) hafnium and zirconium (Zr)),
the insertion layer contains a second element (Maeng, Para [0084], additional interface layer 332 may include silicon oxide (SiO₂) containing silicon), and the second element is different from the first element (silicon is different from both hafnium and zirconium; therefore, the second element is different from the first element).
As an inherent property of the disclosed oxides, hafnium, zirconium and silicon are each tetravalent. The first element and the second element therefore have the same valence. See MPEP § 2112.01.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAHAE KIM whose telephone number is (571)270-1844. The examiner can normally be reached M-F 9-5.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JAHAE KIM/Examiner, Art Unit 2897
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