DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/02/2025 has been entered.
Response to Amendment
The amendment filed on 12/02/2025 has been entered. Claims 1 and 13 have been amended. Claims 9-12 and 16-20 are withdrawn under 37 CFR 1.142(b) as being directed to a nonelected invention. Therefore, claims 1-8 and 13-15 have been fully considered in examination.
Response to Arguments
Applicant's arguments filed on 12/02/2025 have been fully considered but they are not persuasive. Regarding the arguments on pages 7-9, Yoo (US20180374929A1) teaches the ferroelectric layer and the anti-ferroelectric layer have different crystalline structures (Para [0024-0027], ferroelectric gate dielectric layer 120 including a ferroelectric material and interfacial dielectric layer 110 including an anti-ferroelectric material, and both have different crystalline structure), and Maeng (US20220416055A1) teaches the insertion layer is in direct contact with the first electrode (Fig. 5, additional interface layer 332 is in directly contact with first electrode 101, wherein the memory device structure include the first electrode 101/ additional interface layer 332 / anti-ferroelectric layer 321/ ferroelectric layer 323/second electrode 102 stack).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3-8 are rejected under 35 U.S.C. 103 as being unpatentable over Kang (US20240313040A1), and further in view of Yoo (US20180374929A1).
Regarding claim 1, Kang teaches a semiconductor device (Para [0048], semiconductor device), comprising:
a first electrode (Fig. 2, first electrode BE);
a second electrode on the first electrode (Fig. 2, second electrode TE on the first electrode BE);
a ferroelectric layer between the first electrode and the second electrode (Para [0064], second high-k dielectric layer HK2 between the first electrode BE and the second electrode TE);
an anti-ferroelectric layer in contact with the ferroelectric layer (Fig. 2, second anti-ferroelectric layer AFE2 in contact with the second high-k dielectric layer HK2); and
an insertion layer spaced apart from the ferroelectric layer and in direct contact with the anti-ferroelectric layer (Fig. 2, high band gap layer HBG is spaced apart from the second high-k dielectric layer HK2 and in direct contact with the second anti-ferroelectric layer AFE2).
But Kang does not teach the ferroelectric layer and the anti-ferroelectric layer have different crystalline structures.
However, Yoo teaches the ferroelectric layer and the anti-ferroelectric layer have different crystalline structures (Para [0024-0027], ferroelectric gate dielectric layer 120 including a ferroelectric material and interfacial dielectric layer 110 including an anti-ferroelectric material, and both have different crystalline structure).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the invention, to modify a semiconductor device of Kang (US20240313040A1) and further integrating the alternating stack structure of a ferroelectric memory device by Yoo (US20180374929A1). The semiconductor device that involves the combination of familiar elements can reduce the generation of a leakage current, as described in paragraph [0044] of Yoo.
Regarding claim 3, Kang in view of Yoo teaches the semiconductor device of claim 1, wherein an energy band gap of the insertion layer is greater than an energy band gap of the anti-ferroelectric layer (Para [0055] of Kang, the high band gap layer HBG may include a material having a greater energy band gap than the second anti-ferroelectric layers AFE2).
Regarding claim 4, Kang in view of Yoo teaches the semiconductor device of claim 1, wherein the ferroelectric layer comprises an oxide material containing hafnium (Hf) or zirconium (Zr) (Para [0058] of Kang, second high-k dielectric layer HK2 may include at least one of hafnium and zirconium).
Regarding claim 5, Kang in view of Yoo teaches the semiconductor device of claim 1, wherein the ferroelectric layer has a crystal structure of tetragonal phase (Para [0093] of Kang, second high-k dielectric layer HK2 may all have a tetragonal crystal structure).
Regarding claim 6, Kang in view of Yoo teaches the semiconductor device of claim 1, wherein
the anti-ferroelectric layer comprises zirconium or hafnium (Para [0048] of Kang, second anti-ferroelectric layer AFE2 may be made of or include hafnium (Hf), zirconium (Zr)), and
the insertion layer comprises silicon or aluminum (Para [0055] of Kang, the high band gap layer HBG may have a higher dielectric constant than silicon oxide and silicon nitride. high band gap layer HBG may be made of or include an aluminum-containing material).
Regarding claim 7, Kang in view of Yoo teaches the semiconductor device of claim 1, wherein a thickness of the insertion layer is smaller than a thickness of the anti-ferroelectric layer (Para [0069] of Kang, high band gap layer HGB have the smaller thickness than the second anti-ferroelectric layers AFE2’s thickness).
Regarding claim 8, Kang in view of Yoo teaches the semiconductor device of claim 1, wherein the insertion layer is between the anti-ferroelectric layer and the first electrode (Fig. 2 of Kang, high band gap layer HBG is between the second anti-ferroelectric layer AFE2 and the first electrode BE).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kang (US20240313040A1) in view of Yoo (US20180374929A1) as applied to claim 1, and further in view of Maeng (US20220416055A1).
Regarding claim 2, Kang in view of Yoo teaches the semiconductor device of claim 1, wherein the anti-ferroelectric layer contains a first element (Para [0048], second anti-ferroelectric layer AFE2 may be made of or include hafnium (Hf), zirconium (Zr)),
the insertion layer contains a second element (Para [0055], high band gap layer HBG may be made of or include an aluminum-containing material),
the second element is different from the first element (Para [0048-0055]).
But Kang does not specify the first element and the second element have a same valence.
However, Maeng teaches the first element and the second element have a same valence (Fig. 8B, both hafnium zirconium oxide and silicon oxide have same valence of +4. Para [0088], anti-ferroelectric layer includes hafnium zirconium oxide. Para [0114], interface layer 432 includes silicon oxide).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the invention, to modify a semiconductor device of Kang (US20240313040A1) and further integrating the alternating stack structure of a semiconductor device by Maeng (US20220416055A1). The combination of hafnium zirconium oxide and silicon oxide can reduce oxidation, as described in paragraph [0072] of Maeng.
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kang (US20240313040A1), and further in view of Maeng (US20220416055A1).
Regarding claim 13, Kang teaches a semiconductor device (Para [0048], semiconductor device), comprising:
a first electrode (Fig. 2, first electrode BE);
a second electrode on the first electrode (Fig. 2, second electrode TE on the first electrode BE);
a ferroelectric layer between the first electrode and the second electrode (Para [0064], second high-k dielectric layer HK2 between the first electrode BE and the second electrode TE);
an anti-ferroelectric layer between the ferroelectric layer and the first electrode (Fig. 2, second anti-ferroelectric layer AFE2 between the high-k dielectric HK2 and the first electrode BE); and
an insertion layer between the anti-ferroelectric layer and the first electrode (Fig. 2, high band gap layer HBG is between the second anti-ferroelectric layer AFE2 and the first electrode BE),
an energy band gap of the insertion layer being greater than an energy band gap of the anti-ferroelectric layer (Para [0075], the high band gap layer HBG may include a material having a greater energy band gap than the second anti-ferroelectric layers AFE2),
wherein the ferroelectric layer has a first thickness, the anti-ferroelectric layer has a second thickness smaller than the first thickness (Para [0062], second high-k dielectric layers HK2 may be thicker than the second anti-ferroelectric layers AFE2.), and the insertion layer has a third thickness smaller than the second thickness (Para [0055], The high band gap layer HBG may be thinner than each of the second anti-ferroelectric layers AFE2).
But Kang does not teach the insertion layer is in direct contact with the first electrode.
However, Maeng teaches the insertion layer is in direct contact with the first electrode (Fig. 5, additional interface layer 332 is in directly contact with first electrode 101, wherein the memory device structure include the first electrode 101/ additional interface layer 332 / anti-ferroelectric layer 321/ ferroelectric layer 323/second electrode 102 stack).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the invention, to modify a semiconductor device of Kang (US20240313040A1) and further integrating the alternating stack structure of a semiconductor device by Maeng (US20220416055A1). The semiconductor device that involves the combination of familiar elements can increase capacitance, as described in paragraph [0097] of Yoo Maeng.
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Regarding claim 14, Kang in view of Maeng teaches the semiconductor device of claim 13, wherein the ferroelectric layer has a crystal structure of tetragonal phase (Para [0093] of Kang, second high-k dielectric layer HK2 may all have a tetragonal crystal structure).
Regarding claim 15, Kang in view of Maeng teaches the semiconductor device of claim 13, wherein the anti-ferroelectric layer contains a first element (Para [0048], second anti-ferroelectric layer AFE2 may be made of or include hafnium (Hf), zirconium (Zr)),
the insertion layer contains a second element (Para [0055], high band gap layer HBG may be made of or include an aluminum-containing material),
the second element is different from the first element (Para [0048-0055]).
But Kang does not specify the first element and the second element have a same valence.
However, Maeng teaches the first element and the second element have a same valence (Fig. 8B, both hafnium zirconium oxide and silicon oxide have same valence of +4. Para [0088], anti-ferroelectric layer includes hafnium zirconium oxide. Para [0114], interface layer 432 includes silicon oxide).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAHAE KIM whose telephone number is (571)270-1844. The examiner can normally be reached M-F 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at (571) 271-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JAHAE KIM/Examiner, Art Unit 2897
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