Prosecution Insights
Last updated: April 19, 2026
Application No. 17/879,110

ORGANIC PACKAGE CORE FOR A SUBSTRATE WITH HIGH DENSITY PLATED HOLES

Final Rejection §102§103
Filed
Aug 02, 2022
Examiner
THOMPSON, TIMOTHY J
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Advanced Micro Devices, Inc.
OA Round
4 (Final)
84%
Grant Probability
Favorable
5-6
OA Rounds
2y 6m
To Grant
64%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allow Rate
232 granted / 275 resolved
+16.4% vs TC avg
Minimal -21% lift
Without
With
+-20.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
34 currently pending
Career history
309
Total Applications
across all art units

Statute-Specific Performance

§103
53.9%
+13.9% vs TC avg
§102
36.0%
-4.0% vs TC avg
§112
6.3%
-33.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 275 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This action is in response to amendment filed on June 25, 2025. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the detail of “the hollow pillar,” as recited in claims 15 and 23 (including dependent claims), must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 15 is/are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Kamperman (US 5,734,560). Regarding claim 15, Kamperman, figure 1-2, a semiconductor device comprising: a pillar having a perimeter plated with a conductive material (plated via in the bottom portion of the structure 3, see figure, column 5, line 6-23), wherein the pillar is hollow (see figure, column 4, line 60-67); dielectric material encapsulating the pillar (bottom portion of structure 3); an additional pillar that is hollow (plated via in the upper portion of the structure 3, see figure (column 4, line 60-67), wherein a perimeter of the additional pillar comprises the conductive material (plated as explained above), wherein an end of the additional pillar contacts a first conductive pad (connection pad between the two plated vias, see figure, not labeled in the figure), wherein the first conductive pad couples the end of the additional pillar to a first end of the pillar (see figure); and wherein a width of the first conductive pad is greater than a width of the end of the additional pillar, and a width of the first end pillar (see figure); and additional dielectric material encapsulating the additional pillar (upper portion of the structure 3), a surface of the additional dielectric material proximate to a first surface of the dielectric material that is proximate to the first end of the pillar (see figure). Claim(s) 15 is/are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Kresge (US 6,066,808). Regarding claim 15, Kresge, figure 14, a semiconductor device comprising: a pillar having a perimeter plated with a conductive material (plated via in the bottom portion of the structure, 302, see figure), wherein the pillar is hollow (see figure); dielectric material (390) encapsulating the pillar; an additional pillar that is hollow (plated via in the upper portion of the structure, 301, see figure), wherein a perimeter of the additional pillar comprises the conductive material (plated as explained above), wherein an end of the additional pillar contacts a first conductive pad (connection pad between the two plated vias, see figure, not labeled in the figure), wherein the first conductive pad couples the end of the additional pillar to a first end of the pillar (see figure); and wherein a width of the first conductive pad is greater than a width of the end of the additional pillar, and a width of the first end pillar (see figure); and additional dielectric material encapsulating the additional pillar (upper portion of the structure, dielectric 380), a surface of the additional dielectric material proximate to a first surface of the dielectric material that is proximate to the first end of the pillar (see figure). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 16-18 are is/are rejected under 35 U.S.C. 103 as being unpatentable over Kamperman / kresge, as applied to claim 1 above, and further in view of Farquhar (US 5,792, 375), and Kurosawa (US 4,528,072). Regarding claim 16, Kamperman / kresge or does not disclose wherein the dielectric material comprises an organic material. Kamperman is silent about the detail about material used for the dielectric. However, organic material used for a semiconductor package substrate is old and known in the art. Kresge further discloses use of organic material in the structure of a printed circuit board (Column 5, line 24-36). Farquhar (figure 1), discloses a structure with pillar formed of hollow through hole with plating and a pad in the center (between the upper dielectric layer and the lower dielectric layer, not labeled) connecting the upper pillar and the lower pillar. Farquhar, further discloses dielectric formed of organic material (column 3, line 13-25, and column 4, line 20-34). Kurosawa, figure 1C-1D, discloses a structure with pillar formed of hollow through hole with plating (though hole 10 with plating), and a pad in the center (the pad / land between the upper dielectric layer and the lower dielectric layer of the respective pillars, connecting the upper pillar and the lower pillar (see figure), Kurosawa, further discloses dielectric formed of organic material (column 3, line 45 to column 4, line 5, and column 4, line 22-26). Therefore, it would have been obvious to a person having ordinary skill in the art at the time of effective filing date of the application to provide the device of Kamperman / Kresge with dielectric formed of organic material, as taught by Farquhar, and Kurosawa, and (Kresge itself) in order to have desired insulating properties. Additionally, it has been held to be within the general skill of a worker in the art to select a known material of the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960). Regarding claim 17, the modified device of Kamperman / kresge further discloses wherein the additional dielectric material encapsulates at least two sides of the first conductive pad and a portion of a top surface of the first conductive pad, wherein the additional dielectric material comprises an organic material (obvious as explained and applied to claim 16 above). Regarding claim 18, the modified device of Kamperman / kresge further discloses a second conductive pad coupled to a second end of the pillar, the second end of the pillar opposite the first end of the pillar and the second conductive pad proximate to a second surface of the dielectric material that is opposite the first surface of the dielectric material (see figure of Kamperman, kresge, Farquhar, and Kurosawa). Claim(s) 19-21, and 23-29 is/are rejected under 35 U.S.C. 103 as being unpatentable over the modified device of Kamperman / kresge, as applied to claim 16 above, and further in view of May 2019/0363063), Nie (US 2021/0391264), and Shimizu (US 9,875,957). Regarding claim 19, the modified device of Kamperman / kresge does not discloses wherein the pillar is included in a set of hollow pillars where adjacent pillars of the set are separated by a distance between centers of adjacent pillars that does not exceed 400 microns. However, Kamperman discloses that with increased number, reduce size of electrical connection on a chip, the respective number of connection point on the substrate as to be increase, along with controlling the spacing of the connection point (column 3, line 30-40), and Kresge discloses the spacing between the pillar (through holes, as 8 to 10 mils (about 200 to 300 microns) May, figure 10, discloses a package substrate, and states that the pitch of the connection pad (bump) of the package substrate about 200 microns to about 1000 microns (paragraph 0045). Nie, figure 1, discloses a package substrate, and states that the pitch of the connection pad (114) of the package substrate greater than about 70 microns to about 150 microns. (paragraph 0031). Shimizu, figure 1-3, discloses a structure with pad (P1) including the related pillar with a pitch of 40 to 60 microns (column 10, line 15-21), and further disclose the pillars (21) in the core with a pitch of about 100 to 500 microns (column 3, line 57 to column 4, line 3). Therefore, it would have been obvious to a person having ordinary skill in the art at the time of effective filing date of the application to provide the modified device of Kamperman / Kresge with the pillar is included in a set of hollow pillars where adjacent pillars of the set are separated by a distance between centers of adjacent pillars that does not exceed 400 microns, as taught by Kresge, May, Nie, and Shimizu, in order to have increased contact density on the available space on the package substrate. Additionally, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Regarding claim 20, the modified device of Kamperman / Kresge further discloses wherein the pillar is included in a set of hollow pillars where adjacent pillars of the set are separated by a distance between centers of adjacent pillars that does not exceed 200 microns (obvious as explained and applied to claim 19 above). Regarding claim 21, the modified device of Kamperman / Kresge discloses the structure of the pillar including plating. The recitation “wherein the pillar is formed by lithographically removing portions of a resist layer and plating a perimeter of a remaining portion of the resist layer with the conductive material with the conductive material and the additional pillar is formed by lithographically removing portions of an additional resist layer and plating an additional perimeter of a remaining portion of the additional resist layer with the conductive material,” is process limitations in the product claim. Regarding claim 23, the modified device of Kamperman / Kresge further discloses an integrated circuit device comprising: a semiconductor die (obvious as disclosed by Kamperman, electronic device 11, and Shimizu, figure 4, semiconductor chip 81, and Kresge discloses connection between chip, column 1, line 16-36); and a substrate coupled to the semiconductor die, wherein the substrate comprises: a pillar having a perimeter plated with a conductive material, wherein the pillar is hollow; dielectric material encapsulating the pillar; an additional pillar that is hollow, wherein a perimeter of the additional pillar comprises the conductive material, wherein an end of the additional pillar contacting a first conductive pad, wherein the first conductive pad couples the end of the additional pillar to a first end of the pillar; and wherein a width of the first conductive pad is greater than a width of the end of the additional pillar and a width of the first end of the pillar; and additional dielectric material encapsulating the additional pillar, a surface of the additional dielectric material proximate to a first surface of the dielectric material that is proximate to the first end of the pillar (obvious as applied to claim 15 above). Regarding claim 24, the modified device of Kamperman / Kresge further discloses wherein the dielectric material comprises an organic material (obvious as applied to claim 16 above). Regarding claim 25, the modified device of Kamperman / Kresge further discloses wherein the additional dielectric material comprises an organic material (obvious as applied to claim 16 above). Regarding claim 26, the modified device of Kamperman / Kresge further discloses a second conductive pad coupled to a second end of the pillar, the second end of the pillar opposite the first end of the pillar and the second conductive pad proximate to a second surface of the dielectric material that is opposite the first surface of the dielectric material (obvious as applied to claim 18 above). Regarding claim 27, the modified device of Kamperman / Kresge further discloses wherein the pillar is included in a set of hollow pillars where adjacent pillars of the set are separated by a distance between centers of adjacent pillars that does not exceed 400 microns (obvious as explained and applied to claim 19 above). Regarding claim 28, the modified device of Kamperman / Kresge further discloses wherein the pillar is included in a set of hollow pillars where adjacent pillars of the set are separated by a distance between centers of adjacent pillars that does not exceed 200 microns (obvious as explained and applied to claim 19 above). Regarding claim 29, the modified device of Kamperman / Kresge further discloses wherein the pillar is formed by lithographically removing portions of a resist layer and plating a perimeter of a remaining portion of the resist layer with the conductive material with the conductive material and the additional pillar is formed by lithographically removing portions of an additional resist layer and plating an additional perimeter of a remaining portion of the additional resist layer with the conductive material (obvious as applied to claim 21 above). Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over the modified device of Kamperman / Kresge, as applied to claim 16 above, and further in view of Qiang (US 2011/0048776), Paul (US 2010/0307803), and Jian (US 2010/0258339). Regarding claim 22, the modified device of Kamperman does not disclose wherein the dielectric material includes low loss resin or glass filler. Jian discloses a substrate and further discloses low loss resin to improve de-lamination (paragraph 0022). Qiang discloses low loss resin composition in order to have better electrical performance (paragraph 0007). Paul, discloses a circuit assembly and further discloses a low loss resin, including glass fiber (paragraph 0079). Therefore, it would have been obvious to a person having ordinary skill in the art at the time of effective filing date of the application to provide the modified device of Kamperman / Kresge with the dielectric material includes low loss resin or glass filler, as taught by Jian, Paul, and Qiang, in order to improve electrical and mechanical properties. Additionally, it has been held to be within the general skill of a worker in the art to select a known material of the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960). Regarding claim 30, the modified device of Kamperman / Kresge further discloses wherein the dielectric material includes low loss resin or glass filler (obvious as applied to claim 22 above). Response to Arguments Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument / new explanation of the rejection. Additionally, regarding the figure objection, the objection is maintained. The applicant argues that the originally filed figures provide clear understanding for an embodiment that includes pillars 115. Paragraph [0040] (as well as multiple other paragraphs) of the original specification describes additional embodiments in which the pillars 115 are hollow (versus being solid). Regarding these additional embodiments, Applicant respectfully submits that additional drawings are not necessary for understanding that a pillar may be hollow. Said another way, Applicant respectfully submits that an express illustration that pillars 115 are hollow is not necessary for understanding by one of ordinary skill in the art of the subject matter to be patented. This is not found to be persuasive, as the detail of the connection of the hollow pillar with the pad is not clear. Regarding the pad of Kamperman, the argument that the Kamperman discloses the via flared out to match that to the pad, is not found to be persuasive. This is a structural claim. How the structure is formed would not add any structural limitation. Additionally, such a process limitation defines the claimed invention over the prior art to the degree that it defines the product itself. A process limitation cannot serve to patentably distinguish the product over the prior art, in the case that the product is same as, or obvious over the prior art. See Product-by-Process in MPEP § 2113 and 2173.05(p) and In re Thorpe, 777 F.2d 695, 227 USPQ 964, 966 (Fed. Cir. 1985). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Davis (US 5,280,414), figure 11, discloses a structure of a device with a fist pillar (pillar in layer 50), and a second pillar (pillar in layer 20), and a pad in the middle, connecting the first pillar to the second pillar. Davis further discloses organic material for the dielectric layers (column 1, line 19-39). Chen (US 5,442,144), figure 1, partial figure, discloses a structure of a device with a fist pillar (pillar in bottom layer 40), and a second pillar (pillar in the upper layer 40), and a pad in the middle, connecting the first pillar to the second pillar. Davis further discloses organic material for the dielectric layers (PTFE, column 5, line 25-40). Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ISHWARBHAI B PATEL whose telephone number is (571)272-1933. The examiner can normally be reached M-F: 8:30 AM-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Thompson can be reached at 571 272 2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ISHWARBHAI B PATEL/ Primary Examiner, Art Unit 2847 IBP / September 11, 2025
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Prosecution Timeline

Aug 02, 2022
Application Filed
Apr 15, 2024
Examiner Interview (Telephonic)
Apr 18, 2024
Non-Final Rejection — §102, §103
Jul 19, 2024
Response Filed
Oct 18, 2024
Final Rejection — §102, §103
Jan 22, 2025
Request for Continued Examination
Jan 27, 2025
Response after Non-Final Action
Feb 04, 2025
Non-Final Rejection — §102, §103
Jun 25, 2025
Response Filed
Sep 12, 2025
Final Rejection — §102, §103 (current)

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Prosecution Projections

5-6
Expected OA Rounds
84%
Grant Probability
64%
With Interview (-20.6%)
2y 6m
Median Time to Grant
High
PTA Risk
Based on 275 resolved cases by this examiner. Grant probability derived from career allow rate.

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