DETAILED ACTION
This action is responsive to the amendment filed 17/879,460. The amendment has been entered.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “defect regions” in the first and second SiC layers that are disposed exclusively within or above the first and second trenches must be shown or the feature(s) canceled from the claim(s). If the defect region is 127 according to Applicant’s remarks, this region is not formed in the second SiC layer nor are these regions formed “exclusively within or above” the trenches. Based on the figures and specification (¶17), region 127 is formed only in the first SiC layer, and region 127 is not exclusively within or exclusively above the trenches, for every trench the region 127 is partially within and also partially extends above the trenches. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-3, 5-10, and 18-19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 was previously amended to recite “…wherein epitaxially forming the first and second SiC layers forms defect regions in the first and second SiC layers that are disposed exclusively within or above the first and second trenches…”. This prior amendment added new matter. The claimed defect regions refer to the regions having the defects, and the recited disposed exclusively is intended to mean the defects are only formed in and above the trenches and nowhere else, i.e. defects/defect regions are excluded from the region between the trenches. This treatment of a “defect region” is based on the plain meaning of the terms, i.e. a region comprising a defect, since Applicant has not specifically redefined the term in the specification. The exclusive location is not supported by the originally filed specification. The specification states the regions between the trenches are substantially defect free (¶19), meaning there are still defects in the region between the trenches, i.e. a defect region. In light of the specification and claims, this is consistent with Applicant’s use of “defect regions”. Substantially defect free does not entirely exclude regions with defects from being outside the trench regions. The recited “substantially” means subjectively, the region between the trenches is for the most part or approximately free of defects, according to some unknown defect threshold wherein Applicant considers something to become substantially free.
Applicant argues (p. 8) the claimed “defect regions” are the regions 127 in Fig. 3. However, the claim recites “…forms defect regions in the first and second SiC layers that are disposed exclusively within or above the first and second trenches…”. According to ¶17 of the specification:
“[0017] Epitaxially forming the first SiC layer 114 may form defect regions 127 within or above the first and second trenches 106, 108. In these defect regions 127, the SiC material may have a polycrystalline or amorphous crystal structure. This is due to the lattice mismatching and convergence of the first SiC layer 114 as the step-flow grown material spills into the first and second trenches 106, 108. Separately or in combination, voids may form in these defect regions 127, due to the growth pattern of the step-flow grown material within the first and second trenches 106, 108. Separately or in combination, the semiconductor material in the defect regions 127 may be monocrystalline material with a high density of dislocations and/or other crystal defects.”
According to ¶17, “epitaxially forming the first SiC layer 114 may form defect regions 127 within or above the first and second trenches 106, 108”, clearly means the defect regions are formed when the first SiC layer 114 is formed in the trenches, not the second SiC layer, in fact there is no additional discussion of forming “defect regions” with respect to the second SiC layer 120, so in light of Applicant’s remarks and the description of 127, the “defect regions in the first and second SiC layers” is unsupported new matter. Additionally, it is noted ¶19 recites:
“Due to the defect regions 127 that form in the subjacent material, some crystalline defects may propagate into regions 130 of the second SiC layer 120 that are above the first and second trenches 130.”
Applicant does not refer to region 130 as a “defect region”, however one would need to construe a region comprising a defect as a “defect region” based on the plain meaning, and if the claimed “…forms defect regions in the first and second SiC layers…” is supported, then region 130 comprising a defect must also be construed as a “defect region”. If a region comprising a defect is a “defect region”, then the substantially defect free regions discussed above, are also defect regions. If, according to Applicant’s remarks, only regions 127 are the “defect regions”, then the limitation regarding forming defect regions in the first and second SiC layers is also unsupported new matter.
If it is Applicant’s intent to simply describe the “regions” of SiC layers within and/or above the trenches, regardless of any defects, then Applicant should simply recite “regions” (or a first region, second region, etc).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-3, 5, 8-10, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Powell et al. (US 5,915,194) in view of Neudeck et al. (US 2004/0144301), all of record, and Bai et al. (US 2008/0099785), all of record.
(Re Claim 1) Powell teaches a method of forming a semiconductor device, the method comprising (see Figs. 7-8 and col 12 line 4 – col 13 line 34):
providing a base substrate comprising SiC and a growth surface extending along a plane that is angled relative to a first crystallographic plane of the SiC from the base substrate (Fig. 8: 24);
forming first and second trenches in the base substrate that extend from the growth surface into the base substrate (grooves 62 are formed in a grid across the substrate to define mesas where the SiC is grown, Fig. 4, col 8 lines 1-38, col 11 lines 29-44, col 14 lines 11-50);
epitaxially forming a first SiC layer on the growth surface of the base substrate by a step-controlled epitaxy technique (Figs. 7-8: 6H-SiC); and
epitaxially forming a second SiC layer (3C-SiC) on the first SiC layer,
wherein the first SiC layer is a layer of α-SiC (6H polytype), and
wherein the second SiC layer is a layer of β-SiC (3C polytype).
Powell is silent regarding wherein epitaxially forming the first and second SiC layers forms defect regions in the first and second SiC layers that are disposed exclusively within or above the first and second trenches, and wherein forming the first and second SiC layers comprises selecting size parameters of the first and second trenches to reduce defect formation and/or void formation within the second SiC layer in between the defect regions. Also see §112 rejection above, as claimed the “defect regions” and exclusive locations thereof may simply be the regions of SiC material within/above the trenches and these regions do not actually require defects. The claim language does not preclude this treatment. Regardless, Powell selects dimensions of the grooves 62 around each device region, Powell does not discuss defect regions in or above the grooves, but rather only with respect to mitigating defects in the device regions between grooves enabling epitaxially grown, high quality, low defect regions, i.e. substantially defect free regions. With respect to Powell, epitaxial SiC will still be deposited within the grooves and on the mesas during the growth process, and one may simply identify the regions in or above the grooves as defect regions, noting the grooves may be formed by etching or using a dicing saw, each resulting in a damaged surface, which will readily cause a variety of defects to occur. Related art from Neudeck discusses how low quality SiC is deposited in the trenches which at least will not be lattice matched when 3C is deposited and may be mixed polytype and thus obviously having defects (Figs. 1A-1G and ¶¶30, 55-58, 64-65). Neudeck further notes the importance of selecting appropriate trench dimensions to ensure the low quality SiC does not extend up to reach the defect free SiC, thereby confining the low quality SiC having defects within the trench regions (Id.). Related art from Bai teaches aspect ratio trapping wherein epitaxially growing SiC in a trench that is not lattice matched to the substrate, as is the case in Powell and Neudeck, defects will propagate from the mismatched interface along crystal planes and will terminate on sidewalls of the trenches having appropriate aspect ratios (see Figs. 1-6 and supporting text). In view of Neudeck and Bai, a PHOSITA would recognize that the grooves 62 will obviously contain SiC with defects while the SiC epi grown on the mesas will be substantially defect free and that the groove dimensions affect how defects are confined to the groove regions by either allowing the grooves to be large enough such that either the defects terminate on sidewalls and/or the low quality epi simply does not grow out of the trenches. In addition, with respect to the regions between the trenches, none of Neudeck, Bai, or Powell teaches the formation of voids within these regions.
(Re Claim 2) wherein the first SiC layer is formed to comprise an upper surface that originates at a first corner of the first trench, wherein the upper surface of the first SiC layer is aligned with a first crystallographic plane of the SiC from the first SiC layer, and wherein the second SiC layer forms directly on the upper surface of the first SiC layer (Fig. 8).
(Re Claim 3) wherein the first SiC layer is formed to cover the growth surface of the base substrate in between the first and second trenches (Fig. 8).
(Re Claim 5) wherein epitaxially forming the first SiC layer forms defect regions within or above the first and second trenches.
While defects formed within or above the trenches is not explicitly recited by Powell, the disclosed grooves are formed by a dicing saw blade which causes damage. When growing epi on/in the groove regions damaged by the dicing blade, dislocation defects will be formed in the SiC formed in the grooves (col 14 lines 11-50).
(Re Claim 8) wherein the step-controlled epitaxy technique grows the α-SiC in a growth direction that is parallel to the first crystallographic plane, and wherein the first trench comprises a first sidewall that is nearest to the second trench, and wherein the first sidewall extends transversely to the growth direction (see Figs. 4 and 8, col 11 lines 29-44 and col 14 lines 11-50).
(Re Claim 9) wherein the first sidewall extends at an angle that is within 30 degrees of perpendicular to the growth direction (Figs. 4 and 8: the trenches 62 formed by the 25 µm dicing blade having vertical sidewalls are within 30° of the growth direction being perpendicular to the off-axis surface having a tilt of less than 1°).
(Re Claim 10) wherein the first SiC layer is a layer of 2H-SiC, 4H- SiC, or 6H-SiC (4H or 6H).
(Re Claim 16) wherein selecting geometric parameters of the first and second trenches comprises selecting size parameters of the first and second trenches to reduce defect formation and/or void formation of the SiC material from the first SiC layer.
See discussion above, Neudeck discuss how the trenches are dimensioned to ensure the low quality epi with the defects is confined to the trenches and Bai further recognizes that the trench dimensions (e.g. the aspect ratio) can be selected to trap defects within the trenches. A PHOSITA would find it obvious to select trench dimensions according to the prior art teachings to determine which approach results in fewer or no defects in the SiC epi in the device regions.
(Re Clam 18) wherein epitaxially forming the first and second SiC layers forms defect regions above the first and second trenches.
While defects formed within or above the trenches is not explicitly recited by Powell, the disclosed grooves are formed by a dicing saw blade which causes damage. When growing epi on/in the groove regions damaged by the dicing blade, dislocation defects will be formed in the SiC formed in the grooves (col 14 lines 11-50).
(Re Claim 19) wherein crystalline defects propagate into regions of the second SiC layer that are above the first and second trenches.
While defects formed within or above the trenches are not explicitly recited by Powell, the disclosed grooves are formed by a dicing saw blade which causes damage. When growing epi on/in the groove regions damaged by the dicing blade, dislocation defects will be formed in the SiC formed in the grooves (col 14 lines 11-50). Defects propagating through the first layer and reaching the interface where the second layer is growing have every opportunity to continue propagating into the second layer. Nothing in Powell’s process (or Applicant’s process) influences whether or not a defect propagating through one epilayer of SiC can or cannot extend into the next epilayer of SiC. This defect propagation will flow naturally from performing the claimed epitaxial growth sequence disclosed by Powell, whether expressly stated or not. It is obvious performing the same process as claimed will produce the same results.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Powell et al. (US 5,915,194) in view of Spencer et al. (US 2008/0203399) and Wirths et al. (US 2022/0028976), all of record.
(Re Claim 17) Powell teaches a method of forming a semiconductor device, the method comprising (see Figs. 7-8 and col 12 line 4 – col 13 line 34):
providing a base substrate comprising SiC and a growth surface extending along a plane that is angled relative to a first crystallographic plane of the SiC from the base substrate (Fig. 8: 24);
forming first and second trenches in the base substrate that extend from the growth surface into the base substrate (grooves 62 are formed in a grid across the substrate to define mesas where the SiC is grown, Fig. 4, col 8 lines 1-38, col 11 lines 29-44, col 14 lines 11-50);
epitaxially forming a first SiC layer on the growth surface of the base substrate by a step-controlled epitaxy technique (Figs. 7-8: 6H-SiC); and
epitaxially forming a second SiC layer (3C-SiC) on the first SiC layer,
wherein the first SiC layer is a layer of α-SiC (6H polytype), and
wherein the second SiC layer is a layer of β-SiC (3C polytype),
wherein the second SiC layer is formed to comprise a monocrystalline region of the β-SiC that is disposed directly on the upper surface of the first SiC layer (Fig. 8) and is laterally between the first and second trenches (the SiC epi is grown on the mesas defined by the trenches 62).
With respect to the forming an active semiconductor device in the monocrystalline region of the β-SiC, and wherein the active semiconductor device is a heterojunction device comprising a heterojunction between the first SiC layer and the second SiC layer, Powell clearly teaches the SiC epitaxial layers are grown for the purpose of forming active devices, e.g. a MISFET or HEMT, etc. (see col 1 line 14-col 3 line 32). Thus, in view of Powell, alone, a PHOSITA would find it obvious to form an active device, e.g. a transistor, in the low defect SiC epi layers comprising the heterojunction as this will result in devices having improved breakdown and reduced leakage. A PHOSITA may be further motivated to look to related art to teach details of heterojunction devices, such as the MISFET or HEMT disclosed by Powell, comprising heterojunctions and showing the locations of heterojunctions in such devices. Related art from Spencer shows one can form a HEMT using Powell’s heterojunction to form the 2DEG channel region (see Fig. 8). Related art from Wirths shows how Powell’s heterojunction can be used in the active/channel region of a vertical power MOSFET (see Figs. 3A-3F). In view of Spencer and Wirths, a PHOSITA would recognize that the transistors discussed by Powell can advantageously utilize the properties of the heterojunction as part of the active device structure.
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive. First, Applicant argues the defect regions are the regions 127 in Fig. 3, however this interpretation in view of the specification, is also new matter. If one were to limit the “defect regions” to only regions 127 according to Applicant’s remarks, then the claimed “…forms defect regions in the first and second SiC layers…” is unsupported new matter in view of ¶17 (also see §112 discussion above). In light of the plain meaning of the terms “defect regions”, understood to be any region comprising a defect, “defect regions…disposed exclusively within or above the first and second trenches” is new matter since other regions of the device still comprise defects, i.e. defect regions (re: substantially defect free locations). This interpretation is required if one is to interpret region 130 comprising a defect as part of the “defect region”. The Examiner maintains the §112(a) rejections. If Applicant’s intent is to simply describe regions within and above the trenches, regardless of any defects, then Applicant should simply claim these as “regions” rather than defect regions. Applicant argues (p. 8) the claimed “defect regions” are the regions 127 in Fig. 3. However, the claim recites “…forms defect regions in the first and second SiC layers that are disposed exclusively within or above the first and second trenches…”. According to ¶17 of the specification:
“[0017] Epitaxially forming the first SiC layer 114 may form defect regions 127 within or above the first and second trenches 106, 108. In these defect regions 127, the SiC material may have a polycrystalline or amorphous crystal structure. This is due to the lattice mismatching and convergence of the first SiC layer 114 as the step-flow grown material spills into the first and second trenches 106, 108. Separately or in combination, voids may form in these defect regions 127, due to the growth pattern of the step-flow grown material within the first and second trenches 106, 108. Separately or in combination, the semiconductor material in the defect regions 127 may be monocrystalline material with a high density of dislocations and/or other crystal defects.”
According to ¶17, “epitaxially forming the first SiC layer 114 may form defect regions 127 within or above the first and second trenches 106, 108”, clearly means the defect regions are formed when the first SiC layer 114 is formed in the trenches, not the second SiC layer, in fact there is no additional discussion of forming “defect regions” with respect to the second SiC layer, so in light of Applicant’s remarks and the description of 127, the “defect regions in the first and second SiC layers” is unsupported new matter. Additionally, it is noted ¶19 recites:
“Due to the defect regions 127 that form in the subjacent material, some crystalline defects may propagate into regions 130 of the second SiC layer 120 that are above the first and second trenches 130.”
Applicant does not refer to region 130 as a “defect region”, however one would need to construe a region comprising a defect as a defect region based on the plain meaning, and if the claimed “…forms defect regions in the first and second SiC layers…” is supported, then region 130 comprising a defect must also be construed as a defect region, along with any other region comprising a defect, including the substantially free regions. If, according to Applicant’s remarks, only regions 127 are to be construed as the defect regions, then the limitation regarding the defect regions in both of the SiC layers is unsupported.
Next, Applicant argues the limitations “…wherein epitaxially forming the first and second SiC layers forms defect regions in the first and second SiC layers that are disposed exclusively within or above the first and second trenches, and wherein forming the first and second SiC layers comprises selecting size parameters of the first and second trenches to reduce defect formation and/or void formation within the second SiC layer in between the defect regions…” in the rejection of claim 1 are not met. The Examiner respectfully disagrees, see rejections above. With respect to the trenches, all of Powell, Bai, and Neudeck form trenches, and all are directed to forming substantially defect free device regions. Powell recognizes processes such as dicing can cause crystal damage leading to nucleation points for defects in subsequent epilayers (e.g. see col 11 line 14-col 12 line 18, col 14 lines 11-50). Powell forms grooves 62 having selected size parameters, using a dicing saw, and forms high quality/low defect SiC in the device regions between the trenches. From Powell, alone, a PHOSITA would recognize that the damaged groove surfaces from the saw provide nucleation points for defects in subsequent SiC growth, and thus the trenches would obviously contain more defects than the high quality/low defect device regions between the trenches. This occurs simply based on the trenches having vertical sidewalls and for any defects propagating horizontally or along any crystal plane(s) intersecting a trench sidewall, also see Bai’s entire disclosure. Powell is obviously already benefiting from defect mitigating trenches whether expressly stated or not. The prior art from Bai and Neudeck simply teaches there are different mechanisms for mitigating defects with respect to the trenches, thus a PHOSITA could select trench size parameters to mitigate defects according to either of Bai or Neudeck. Next it is noted the recited “…to reduce defect formation…” describes intent without actually requiring the selected size parameters to be effective or successful in actually reducing defects. Selecting a size of something with the intent that it produces a desired result, e.g. to reduce defects, does not guarantee the result. This only establishes a desire or intent behind a selection of size parameters. In view of the teachings of Bai and Neudeck, a PHOSITA would find it obvious to select size parameters for the known benefits of reducing defects, regardless of the underlying mechanism.
With respect to claim 17, Powell teaches epitaxially forming the SiC layers as claimed. It is noted Applicant mischaracterizes Powell’s disclosure and first SiC layer (remarks p. 14). The Examiner maintains a PHOSITA would find it obvious to form a heterojunction device, such as a MISFET or HEMT in the high quality, low defect, SiC heterojunction formed (e.g. see Powell’s discussion in col 1-col 7). Regardless, a PHOSITA may also look to related art to teach suitable heterojunction devices and both Spencer and Wirths each teach forming devices with hetreojunctions having a lower 4H/6H polytype and then a 3C polytype layer and these layers are formed in the active parts of a transistor, each heterojunction comprising the claimed combination of layers. Spencer and Wirths teach device examples that may be formed using Powell’s SiC heterojunction layers. The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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/ERIK T. K. PETERSON/Primary Examiner, Art Unit 2898