DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 10,354,605) in view of Chen (US 2013/0113686) and Kajita (US 11,036,107) and further in view of Oh (US 10,133,138).
Regarding claim 1, Lee teaches display device comprising: first and second unit pixels adjacent to each other in a first direction (Fig. 1 shows plurality of pixels), and each comprising first to third pixels (Fig. 4 shows RGB pixels of odd pixel group. It is therefore understood that even pixel groups would also be ); a first voltage line on a first side of each of the first and second unit pixels, and extended in a second direction crossing the first direction ( Fig. 4 Vcom); a data line on a second side of each of the first and second unit pixels, and extended in the second direction(Fig. 4 shows each group comprises data lines); first gate lines between the first side of the first unit pixel and the second side of the second unit pixel, and extended in the second direction (Fig. 4 and 6 odd vertical gate lines VG1-VG5); and a second gate line connected to at least one of the first gate lines, and extended in the first direction (Figs. 4 and 6 odd horizontal gate lines G1-G5). Although Lee teaches the limitations as discussed above, he does not teach first and second unit pixels adjacent to each other in a first direction, and each comprising first to third pixels and with no other unit pixels therebetween and a plurality of first gate lines where a number of first gate lines between the first unit pixel and the second unit pixel being equal to or greater than two.
However in the field of manufacturing a display panel, Chen teaches teach first and second unit pixels adjacent to each other in a first direction, and each comprising first to third pixels and with no other unit pixels therebetween and a plurality of first gate lines where a number of first gate lines between the first unit pixel and the second unit pixel being equal to or greater than two (Figs. 3 and 7 show a display device 12 with unit pixels RGB between data lines DLn and DLn+1, Horizontal gate lines GL and two vertical gate lines GFLq for the unit pixels.).
Therefore it would have been obvious to one of ordinary skill in the art to combine the device as taught by Lee with method of manufacturing as taught by Chen for rearranging parts. This combination would provide an improved display quality and reduce the cost of manufacturing as taught by Chen [0007-0008]. Although the combination teaches the limitations as discussed above, they fail to teach disposing gate line between all of the first to third pixels of the first pixel unit and all of the first to third pixels of the second pixel unit.
However in the field of manufacturing a display panel, Kajita teaches a touch display panel where the vertical gate lines (VG) are disposed between all of the first to third pixels of the first pixel unit and all of the first to third pixels of the second pixel unit (Fig. 2 show gate lead line VG disposed between pixel groups RGB)..
Therefore it would have been obvious to one of ordinary skill in the art to combine the device as taught by Lee with method of manufacturing as taught by Chen, and the method of disposing gate lines Kajita, since rearranging parts of an invention involves only routine skill in the art In re Japikse, 86 USPQ 70. This combination would provide an improved display quality and reduce the cost of manufacturing as taught by Chen [0007-0008]. Although the combination teaches the limitations as described above, they fail to teach wherein the data line is more adjacent to the second unit pixel than the plurality of first gate lines, and wherein the plurality of first gate lines are more adjacent to the first unit pixel than the data line.
However in the field of manufacturing a display device Oh teaches a design wherein the data line is more adjacent to a second unit pixel than the plurality of first gate lines(Fig. 3 DL1 is more adjacent to a unit pixel PX 11 than gate lines GL_3-GL_5)) , and wherein the plurality of first gate lines are more adjacent to the first unit pixel than the data line(Fig. 3 gate lines GL_3-GL_5 is more adjacent to a unit pixel PX 13 than data line PX13).
Therefore it would have been obvious to one of ordinary skill in the art to combine the device as taught by Lee with method of manufacturing as taught by Chen, and the method of disposing gate lines Kajita and the method of gate line arrangement as taught by Oh, since rearranging parts of an invention involves only routine skill in the art In re Japikse, 86 USPQ 70. This combination would provide an improved display quality and reduce the cost of manufacturing as taught by Chen [0007-0008].
Regarding claim 2, Lee teaches wherein a number of first gate lines between the first unit pixel and the second unit pixel is an odd number equal to or greater than three ((Fig. 4 and 6 odd vertical gate lines VG1-VG5).
Regarding claim 3, Lee teaches wherein the first gate lines are between the first voltage line connected to the first unit pixel and the data line connected to the second unit pixel((Fig. 4 and 6 odd vertical gate lines VG1-VG5 are connected between D1 and Vcom. Fig. 1 shows how the pixels are adjacent).
Regarding claim 4, Lee discloses the claimed invention except for third and fourth unit pixels arranged adjacent to each other in the first direction on the second side of the first unit pixel or on the first side of the second unit pixel, wherein other first gate lines are between a first side of the third unit pixel and a second side of the fourth unit pixel.
However would have been obvious to one having ordinary skill in the art at the time the invention was made to for third and fourth unit pixels arranged adjacent to each other in the first direction on the second side of the first unit pixel or on the first side of the second unit pixel, wherein other first gate lines are between a first side of the third unit pixel and a second side of the fourth unit pixel, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Regarding claim 5, Lee discloses the claimed invention except for wherein the first gate line and the additional first gate lines are not between the second and third unit pixels.
However would have been obvious to one having ordinary skill in the art at the time the invention was made to for the first gate line and the additional first gate lines are not between the second and third unit pixels, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Regarding claim 6, Lee in view of Chen disclose the claimed invention except for wherein a number of additional first gate lines between the third unit pixels and the fourth unit pixel is an odd number equal to or greater than three.
However because Lee and Chen teach disposing multiple first gate lines for pixel unit, it would have bene an obvious matter of design choice to dispose a number of additional first gate lines between the third unit pixels and the fourth unit pixel is an odd number equal to or greater than three, since the applicant has not disclosed that the having odd number of gate lines being equal to or greater than three solves any stated problem or is for any particular purpose and it appears that the invention would perform will with any number of odd gate lines.
Allowable Subject Matter
Claims 7-11 and 13-20 are allowed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRE L MATTHEWS whose telephone number is (571)270-5806. The examiner can normally be reached Mon-Fri 9:00-6:00.
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/ANDRE L MATTHEWS/ Primary Examiner, Art Unit 2621
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