DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 22-25 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 22 recites “a first package (104, Figs. 2 or 3) comprising a first integrated device (105, Figs. 2 or 3)”, “a first metallization portion (140, Figs. 2 or 3) coupled to the first integrated device”, “a second integrated device (106, Figs. 2 or 3)”, and “forming an encapsulation layer (108, Figs. 2 or 3) over the first package (104) and the second integrated device (106)”. The claim further recites “forming a second metallization portion over the second integrated device, the first metallization portion of the first package and the encapsulation layer, wherein the second metallization portion comprises: at least one second dielectric layer; and a second plurality of metallization interconnects”. Now, as shown in Figs. 2 or 3, the 2nd integrated device is 106, 1st metallization is 140, and the encapsulation layer is 108. The only metallization portion shown in Figs. 2 or 3, that is formed over the second integrated device (106), the first metallization portion (140) of the first package (104) and the encapsulation layer (108), is the layer 282+224 (282 is metal interconnects and 224 is dielectric), and hence the second metallization portion has to be 282+224. The newly amended claim further recites, “wherein some metallization interconnects from the second plurality of metallization interconnects directly touch some metallization interconnects from the first plurality of metallization interconnects, and wherein interconnects from the second integrated device directly touch the second plurality of metallization interconnects of the second metallization portion.” As described above, the second metallization portion has to be 282+224, and as shown in the devices in Figs. 2 or 3, the second metallization portion 282+224 do not directly touch the first metallization portion (140), thus introducing new matter and hence the claim is rejected. Additionally, the interconnects from the second integrated device (106) do not directly touch the second metallization portion 282+224. Thus, the newly amended claim introduces new matter and hence rejected.
Claims 23-25 depend from claim 22 and are rejected at least for the reasons above.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim 1-6, 8-15 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2020/0144224 A1, of record).
Re Claim 1, Lin teaches a package (Fig. 23h) comprising:
a first integrated device (159-2, Fig. 23h, paras [0246] and [0424], also see Fig. 15B for details);
a first metallization portion (marked “1st metallization” in annotated Fig. 23h below, which includes element 200 as shown in Fig. 17G, para [0367]) coupled to the first integrated device (159-2), wherein the first metallization portion comprises (note that element 200 within “1st metallization” includes redistribution layer 561 which is similar to interconnection layer 20 in Fig. 14A, para [0367]):
at least one first dielectric layer (12, Fig. 14A, para [0367]); and
a first plurality of metallization interconnects (metal pads 6a + vias 157 + interconnection metal layers 6 within RDL 561, see “1st metallization” in annotated Fig. 23h below, para [0409], also see Fig. 17G and para [0367] for details within element 200);
a second integrated device (159-1, Figs. 23h, para [0424]);
a second metallization portion (marked “2nd metallization” in annotated Fig. 23h below) coupled to the second integrated device (159-1) and the first metallization portion (“1st metallization”), wherein the second metallization portion (“2nd metallization”) comprises:
at least one second dielectric layer (12 within layer 20 of “2nd metallization”, compare Fig. 23h and Fig. 14A, para [0326]); and
a second plurality of metallization interconnects (metal pads 6a + interconnection metal layers 6, within “2nd metallization”, Fig. 23h, paras [0409] and [0326]); and
wherein some metallization interconnects from the second plurality of metallization interconnects (metal pads 6a within “2nd metallization”) directly touch (see Fig. 23h) some metallization interconnects from the first plurality of metallization interconnects (metal pads 6a within “1st metallization”), and
wherein interconnects (marked “interconnects from 2nd device” in annotated Fig. 23h below) from the second integrated device (159-1) directly touch (see Fig. 23h) the second plurality of metallization interconnects of the second metallization portion (metal pads 6a within “2nd metallization”); and
an encapsulation layer (“second 565”, Fig. 23h, para [0424], see annotated Fig. 23h below) coupled to the first metallization portion (“1st metallization”), the second integrated device (159-1) and the second metallization portion (“2nd metallization”, see annotated Fig. 23h below).
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Re Claim 2, Lin teaches the package of claim 1,
wherein the first metallization portion (“1st metallization”) includes a first redistribution portion (RDL 561 within element 200 of “1st metallization”, see claim 1 above),
wherein the first plurality of metallization interconnects (metal pads 6a + vias 157 + interconnection metal layers 6 within RDL 561, see claim 1 above) includes a first plurality of redistribution interconnects (interconnection metal layers 6 within RDL 561, compare Fig. 23h, Fig. 17G and 14A),
wherein the second metallization portion (“2nd metallization”) includes a second redistribution portion (RDL 20 of “2nd metallization”, compare Figs. 23h and 14A, para [0367]), and
wherein the second plurality of metallization interconnects (metal pads 6a + interconnection metal layers 6, within “2nd metallization”, see Fig. 23h) includes a second plurality of redistribution interconnects (interconnection metal layers 6 within “2nd metallization”, compare Figs. 23h and 14A).
Re Claim 3, Lin teaches the package of claim 2,
wherein a first portion of a first redistribution interconnect from the first plurality of redistribution interconnects, includes a side profile that has a U-shape or a V shape (see inset of Fig. 14A), and
wherein a second portion of a second redistribution interconnect from the second plurality of redistribution interconnects, includes a side profile that has a U-shape or a V shape (see inset of Fig. 14A).
Re Claim 4, Lin teaches the package of claim 3, wherein a bottom portion of the first redistribution portion (bottom portion of RDL 561 within element 200 of “1st metallization”) is directly coupled to a bottom portion of the second redistribution portion (bottom portion of RDL 20 of “2nd metallization”, see Fig. 23h).
Re Claim 5, Lin teaches the package of claim 1, further comprising a first encapsulation layer (“first 565” annotated in Fig. 23h above, also see Fig. 17G and para [0380]) that is coupled to the first integrated device (159-2, Fig. 23h),
wherein the encapsulation layer (“second 565”, see claim 1 above) is a second encapsulation layer that is coupled to the first encapsulation layer (“first 565”), and
wherein the first integrated device (159-2) is coupled to the first metallization portion (“1st metallization”) through a plurality of solder interconnects (563, Fig. 17G, para [0385], where the bonded contacts may be solder bumps, paras [0047] – [0048]).
Re Claim 6, Lin teaches the package of claim 1, further comprising a plurality of through mold vias (582, Fig. 23h, para [0424]) that are coupled to the second metallization portion (“2nd metallization”), wherein the plurality of through mold vias are located in the encapsulation layer (“second 565”).
Re Claim 8, Lin teaches the package of claim 1, further comprising:
a plurality of through mold interconnects (582, Fig. 23h, para [0424]) that extend through a thickness of the encapsulation layer (“second 565”), wherein the plurality of through mold interconnects are coupled to the second metallization portion (“2nd metallization”);
a plurality of interconnects (27, Fig. 23h, para [0424]) coupled to a surface of the encapsulation layer (top surface of “second 565”); and
a third integrated device (“upper 159-1”, Fig. 23i) coupled to the plurality of interconnects (27) through a plurality of solder interconnects (interconnects 583+112 between “upper 159-1” and “lower 159-1”, see Fig. 23i, para [0428], also see Fig. 23f where solder 112 is marked), where the bonded contacts may be solder bumps, para [0428]).
Re Claim 9, Lin teaches the package of claim 8, wherein the third integrated device (“upper 159-1”, Fig. 23i) is configured to be electrically coupled to the first integrated device (159-2, Figs. 23h-21i) through an electrical path (see Fig. 23i) that includes at least one solder interconnect from the plurality of solder interconnects (interconnects 583+112 between “upper 159-1” and “lower 159-1”, see claim 8 above, Fig. 23i), at least one interconnect from the plurality of interconnects (metal interconnects 27, Fig. 23h-23i), at least one interconnect from the plurality of through mold interconnects (via interconnects 582, Figs. 23h-23i), at least one metallization interconnect from the second plurality of metallization interconnects (metal layers 6 within “2nd metallization”) and at least one metallization interconnect from the first plurality of metallization interconnects (metal layers 6 within “1st metallization”).
Re Claim 10, Lin teaches the package of claim 9, wherein the third integrated device (“upper 159-1”, Fig. 23i) is configured to be electrically coupled to the second integrated device (159-1, Fig. 23h-23i) through another electrical path (see Fig. 23i) that includes at least one other solder interconnect from the plurality of solder interconnects (interconnects 583+112 between “upper 159-1” and “lower 159-1”, see claim 8 above, Fig. 23i), at least one other interconnect from the plurality of interconnects (metal interconnects 27, Fig. 23h-23i), at least one other interconnect from the plurality of through mold interconnects (via interconnects 582, Figs. 23h-23i), and at least one other metallization interconnect from the second plurality of metallization interconnects (metal layers 6 within “2nd metallization”).
Re Claim 11, Lin teaches the package of claim 8, wherein the plurality of through mold interconnects includes a plurality of through mold vias and/or a plurality of through mold solder interconnects (via interconnects 582, Fig. 23h, para [0424]).
Re Claim 12, Lin teaches a device comprising (Fig. 23h):
a first package comprising:
a first integrated device (159-2, Fig. 23h, paras [0246] and [0424], also see Fig. 15B for details); and
a first metallization portion (marked “1st metallization” in annotated Fig. 23h above, which includes element 200 as shown in Fig. 17G, para [0367]) coupled to the first integrated device (159-2), wherein the first metallization portion comprises (note that element 200 within “1st metallization” includes redistribution layer 561 which is similar to interconnection layer 20 in Fig. 14A, para [0367]):
at least one first dielectric layer (12, Fig. 14A, para [0367]); and
a first plurality of metallization interconnects (metal pads 6a + vias 157 + interconnection metal layers 6 within RDL 561, see “1st metallization” in annotated Fig. 23h above, para [0409], also see Fig. 17G and para [0367] for details within element 200);
a second integrated device (159-1, Fig. 23h, para [0424]);
a second metallization portion (marked “2nd metallization” in annotated Fig. 23h above) coupled to the second integrated device (159-1) and the first metallization portion of the first package (“1st metallization”), wherein the second metallization portion (“2nd metallization”) comprises:
at least one second dielectric layer (12 within layer 20 of “2nd metallization”, compare Fig. 23h and Fig. 14A, para [0326]); and
a second plurality of metallization interconnects (metal pads 6a + interconnection metal layers 6, within “2nd metallization”, Fig. 23h, paras [0409] and [0326]); and
wherein some metallization interconnects from the second plurality of metallization interconnects (metal pads 6a within “2nd metallization”) directly touch (see Fig. 23h) some metallization interconnects from the first plurality of metallization interconnects (metal pads 6a within “1st metallization”), and
wherein interconnects (marked “interconnects from 2nd device” in annotated Fig. 23h above) from the second integrated device (159-1) directly touch (see Fig. 23h) the second plurality of metallization interconnects of the second metallization portion (metal pads 6a within “2nd metallization”); and
an encapsulation layer (“second 565”, Fig. 23h, para [0424], see annotated Fig. 23h above) coupled to the first package (see annotated Fig. 23h above), the second integrated device (159-1) and the second metallization portion (“2nd metallization”, see annotated Fig. 23h above).
Re Claim 13, Lin teaches the device of claim 12,
wherein the first metallization portion (“1st metallization”) includes a first redistribution portion (RDL 561 within element 200 of “1st metallization”, see claim 1 above),
wherein the first plurality of metallization interconnects (metal pads 6a + vias 157 + interconnection metal layers 6 within RDL 561, see claim 1 above) includes a first plurality of redistribution interconnects (interconnection metal layers 6 within RDL 561, compare Fig. 23h, Fig. 17G and 14A),
wherein the second metallization portion (“2nd metallization”) includes a second redistribution portion (RDL 20 of “2nd metallization”, compare Figs. 23h and 14A, para [0367]), and
wherein the second plurality of metallization interconnects (metal pads 6a + interconnection metal layers 6, within “2nd metallization”, see Fig. 23h) includes a second plurality of redistribution interconnects (interconnection metal layers 6 within “2nd metallization”, compare Figs. 23h and 14A).
Re Claim 14, Lin teaches the device of claim 12,
wherein the first integrated (159-2) is coupled to the first metallization portion (“1st metallization”) through a plurality of solder interconnects (563, Fig. 17G, para [0385], where the bonded contacts may be solder bumps, paras [0047] – [0048]),
wherein the first package comprises a first encapsulation layer (“first 565” annotated in Fig. 23h above, also see Fig. 17G and para [0380]), and
wherein the encapsulation layer (“second 565”, see claim 12 above) is a second encapsulation layer that is coupled to the first encapsulation layer (“first 565”).
Re Claim 15, Lin teaches the device of claim 12, further comprising a plurality of through mold vias (582, Fig. 23h, para [0424]) that are coupled to the second metallization portion (“2nd metallization”), wherein the plurality of through mold vias are located in the encapsulation layer (“second 565”).
Re Claim 21, Lin teaches the device of claim 12, wherein the device is selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle (self-drive car, see para [0008]).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 7 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2020/0144224 A1, of record), and further in view of We et al. (US 2021/0175178 A1, of record).
Re Claim 7, Lin teaches the package of claim 1, further comprising a plurality of through mold interconnects (582, Fig. 23h, para [0424]) that are coupled to the second metallization portion (“2nd metallization”), wherein the plurality of through mold interconnects are located in the encapsulation layer (“second 565”).
Lin does not teach that the through mold interconnects are through mold solder interconnects.
Related art We teaches that the through mold interconnects can be a through mold pillar (480, Fig. 4, para [0033]), similar to Lin or it can be through mold solder interconnects (280, Fig. 2, para [0019]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the through mold via interconnect of Lin to a through mold solder interconnect, according to the teachings of We. We teaches that the through mold interconnect can be a via interconnect, similar to the one shown by Lin, or it can be through mold solder interconnect. One of ordinary skill would realize that these are art-recognized alternate through mold interconnection structures for sending electrical signals, and one of ordinary skill in the art would have found it obvious to substitute the through mold solder interconnect instead of via interconnect. The use of a known interconnection structure for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Re Claim 16, Lin teaches the device of claim 12, further comprising a plurality of through mold interconnects (582, Fig. 23h, para [0424]) that are coupled to the second metallization portion (“2nd metallization”), wherein the plurality of through mold interconnects are located in the encapsulation layer (“second 565”).
Lin does not teach that the through mold interconnects are through mold solder interconnects.
Related art We teaches that the through mold interconnects can be a through mold pillar (480, Fig. 4, para [0033]), similar to Lin or it can be through mold solder interconnects (280, Fig. 2, para [0019]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the through mold via interconnect of Lin to a through mold solder interconnect, according to the teachings of We. We teaches that the through mold interconnect can be a via interconnect, similar to the one shown by Lin, or it can be through mold solder interconnect. One of ordinary skill would realize that these are art-recognized alternate through mold interconnection structures for sending electrical signals, and one of ordinary skill in the art would have found it obvious to substitute the through mold solder interconnect instead of via interconnect. The use of a known interconnection structure for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Re Claim 17, Lin modified by We teaches the device of claim 16,
wherein the plurality of through mold solder interconnects (280, Fig. 2, We) include a first plurality of through mold solder interconnects (marked “280-a” in annotated Fig. 2 of We below) and a second plurality of through mold solder interconnects (marked “280-b” in annotated Fig. 2 of We below), and
wherein the first plurality of through mold solder interconnects are coupled to the second plurality of through mold solder interconnects (Fig. 2, We).
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Re Claim 18, Lin modified by We teaches the device of claim 17,
wherein the first plurality of through mold solder interconnects include a first width (marked “width-1” in annotated Fig. 2 of We above), and
wherein the second plurality of through mold solder interconnects include a second width (marked “width-2” in annotated Fig. 2 of We above).
Re Claim 19, Lin modified by We teaches the device of claim 17, wherein the second plurality of through mold solder interconnects (“280-b”, We) are coupled to the second metallization portion (“2nd metallization”, Lin).
Re Claim 20, Lin modified by We teaches the device of claim 16, further comprising:
a plurality of interconnects (27, Fig. 23h, para [0424], Lin) coupled to a surface of the encapsulation layer (top surface of “second 565”, see annotated Fig. 23h above, Lin), wherein the plurality of interconnects (27, Lin) are coupled to the plurality of through mold solder interconnects (280, Fig. 2, We, modification of via interconnects 582, Fig. 23h, Lin, see claim 16 above); and
a solder resist layer (42, Fig. 23h, para [0424], Lin) formed over the surface of the encapsulation layer (top surface of “second 565”, Fig. 23h, Lin) and over at least some of the interconnects from the plurality of interconnects (27, Fig. 23h, Lin).
Response to Arguments
Applicant’s arguments with respect to claims 1, 12 and 22 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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