DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
The election/restriction requirement as stated in the office action dated 8/5/2025 is withdrawn in view of applicant’s argument filed on 10/3/2025.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1-6, 8-15 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2020/0144224 A1).
Re Claim 1, Lin teaches a package (Figs. 21h-21i) comprising:
a first integrated device (159-2, Fig. 21h, paras [0246] and [0423], also see Fig. 15B for details);
a first metallization portion (“first 561” within module 190, Figs. 21h-21i, see Fig. 17E where layer 561 within module 190 is marked, para [0367], also annotated Fig. 21h below) coupled to the first integrated device (159-2), wherein the first metallization portion comprises (“first 561” within module 190 is similar to interconnection layer 20 in Fig. 14A, para [0367]):
at least one first dielectric layer (12, Fig. 14A, para [0367]); and
a first plurality of metallization interconnects (6, Fig. 14A, para [0367]);
a second integrated device (159-1, Figs. 21h-21i, para [0394]);
a second metallization portion (“second 561”, 561 marked at the bottom of Figs. 21h-21i, para [0367], also annotated Fig. 21h below) coupled to the second integrated device (159-1) and the first metallization portion (“first 561”), wherein the second metallization portion (“second 561”, is similar to interconnection layer 20 in Fig. 14A, para [0367]) comprises:
at least one second dielectric layer (12, Fig. 14A, para [0367]); and
a second plurality of metallization interconnects (6, Fig. 14A, para [0367]); and
an encapsulation layer (“second 565”, Fig. 21h-21i, para [0423], see annotated Fig. 21h below) coupled to the first metallization portion (“first 561”), the second integrated device (159-1) and the second metallization portion (“second 561”).
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Re Claim 2, Lin teaches the package of claim 1,
wherein the first metallization portion (“first 561”) includes a first redistribution portion (layer 561 is similar to interconnection layer 20 in Fig. 14A, para [0367]),
wherein the first plurality of metallization interconnects (layer 6 of “first 561”) includes a first plurality of redistribution interconnects (see Fig. 14A),
wherein the second metallization portion (“second 561”) includes a second redistribution portion (layer 561 is similar to interconnection layer 20 in Fig. 14A, para [0367]), and
wherein the second plurality of metallization interconnects (layer 6 of “second 561”) includes a second plurality of redistribution interconnects (see Fig. 14A).
Re Claim 3, Lin teaches the package of claim 2,
wherein a first portion of a first redistribution interconnect from the first plurality of redistribution interconnects, includes a side profile that has a U-shape or a V shape (see inset of Fig. 14A), and
wherein a second portion of a second redistribution interconnect from the second plurality of redistribution interconnects, includes a side profile that has a U-shape or a V shape (see inset of Fig. 14A).
Re Claim 4, Lin teaches the package of claim 3, wherein a bottom portion of the first redistribution portion (bottom portion of “first 561”) is directly coupled to a bottom portion of the second redistribution portion (bottom portion of “second 561”, see Fig. 21h).
Re Claim 5, Lin teaches the package of claim 1, further comprising a first encapsulation layer (“first 565” within module 190, Fig. 21h, see Fig. 17E where layer 565 within module 190 is marked, para [0384], also annotated in Fig. 21h above) that is coupled to the first integrated device (159-2, Fig. 21h, also see Fig. 17E),
wherein the encapsulation layer (“second 565”, see claim 1 above) is a second encapsulation layer that is coupled to the first encapsulation layer (“first 565”), and
wherein the first integrated device (159-2) is coupled to the first metallization portion (“first 561”) through a plurality of solder interconnects (563, Fig. 17E, para [0368], where the bonded contacts may be solder bumps, paras [0047] – [0048]).
Re Claim 6, Lin teaches the package of claim 1, further comprising a plurality of through mold vias (582, Fig. 21h, para [0423]) that are coupled to the second metallization portion (“second 561”), wherein the plurality of through mold vias are located in the encapsulation layer (“second 565”).
Re Claim 8, Lin teaches the package of claim 1, further comprising:
a plurality of through mold interconnects (582, Fig. 21h, para [0423]) that extend through a thickness of the encapsulation layer (“second 565”), wherein the plurality of through mold interconnects are coupled to the second metallization portion (“second 561”);
a plurality of interconnects (27, Fig. 21h-21i, para [0420]) coupled to a surface of the encapsulation layer (top surface of “second 565”); and
a third integrated device (“upper 159-1”, Fig. 21i) coupled to the plurality of interconnects (27) through a plurality of solder interconnects (interconnects 563 just below “upper 159-1”, Fig. 2i, para [0368], where the bonded contacts may be solder bumps, paras [0047] – [0048]).
Re Claim 9, Lin teaches the package of claim 8, wherein the third integrated device (“upper 159-1”, Fig. 21i) is configured to be electrically coupled to the first integrated device (159-2, Figs. 21h-21i) through an electrical path (see Fig. 21i) that includes at least one solder interconnect from the plurality of solder interconnects (interconnects 563 just below “upper 159-1”, Fig. 21i), at least one interconnect from the plurality of interconnects (metal interconnects 27, Fig. 21h-21i), at least one interconnect from the plurality of through mold interconnects (via interconnects 582, Figs. 21h-21i), at least one metallization interconnect from the second plurality of metallization interconnects (metal interconnects 6 of “second 561”) and at least one metallization interconnect from the first plurality of metallization interconnects (metal interconnects 6 of “first 561”).
Re Claim 10, Lin teaches the package of claim 9, wherein the third integrated device (“upper 159-1”, Fig. 21i) is configured to be electrically coupled to the second integrated device (159-1, Fig. 21h) through another electrical path (see Fig. 21i) that includes at least one other solder interconnect from the plurality of solder interconnects (interconnects 563 just below “upper 159-1”, Fig. 21i), at least one other interconnect from the plurality of interconnects (metal interconnects 27, Fig. 21h-21i), at least one other interconnect from the plurality of through mold interconnects (via interconnects 582, Figs. 21h-21i), and at least one other metallization interconnect from the second plurality of metallization interconnects (metal interconnects 6 of “second 561”).
Re Claim 11, Lin teaches the package of claim 8, wherein the plurality of through mold interconnects includes a plurality of through mold vias and/or a plurality of through mold solder interconnects (via interconnects 582, Fig. 21h, para [0423]).
Re Claim 12, Lin teaches a device comprising (Figs. 21h):
a first package comprising:
a first integrated device (159-2, Fig. 21h, paras [0246] and [0423], also see Fig. 15B for details); and
a first metallization portion (“first 561” within module 190, Figs. 21h, see Fig. 17E where layer 561 within module 190 is marked, para [0367], also annotated Fig. 21h above) coupled to the first integrated device (159-2), wherein the first metallization portion comprises (“first 561” within module 190 is similar to interconnection layer 20 in Fig. 14A, para [0367]):
at least one first dielectric layer (12, Fig. 14A, para [0367]); and
a first plurality of metallization interconnects (6, Fig. 14A, para [0367]);
a second integrated device (159-1, Figs. 21h, para [0394]);
a second metallization portion (“second 561”, 561 marked at the bottom of Figs. 21h, para [0367], also annotated Fig. 21h above) coupled to the second integrated device (159-1) and the first metallization portion of the first package (“first 561”), wherein the second metallization portion (“second 561”, is similar to interconnection layer 20 in Fig. 14A, para [0367]) comprises:
at least one second dielectric layer (12, Fig. 14A, para [0367]); and
a second plurality of metallization interconnects (6, Fig. 14A, para [0367]); and
an encapsulation layer (“second 565”, Fig. 21h, para [0423], see annotated Fig. 21h above) coupled to the first package, the second integrated device and the second metallization portion (Fig. 21h).
Re Claim 13, Lin teaches the device of claim 12,
wherein the first metallization portion (“first 561”) includes a first redistribution portion (layer 561 is similar to interconnection layer 20 in Fig. 14A, para [0367]),
wherein the first plurality of metallization interconnects (layer 6 of “first 561”) includes a first plurality of redistribution interconnects (see Fig. 14A),
wherein the second metallization portion (“second 561”) includes a second redistribution portion (layer 561 is similar to interconnection layer 20 in Fig. 14A, para [0367]), and
wherein the second plurality of metallization interconnects (layer 6 of “second 561”) includes a second plurality of redistribution interconnects (see Fig. 14A).
Re Claim 14, Lin teaches the device of claim 12,
wherein the first integrated (159-2) is coupled to the first metallization portion (“first 561”) through a plurality of solder interconnects (563, Fig. 17E, para [0368], where the bonded contacts may be solder bumps, paras [0047] – [0048]),
wherein the first package comprises a first encapsulation layer (“first 565” within module 190, Fig. 21h, see Fig. 17E where layer 565 within module 190 is marked, para [0384], also annotated Fig. 21h above), and
wherein the encapsulation layer (“second 565”, see claim 12 above) is a second encapsulation layer that is coupled to the first encapsulation layer (“first 565”).
Re Claim 15, Lin teaches the device of claim 12, further comprising a plurality of through mold vias (582, Fig. 21h, para [0423]) that are coupled to the second metallization portion (“second 561”), wherein the plurality of through mold vias are located in the encapsulation layer (“second 565”).
Re Claim 21, Lin teaches the device of claim 12, wherein the device is selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle (self-drive car, see para [0008]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2020/0144224 A1), and further in view of We et al. (US 2021/0175178 A1).
Re Claim 7, Lin teaches the package of claim 1, further comprising a plurality of through mold interconnects (582, Fig. 21h, para [0423]) that are coupled to the second metallization portion (“second 561”), wherein the plurality of through mold interconnects are located in the encapsulation layer (“second 565”).
Lin does not teach that the through mold interconnects are through mold solder interconnects.
Related art We teaches that the through mold interconnects can be a through mold pillar (480, Fig. 4, para [0033]), similar to Lin or it can be through mold solder interconnects (280, Fig. 2, para [0019]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the through mold via interconnect of Lin to a through mold solder interconnect, according to the teachings of We. We teaches that the through mold interconnect can be a via interconnect, similar to the one shown by Lin, or it can be through mold solder interconnect. One of ordinary skill would realize that these are art-recognized alternate through mold interconnection structures for sending electrical signals, and one of ordinary skill in the art would have found it obvious to substitute the through mold solder interconnect instead of via interconnect. The use of a known interconnection structure for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Re Claim 16, Lin teaches the device of claim 12, further comprising a plurality of through mold interconnects (582, Fig. 21h, para [0423]) that are coupled to the second metallization portion (“second 561”), wherein the plurality of through mold interconnects are located in the encapsulation layer (“second 565”).
Lin does not teach that the through mold interconnects are through mold solder interconnects.
Related art We teaches that the through mold interconnects can be a through mold pillar (480, Fig. 4, para [0033]), similar to Lin or it can be through mold solder interconnects (280, Fig. 2, para [0019]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the through mold via interconnect of Lin to a through mold solder interconnect, according to the teachings of We. We teaches that the through mold interconnect can be a via interconnect, similar to the one shown by Lin, or it can be through mold solder interconnect. One of ordinary skill would realize that these are art-recognized alternate through mold interconnection structures for sending electrical signals, and one of ordinary skill in the art would have found it obvious to substitute the through mold solder interconnect instead of via interconnect. The use of a known interconnection structure for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Re Claim 17, Lin modified by We teaches the device of claim 16,
wherein the plurality of through mold solder interconnects (280, Fig. 2, We) include a first plurality of through mold solder interconnects (marked “280-a” in annotated Fig. 2 of We below) and a second plurality of through mold solder interconnects (marked “280-b” in annotated Fig. 2 of We below), and
wherein the first plurality of through mold solder interconnects are coupled to the second plurality of through mold solder interconnects (Fig. 2, We).
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Re Claim 18, Lin modified by We teaches the device of claim 17,
wherein the first plurality of through mold solder interconnects include a first width (marked “width-1” in annotated Fig. 2 of We above), and
wherein the second plurality of through mold solder interconnects include a second width (marked “width-2” in annotated Fig. 2 of We above).
Re Claim 19, Lin modified by We teaches the device of claim 17, wherein the second plurality of through mold solder interconnects (“280-b”, We) are coupled to the second metallization portion (“second 561”, Lin).
Re Claim 20, Lin modified by We teaches the device of claim 16, further comprising:
a plurality of interconnects (27, Fig. 21h, para [0420], Lin) coupled to a surface of the encapsulation layer (top surface of “second 565”, Fig. 21h, Lin), wherein the plurality of interconnects (27, Lin) are coupled to the plurality of through mold solder interconnects (280, Fig. 2, We, modification of via interconnects 582, Fig. 21h, Lin, see claim 16 above); and
a solder resist layer (42, Fig. 21h, para [0420], Lin) formed over the surface of the encapsulation layer (top surface of “second 565”, Fig. 21h, Lin) and over at least some of the interconnects from the plurality of interconnects (27, Fig. 21h, Lin).
Claims 22-24 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2020/0144224 A1), and further in view of Lee et al. (US 2022/0262777 A1).
Re Claim 22, Lin teaches a method for fabricating a package (Fig. 21h), comprising:
providing a first package comprising:
a first integrated device (159-2, Fig. 21h, paras [0246] and [0423], also see Fig. 15B for details); and
a first metallization portion (“first 561” within module 190, Fig. 21h, see Fig. 17E where layer 561 within module 190 is marked, para [0367], also annotated Fig. 21h above) coupled to the first integrated device (159-2), wherein the first metallization portion comprises (“first 561” within module 190 is similar to interconnection layer 20 in Fig. 14A, para [0367]):
at least one first dielectric layer (12, Fig. 14A, para [0367]); and
a first plurality of metallization interconnects (6, Fig. 14A, para [0367]);
providing a second integrated device (159-1, Figs. 21h, para [0394]);
forming an encapsulation layer (“second 565”, Fig. 21h, para [0423], see annotated Fig. 21h above); and
forming a second metallization portion (27+42, Fig. 21h, para [0420]) over the second integrated device (159-1), the first metallization portion (“first 561”) of the first package and the encapsulation layer (“second 565”), wherein the second metallization portion comprises:
at least one second dielectric layer (42); and
a second plurality of metallization interconnects (27).
Lin discloses an encapsulation layer 565 in Fig. 21h, which encapsulates all the side surfaces but not the top surface, and hence it does not disclose forming over the first package and the second integrated device.
Related art, Lee teaches an encapsulation layer (410, Fig. 1, para [0043]) which not only encapsulates the sides but also formed over the devices (200/300, Fig. 1).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the encapsulation layer of Lin according to the teachings of Lee, such that the encapsulation layer is also formed over the integrated devices. This will help to fully enclose the device within the protective encapsulation layer, preventing from any damages to the top surfaces of the devices during subsequent fabrication process.
Re Claim 23, Lin modified by Lee teaches the method of claim 22,
wherein the first integrated (159-2, Fig. 21h, Lin) is coupled to the first metallization portion (“first 561”, Lin) through a plurality of solder interconnects (563, Fig. 17E, para [0368], where the bonded contacts may be solder bumps, paras [0047] – [0048], Lin),
wherein the first package comprises a first encapsulation layer (“first 565” within module 190, Fig. 21h, see Fig. 17E where layer 565 within module 190 is marked, para [0384], also annotated Fig. 21h above, Lin), and
wherein the encapsulation layer (“second 565”, Lin, see claim 12 above) is a second encapsulation layer that is coupled to the first encapsulation layer (“first 565”, Lin).
Re Claim 24, Lin modified by Lee teaches the method of claim 22, further comprising forming a plurality of through mold vias (582, Fig. 21h, para [0423], Lin) in the encapsulation layer (“second 565”, Lin), wherein the second metallization portion (27+42, Fig. 21h Lin) is coupled to the plurality of mold vias (582, Lin).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2020/0144224 A1) and Lee et al. (US 2022/0262777 A1), and further in view of We et al. (US 2021/0175178 A1).
Re Claim 25, Lin modified by Lee teaches the method of claim 22, further comprising forming a plurality of through mold interconnects (582, Fig. 21h, para [0423], Lin), wherein the second metallization portion (27+42, Fig. 21h Lin) is coupled to the plurality of through mold interconnects (582, Lin), wherein the encapsulation layer (“second 565”, Lin) is formed such that the encapsulation layer encapsulates the plurality of through mold interconnects (see Fig. 21h, Lin).
Lin does not teach that the through mold interconnects are through mold solder interconnects.
Related art We teaches that the through mold interconnects can be a through mold pillar (480, Fig. 4, para [0033]), similar to Lin or it can be through mold solder interconnects (280, Fig. 2, para [0019]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the through mold via interconnect of Lin to a through mold solder interconnect, according to the teachings of We. We teaches that the through mold interconnect can be a via interconnect, similar to the one shown by Lin, or it can be through mold solder interconnect. One of ordinary skill would realize that these are art-recognized alternate through mold interconnection structures for sending electrical signals, and one of ordinary skill in the art would have found it obvious to substitute the through mold solder interconnect instead of via interconnect. The use of a known interconnection structure for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Conclusion
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898