DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
This OA is in response to the amendment filled on 7/7/2026 that has been entered, wherein claims 25-32,34-41,43-50,52-58 and 60-64 are pending, claims 1-24, 33, 42, 51 and 59 are canceled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 25-28, 31-32, 34-41, 43-50, 52-58 and 60-64 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Orlowski (US 2007/0254435 A1) in view of Bohr et al. (US 2011/0156107 A1) both of record.
Regarding claim 25, Orlowski teaches a semiconductor device(Figs. 7-10) including a field effect transistor(¶0036) comprising:
a semiconductor substrate(12, ¶0027) including a channel forming region(16, ¶0025);
a gate insulating film(32, ¶0032) formed at the channel forming region(16, ¶0025) and formed at least partially on a first insulating film(14, ¶0032);
a gate electrode(36, ¶0034) formed over the gate insulating film(32, ¶0032), wherein the gate insulating film(32, ¶0032) extends in a first direction(vertical direction of Fig. 7) along one or more sidewall surfaces of the gate electrode(36, ¶0034) and extends in a second direction(direction of line 7, Fig. 8) which intersects with a source-drain direction(direction of line 10, Fig. 8) that is different than the first direction(vertical direction of Fig. 7), between and along another surface of the gate electrode(36, ¶0034) and a surface of the first insulating film(14, ¶0032);
a source/drain region(44, 46, ¶0025) formed on the semiconductor substrate(12, ¶0027); and
a second insulating layer(20, ¶0027) formed over the source/drain region(44, 46, ¶0025) in a region other than at least a region of the first silicon nitride insulating layer,
wherein the field effect transistor(¶0036) is a fin-type field effect transistor(¶0036),
wherein the gate insulating film(32, ¶0032) makes contact with a lower portion of a first sidewall insulating film(right 28, Fig. 7, ¶0025) and a lower portion of a second sidewall insulating film(left 28, Fig. 7, ¶0025) in the second direction(direction of line 7, Fig. 8), and
wherein a distance from an inner sidewall of the first sidewall insulating film(right 28, Fig. 7, ¶0025) to the channel forming region(16, ¶0025) is different(Fig. 7) from a distance from an inner sidewall of the second sidewall insulating film(left 28, Fig. 7, ¶0025) to the channel forming region(16, ¶0025) in the second direction(direction of line 7, Fig. 8).
Orlowski does not teach a first silicon nitride insulating layer formed over the gate electrode(36, ¶0034); a second silicon nitride insulating layer formed over the source/drain region(44, 46, ¶0025) in a region other than at least a region of the first silicon nitride insulating layer.
Bohr teaches a semiconductor device(Fig. 4) comprising a first silicon nitride insulating layer(300, ¶0031) formed over the gate electrode(102, ¶0029); a second silicon nitride insulating layer(110a, ¶0035) formed over the source/drain region(106, ¶0033) in a region other than at least a region of the first silicon nitride insulating layer(300, ¶0031). It would have been obvious to one of ordinary skill in the art at the time of invention to modify the device of Orlowski, to include a first silicon nitride insulating layer formed over the gate electrode; a second silicon nitride insulating layer formed over the source/drain region in a region other than at least a region of the first silicon nitride insulating layer, as taught by Bohr, in order to electrically isolate the gate electrode and prevent a short between the gate electrode and contacts(¶0051).
Regarding claim 26, Orlowski teaches the semiconductor device according to claim 25, but is not relied on to teach the first silicon nitride insulating layer is interposed between the second silicon nitride insulating layer.
Bohr teaches a semiconductor device(Fig. 4) wherein the first silicon nitride insulating layer(300, ¶0031) is interposed between the second silicon nitride insulating layer(110a, ¶0035). It would have been obvious to one of ordinary skill in the art at the time of invention to modify the device of Orlowski, so that the first silicon nitride insulating layer is interposed between the second silicon nitride insulating layer, as taught by Bohr, in order to electrically isolate the gate electrode and prevent a short between the gate electrode and contacts(¶0051).
Regarding claim 27, Orlowski teaches the semiconductor device according to claim 25, wherein the source/drain region(44, 46, ¶0025) is formed from a mixed crystal layer including silicon(silicon, ¶0025, ¶0027) and atoms different in lattice constant from silicon(germanium, ¶0025, ¶0027).
Regarding claim 28, Orlowski teaches the semiconductor device according to claim 27, wherein the mixed crystal layer(silicon germanium, ¶0025, ¶0027) comprises silicon(silicon, ¶0025, ¶0027) and germanium(germanium, ¶0025, ¶0027).
Regarding claim 31, Orlowski teaches the semiconductor device according to claim 25, wherein a first region forms a concave shape(Fig. 7) for receiving the gate electrode(36, ¶0034).
Regarding claim 32, Orlowski teaches the semiconductor device according to claim 25, but is not relied on to teach the gate electrode(36, ¶0034) makes contact with the first sidewall insulating film(right 28, Fig. 7, ¶0025) and the second sidewall insulating film(left 28, Fig. 7, ¶0025) in the second direction(direction of line 7, Fig. 8).
Bohr teaches a semiconductor device(Fig. 2c) wherein the gate electrode(102, ¶0029) makes contact with the first sidewall insulating film(right 108, ¶0032) and the second sidewall insulating film(left 108, ¶0032) in the second direction. It would have been obvious to one of ordinary skill in the art at the time of invention to modify the device of Orlowski, so that the first silicon nitride insulating layer makes contact with the first sidewall insulating film and the second sidewall insulating film in the second direction, as taught by Bohr, in order to electrically isolate the gate electrode and prevent a short between the gate electrode and contacts(¶0051).
Regarding claim 34, Orlowski teaches the semiconductor device according to claim 25, wherein the gate insulating film(32, ¶0032) is formed to include a first side surface, a second side surface, and a bottom surface, the first and second side surfaces extending in the first direction(vertical direction of Fig. 7) and the bottom surface extending in the source-drain direction(direction of line 10, Fig. 8), the first and second side surfaces and the bottom surface forming a first region(50, Fig. 10), and
the gate electrode(36, ¶0034) is formed in the first region over the bottom surface.
Regarding claim 35, Orlowski teaches the semiconductor device according to claim 34, but is not relied on to teach the first silicon nitride insulating layer makes contact with the first sidewall insulating film(right 28, Fig. 7, ¶0025) and the second sidewall insulating film(left 28, Fig. 7, ¶0025) in the second direction(direction of line 7, Fig. 8).
Bohr teaches a semiconductor device(Fig. 4) wherein the first silicon nitride insulating layer(300, ¶0031) makes contact with the first sidewall insulating film(right 108, ¶0032) and the second sidewall insulating film(left 108, ¶0032) in the second direction. It would have been obvious to one of ordinary skill in the art at the time of invention to modify the device of Orlowski, so that the first silicon nitride insulating layer makes contact with the first sidewall insulating film and the second sidewall insulating film in the second direction, as taught by Bohr, in order to electrically isolate the gate electrode and prevent a short between the gate electrode and contacts(¶0051).
Regarding claim 36, Orlowski teaches the semiconductor device according to claim 34, wherein the first sidewall insulating film(right 28, Fig. 7, ¶0025) and the second sidewall insulating film(left 28, Fig. 7, ¶0025) surround the gate electrode(36, ¶0034).
Regarding claim 37, Orlowski teaches the semiconductor device according to claim 25, but is not relied on to teach the first silicon nitride insulating layer makes contact with the first sidewall insulating film(right 28, Fig. 7, ¶0025) and the second sidewall insulating film(left 28, Fig. 7, ¶0025) in the second direction(direction of line 7, Fig. 8).
Bohr teaches a semiconductor device(Fig. 4) wherein the first silicon nitride insulating layer(300, ¶0031) makes contact with the first sidewall insulating film(right 108, ¶0032) and the second sidewall insulating film(left 108, ¶0032) in the second direction. It would have been obvious to one of ordinary skill in the art at the time of invention to modify the device of Orlowski, so that the first silicon nitride insulating layer makes contact with the first sidewall insulating film and the second sidewall insulating film in the second direction, as taught by Bohr, in order to electrically isolate the gate electrode and prevent a short between the gate electrode and contacts(¶0051).
Regarding claim 38, Orlowski teaches a semiconductor device(Fig. 7-10) including a field effect transistor(¶0036) comprising:
a semiconductor substrate(12, ¶0027) including a fin shape channel forming region(16, ¶0025);
a gate insulating film(32, ¶0032) formed at the fin shape channel forming region(16, ¶0025) and formed at least partially on a first insulating film(14, ¶0032);
a gate electrode(36, ¶0034) formed over the gate insulating film(32, ¶0032), wherein a first portion of the gate insulating film(32, ¶0032) comprises a first region that extends along a first direction(vertical direction of Fig. 7) which intersects with a source-drain direction(direction of line 10, Fig. 8) of the fin shape channel forming region(16, ¶0025), and a second portion of the gate insulating film(32, ¶0032) comprises another region other than the first region, the another region extending in the first direction(vertical direction of Fig. 7);
a source/drain region(44, 46, ¶0025) formed on the semiconductor substrate(12, ¶0027); and
a second insulating layer(20, ¶0027) formed over the source/drain region(44, 46, ¶0025),
wherein the field effect transistor(¶0036) is a fin-type field effect transistor(¶0036),
wherein the gate insulating film(32, ¶0032) makes contact with a lower portion of a first sidewall insulating film(right 28, Fig. 7, ¶0025) and a lower portion of a second sidewall insulating film(left 28, Fig. 7, ¶0025) in the first direction(vertical direction of Fig. 7), and
wherein a distance from an inner sidewall of the first sidewall insulating film(right 28, Fig. 7, ¶0025) to the channel forming region(16, ¶0025) is different(Fig. 7) from a distance from an inner sidewall of the second sidewall insulating film(left 28, Fig. 7, ¶0025) to the channel forming region(16, ¶0025) in the first direction(vertical direction of Fig. 7).
Orlowski does not teach a first silicon nitride insulating layer formed over the gate electrode(36, ¶0034); a second silicon nitride insulating layer formed over the source/drain region(44, 46, ¶0025) in a region other than at least a region of the first silicon nitride insulating layer.
Bohr teaches a semiconductor device(Fig. 4) comprising a first silicon nitride insulating layer(300, ¶0031) formed over the gate electrode(102, ¶0029); a second silicon nitride insulating layer(110a, ¶0035) formed over the source/drain region(106, ¶0033) in a region other than at least a region of the first silicon nitride insulating layer(300, ¶0031). It would have been obvious to one of ordinary skill in the art at the time of invention to modify the device of Orlowski, to include a first silicon nitride insulating layer formed over the gate electrode; a second silicon nitride insulating layer formed over the source/drain region in a region other than at least a region of the first silicon nitride insulating layer, as taught by Bohr, in order to electrically isolate the gate electrode and prevent a short between the gate electrode and contacts(¶0051).
Regarding claim 39, Orlowski teaches the semiconductor device according to claim 38, wherein the first silicon nitride insulating layer is interposed between the second silicon nitride insulating layer.
Regarding claim 40, Orlowski teaches the semiconductor device according to claim 38, wherein a second region(50, Fig. 9) forms a concave shape for receiving the gate electrode(36, ¶0034).
Regarding claim 41, Orlowski teaches the semiconductor device according to claim 38, but is not relied on to teach the gate electrode(36, ¶0034) makes contact with the first sidewall insulating film(right 28, Fig. 7, ¶0025) and the second sidewall insulating film(left 28, Fig. 7, ¶0025) in the second direction(direction of line 7, Fig. 8).
Bohr teaches a semiconductor device(Fig. 2c) wherein the gate electrode(102, ¶0029) makes contact with the first sidewall insulating film(right 108, ¶0032) and the second sidewall insulating film(left 108, ¶0032) in the second direction. It would have been obvious to one of ordinary skill in the art at the time of invention to modify the device of Orlowski, so that the first silicon nitride insulating layer makes contact with the first sidewall insulating film and the second sidewall insulating film in the second direction, as taught by Bohr, in order to electrically isolate the gate electrode and prevent a short between the gate electrode and contacts(¶0051).
Regarding claim 43, Orlowski teaches the semiconductor device according to claim 38, wherein the gate insulating film(32, ¶0032) is formed to include a first side surface, a second side surface, and a bottom surface, the first and second side surfaces extending in a second direction(direction of line 7, Fig. 8) along one or more sidewall surfaces of the gate electrode(36, ¶0034) and the bottom surface extending in the source-drain direction(direction of line 10, Fig. 8), the first and second side surfaces and the bottom surface forming a first region(50, Fig. 9), and the gate electrode(36, ¶0034) is formed in the first region(50, Fig. 9) over the bottom surface.
Regarding claim 44, Orlowski teaches the semiconductor device according to claim 43, but is not relied on to teach the first silicon nitride insulating layer makes contact with the first sidewall insulating film(right 28, Fig. 7, ¶0025) and the second sidewall insulating film(left 28, Fig. 7, ¶0025) in the second direction(direction of line 7, Fig. 8).
Bohr teaches a semiconductor device(Fig. 4) wherein the first silicon nitride insulating layer(300, ¶0031) makes contact with the first sidewall insulating film(right 108, ¶0032) and the second sidewall insulating film(left 108, ¶0032) in the second direction. It would have been obvious to one of ordinary skill in the art at the time of invention to modify the device of Orlowski, so that the first silicon nitride insulating layer makes contact with the first sidewall insulating film and the second sidewall insulating film in the second direction, as taught by Bohr, in order to electrically isolate the gate electrode and prevent a short between the gate electrode and contacts(¶0051).
Regarding claim 45, Orlowski teaches the semiconductor device according to claim 43, wherein the first sidewall insulating film(right 28, Fig. 7, ¶0025) and the second sidewall insulating film(left 28, Fig. 7, ¶0025) surround the gate electrode(36, ¶0034).
Regarding claim 46, Orlowski teaches the semiconductor device according to claim 38, but is not relied on to teach the first silicon nitride insulating layer makes contact with the first sidewall insulating film(right 28, Fig. 7, ¶0025) and the second sidewall insulating film(left 28, Fig. 7, ¶0025) in the second direction(direction of line 7, Fig. 8).
Bohr teaches a semiconductor device(Fig. 4) wherein the first silicon nitride insulating layer(300, ¶0031) makes contact with the first sidewall insulating film(right 108, ¶0032) and the second sidewall insulating film(left 108, ¶0032) in the second direction. It would have been obvious to one of ordinary skill in the art at the time of invention to modify the device of Orlowski, so that the first silicon nitride insulating layer makes contact with the first sidewall insulating film and the second sidewall insulating film in the second direction, as taught by Bohr, in order to electrically isolate the gate electrode and prevent a short between the gate electrode and contacts(¶0051).
Regarding claim 47, Orlowski teaches a semiconductor device(Figs. 7-10) including a field effect transistor(¶0036) comprising:
a semiconductor substrate(12, ¶0027) including a fin shape channel forming region(16, ¶0025);
a gate insulating film(32, ¶0032) formed at the fin shape channel forming region(16, ¶0025) and formed at least partially on a first insulating film(14, ¶0032);
a gate electrode(36, ¶0034) formed over the gate insulating film(32, ¶0032),
wherein the gate insulating film(32, ¶0032) includes a first portion that extends along a first direction(vertical direction of Fig. 7) which intersects with a source-drain direction(direction of line 10, Fig. 8) and along a second direction(direction of line 7, Fig. 8) protruding from the semiconductor substrate(12, ¶0027), and a second portion that extends from the first portion in the first direction(vertical direction of Fig. 7) between the gate electrode(36, ¶0034) and the first insulating film(14, ¶0032);
a source/drain region(44, 46, ¶0025) formed on the semiconductor substrate(12, ¶0027); and
a second insulating layer(20, ¶0027) formed over the source/drain region(44, 46, ¶0025),
wherein the field effect transistor(¶0036) is a fin-type field effect transistor(¶0036),
the gate insulating film(32, ¶0032) makes contact with a lower portion of a first sidewall insulating film(right 28, Fig. 7, ¶0025) and a lower portion of a second sidewall insulating film(left 28, Fig. 7, ¶0025) in the first direction(vertical direction of Fig. 7), and
wherein a distance from an inner sidewall of the first sidewall insulating film(right 28, Fig. 7, ¶0025) to the channel forming region(16, ¶0025) is different(Fig. 7) from a distance from an inner sidewall of the second sidewall insulating film(left 28, Fig. 7, ¶0025) to the fin shape channel forming region(16, ¶0025) in the first direction(vertical direction of Fig. 7).
Orlowski does not teach a first silicon nitride insulating layer formed over the gate electrode(36, ¶0034); a second silicon nitride insulating layer formed over the source/drain region(44, 46, ¶0025) in a region other than at least a region of the first silicon nitride insulating layer.
Bohr teaches a semiconductor device(Fig. 4) comprising a first silicon nitride insulating layer(300, ¶0031) formed over the gate electrode(102, ¶0029); a second silicon nitride insulating layer(110a, ¶0035) formed over the source/drain region(106, ¶0033) in a region other than at least a region of the first silicon nitride insulating layer(300, ¶0031). It would have been obvious to one of ordinary skill in the art at the time of invention to modify the device of Orlowski, to include a first silicon nitride insulating layer formed over the gate electrode; a second silicon nitride insulating layer formed over the source/drain region in a region other than at least a region of the first silicon nitride insulating layer, as taught by Bohr, in order to electrically isolate the gate electrode and prevent a short between the gate electrode and contacts(¶0051).
Regarding claim 48, Orlowski teaches the semiconductor device according to claim 47, wherein the first silicon nitride insulating layer is interposed between the second silicon nitride insulating layer.
Regarding claim 49, Orlowski teaches the semiconductor device according to claim 47, wherein the gate insulating film(32, ¶0032) includes a first region(Fig. 7) forms a concave shape for receiving the gate electrode(36, ¶0034).
Regarding claim 50, Orlowski teaches the semiconductor device according to claim 47, wherein the gate electrode(36, ¶0034) makes contact with the first sidewall insulating film(right 28, Fig. 7, ¶0025) and the second sidewall insulating film(left 28, Fig. 7, ¶0025) in the first direction(vertical direction of Fig. 7).
Regarding claim 52, Orlowski teaches the semiconductor device according to claim 47, wherein the gate insulating film(32, ¶0032) is formed to include a first side surface, a second side surface, and a bottom surface, the first and second side surfaces extending in the second direction(direction of line 7, Fig. 8) and the bottom surface extending in the source-drain direction(direction of line 10, Fig. 8), the first and second side surfaces and the bottom surface forming a first region, and
the gate electrode(36, ¶0034) is formed in the first region over the bottom surface.
Regarding claim 53, Orlowski teaches the semiconductor device according to claim 52, wherein the first silicon nitride insulating layer makes contact with the first sidewall insulating film(right 28, Fig. 7, ¶0025) and the second sidewall insulating film(left 28, Fig. 7, ¶0025) in the first direction(vertical direction of Fig. 7).
Regarding claim 54, Orlowski teaches the semiconductor device according to claim 52, wherein the first sidewall insulating film(right 28, Fig. 7, ¶0025) and the second sidewall insulating film(left 28, Fig. 7, ¶0025) surround the gate electrode(36, ¶0034).
Regarding claim 55, Orlowski teaches the semiconductor device according to claim 47, wherein the first silicon nitride insulating layer makes contact with the first sidewall insulating film(right 28, Fig. 7, ¶0025) and the second sidewall insulating film(left 28, Fig. 7, ¶0025) in the first direction(vertical direction of Fig. 7).
Regarding claim 56, Orlowski teaches a semiconductor device(Figs. 7-10) including a field effect transistor(¶0036) comprising:
a semiconductor substrate(12, ¶0027) including a channel forming region(16, ¶0025);
a gate insulating film(32, ¶0032) formed to include a first side surface, a second side surface and a bottom surface, the first and second side surfaces extending in a first direction(vertical direction of Fig. 7), and the bottom surface extending in a source-drain direction(direction of line 10, Fig. 8), the first and second side surfaces and the bottom surface forming a first region;
a gate electrode(36, ¶0034) formed in the first region(50, Fig. 7) over the bottom surface;
a source/drain region(44, 46, ¶0025) formed on the semiconductor substrate(12, ¶0027); and
a second insulating layer(20, ¶0027) formed in a second region(region of 20) other than the first region(50, Fig. 7),
wherein the field effect transistor(¶0036) is a fin-type field effect transistor(¶0036),
wherein the gate insulating film(32, ¶0032) makes contact with a lower portion of a first sidewall insulating film(right 28, Fig. 7, ¶0025) and a lower portion of a second sidewall insulating film(left 28, Fig. 7, ¶0025) in a second direction(direction of line 7, Fig. 8) which intersects with the source-drain direction(direction of line 10, Fig. 8), and
wherein a distance from an inner sidewall of the first sidewall insulating film(right 28, Fig. 7, ¶0025) to the channel forming region(16, ¶0025) is different(Fig. 7) from a distance from an inner sidewall of the second sidewall insulating film(left 28, Fig. 7, ¶0025) to the channel forming region(16, ¶0025) in the second direction(direction of line 7, Fig. 8).
Orlowski does not teach a first silicon nitride insulating layer formed over the gate electrode(36, ¶0034); a second silicon nitride insulating layer formed over the source/drain region(44, 46, ¶0025) in a region other than at least a region of the first silicon nitride insulating layer.
Bohr teaches a semiconductor device(Fig. 4) comprising a first silicon nitride insulating layer(300, ¶0031) formed over the gate electrode(102, ¶0029); a second silicon nitride insulating layer(110a, ¶0035) formed over the source/drain region(106, ¶0033) in a region other than at least a region of the first silicon nitride insulating layer(300, ¶0031). It would have been obvious to one of ordinary skill in the art at the time of invention to modify the device of Orlowski, to include a first silicon nitride insulating layer formed over the gate electrode; a second silicon nitride insulating layer formed over the source/drain region in a region other than at least a region of the first silicon nitride insulating layer, as taught by Bohr, in order to electrically isolate the gate electrode and prevent a short between the gate electrode and contacts(¶0051).
Regarding claim 57, Orlowski teaches the semiconductor device according to claim 56, but is not relied on to teach the first silicon nitride insulating layer is interposed between the second silicon nitride insulating layer.
Bohr teaches a semiconductor device(Fig. 4) wherein the first silicon nitride insulating layer(300, ¶0031) is interposed between the second silicon nitride insulating layer(110a, ¶0035). It would have been obvious to one of ordinary skill in the art at the time of invention to modify the device of Orlowski, so that the first silicon nitride insulating layer is interposed between the second silicon nitride insulating layer, as taught by Bohr, in order to electrically isolate the gate electrode and prevent a short between the gate electrode and contacts(¶0051).
Regarding claim 58, Orlowski teaches the semiconductor device according to claim 56, wherein the first region(50, Fig. 7) forms a concave shape for receiving the gate electrode(36, ¶0034).
Regarding claim 60, Orlowski teaches the semiconductor device according to claim 56, but is not relied on to teach the first silicon nitride insulating layer makes contact with the first sidewall insulating film(right 28, Fig. 7, ¶0025) and the second sidewall insulating film(left 28, Fig. 7, ¶0025) in the second direction(direction of line 7, Fig. 8).
Bohr teaches a semiconductor device(Fig. 4) wherein the first silicon nitride insulating layer(300, ¶0031) makes contact with the first sidewall insulating film(right 108, ¶0032) and the second sidewall insulating film(left 108, ¶0032) in the second direction. It would have been obvious to one of ordinary skill in the art at the time of invention to modify the device of Orlowski, so that the first silicon nitride insulating layer makes contact with the first sidewall insulating film and the second sidewall insulating film in the second direction, as taught by Bohr, in order to electrically isolate the gate electrode and prevent a short between the gate electrode and contacts(¶0051).
Regarding claim 61, Orlowski teaches the semiconductor device according to claim 25, wherein the gate insulating film(32, ¶0032) continuously extends from the channel forming region(16, ¶0025) to the first and second sidewall insulating films(28, Fig. 7, ¶0025) and directly contacts the first and second sidewall insulating films(28, Fig. 7, ¶0025).
Regarding claim 62, Orlowski teaches the semiconductor device according to claim 38, wherein the gate insulating film(32, ¶0032) continuously extends from the channel forming region(16, ¶0025) to the first and second sidewall insulating films(28, Fig. 7, ¶0025) and directly contacts the first and second sidewall insulating films(28, Fig. 7, ¶0025).
Regarding claim 63, Orlowski teaches the semiconductor device according to claim 47, wherein the gate insulating film(32, ¶0032) continuously extends from the channel forming region(16, ¶0025) to the first and second sidewall insulating films(28, Fig. 7, ¶0025) and directly contacts the first and second sidewall insulating films(28, Fig. 7, ¶0025).
Regarding claim 64, Orlowski teaches the semiconductor device according to claim 56, wherein the gate insulating film(32, ¶0032) continuously extends from the channel forming region(16, ¶0025) to the first and second sidewall insulating films(28, Fig. 7, ¶0025) and directly contacts the first and second sidewall insulating films(28, Fig. 7, ¶0025).
Claims 29-30 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Orlowski (US 2007/0254435 A1) and Bohr et al. (US 2011/0156107 A1) as applied to claim 28, further in view of Zhu et al. (US 2006/0160317 A1) as cited in the IDS of 8/3/2022, all of record.
Regarding claim 29, Orlowski, in view of Bohr, teaches the semiconductor device according to claim 28, but is not relied on to teach the first silicon nitride insulating layer is a first stress application layer, and the second silicon nitride insulating layer is a second stress application layer.
Zhu teaches a semiconductor device(Fig. 8) including a field effect transistor wherein the first silicon nitride insulating layer(28, ¶0019, ¶0027) is a first stress application layer(¶0027), and the second silicon nitride insulating layer(22, ¶0019, ¶0027) is a second stress application layer(¶0027). It would have been obvious to one of ordinary skill in the art at the time of invention to modify the device of Orlowski, so that the first silicon nitride insulating layer is a first stress application layer, and the second silicon nitride insulating layer is a second stress application layer, as taught by Zhu, in order to enhance the stress in the channel forming region(¶0027).
Regarding claim 30, Orlowski, in view of Bohr, teaches the semiconductor device according to claim 29, but is not relied on to teach the first stress application layer applies a first stress to the channel forming region(16, ¶0025) and the second stress application layer applies a second stress to the channel forming region(16, ¶0025), and a direction of the first stress is different from a direction of the second stress.
Zhu teaches a semiconductor device(Fig. 8) including a field effect transistor wherein the first stress application layer(28, ¶0027) applies a first stress to the channel forming region(not labeled, ¶0027), and the second stress application layer(22, ¶0027) applies a second stress to the channel forming region(not labeled, ¶0027), and a direction of the first stress is different from a direction of the second stress(¶0027). It would have been obvious to one of ordinary skill in the art at the time of invention to modify the device of Orlowski, so that the first stress application layer applies a first stress to the channel forming region and the second stress application layer applies a second stress to the channel forming region, and a direction of the first stress is different from a direction of the second stress, as taught by Zhu, in order to enhance the stress in the channel forming region(¶0027).
Response to Arguments
Applicant's arguments filed 7/7/2026 have been fully considered but they are not persuasive.
Regarding claim 1, Applicant’s argue Orlowski does not disclose that "a distance from an inner sidewall of the first sidewall insulating film to the channel forming region is different from a distance from an inner sidewall of the second sidewall insulating film to the channel forming region in the second direction." The Action cites Fig. 7 of Orlowski and asserts that the recited distances are different. However, the rejection does not identify any disclosure in Orlowski describing first and second sidewall insulating films having inner sidewalls positioned at different distances from the channel forming region, nor does Orlowski otherwise describe an intentionally asymmetric spacer arrangement relative to the channel region. Rather, Orlowski consistently describes opposing spacers 28 formed along opposite sides of the gate opening and used as corresponding structures in the formation of the FinFET device.
The examiner respectfully submits that drawings can anticipate claims if they clearly show the structure which is claimed, and it does not matter if the feature shown is unintended or unexplained in the specification. MPEP 2125. Figure 7 of Orlowski clearly depicts visibly different distances between channel region 16 and opposite sides of sidewall insulating film 28.
Applicant respectfully submits that the rejection relies solely upon an interpretation of the schematic illustration of Fig. 7. However, a non-scaled patent drawing cannot, without supporting disclosure, establish the specific dimensional relationship required by the claim. The fact that a schematic drawing may depict structures with minor visual differences does not constitute a teaching that the first and second sidewall insulating films are positioned such that their respective inner sidewalls are located at different distances from the channel forming region, as expressly recited in claim 25. Neither the cited portions of Orlowski nor analysis in the Action identifies any disclosure of this claimed asymmetric spacing relationship.
The examiner respectfully submits that the claim does not require specific numerical value, only that the spacing is “different”. A person of ordinary skill in the art would reasonably conclude from Fig. 7 of Orlowski that spacing between inner sidewalls sidewall insulating film 28 and channel 16 are different thus Orlowski teaches a distance from an inner sidewall of the first sidewall insulating film(right 28, Fig. 7, ¶0025) to the channel forming region(16, ¶0025) is different(Fig. 7) from a distance from an inner sidewall of the second sidewall insulating film(left 28, Fig. 7, ¶0025) to the fin shape channel forming region(16, ¶0025) in the first direction(vertical direction of Fig. 7).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA DYKES whose telephone number is (571)270-3161. The examiner can normally be reached M-F 9:30 am-5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LAURA M DYKES/Examiner, Art Unit 2892
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