DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims presented have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 6-12 are rejected under 35 U.S.C. 103 as being unpatentable over NOBORIO et al. (US20200235239A1) in view of Ono et al. (US20060157778A1).
Regarding claim 1, Fig.1 and Fig.2 of NOBORIO teaches a field effect transistor comprising:
a semiconductor substrate (see annotated Fig.1);
a plurality of trenches 11 (para.0052) disposed at a top surface of the semiconductor substrate (see annotated Fig.1);
a gate insulation film 12 (para.0053) disposed in each of the trenches 11;
a gate electrode 13 (para.0053) disposed in each of the trenches 11; and
a source electrode 15 (para.0049) covering the top surface of the semiconductor substrate,
wherein the trenches 11 respectively extend in a first direction (Y direction) at the top surface, and the trenches 11 are spaced apart in a direction perpendicular to the first direction (Y direction), the first direction (Y direction) being parallel to the top surface of the semiconductor substrate (see annotated Fig.1),
wherein the semiconductor substrate includes a plurality of inter-trench semiconductor regions (see annotated Fig.1), and each of the inter-trench semiconductor regions (see annotated Fig.1) is disposed between adjacent two of the trenches 11,
wherein the inter-trench semiconductor regions respectively include a plurality of source regions 8 (para.0047), a plurality of contact regions 10 (para.0050), and a plurality of body regions 6 (para.0046),
wherein each of the source regions 8 is an n-type and is in contact with the source electrode 15 and the gate insulation film 12,
wherein each of the contact regions 10 is a p-type and is in contact with the source electrode 15,
wherein each of the body regions 6 is the p-type and has lower p-type impurity concentration than each of the contact regions 10,
wherein each of the body regions 6 is in contact with the gate insulation film 12 at a side closer to a bottom surface of the semiconductor substrate than the source regions 8, and is in contact with corresponding one of the contact regions 10 and corresponding one of the source regions 8 at a side closer to the bottom surface of the semiconductor substrate than the contact regions 10 and the source regions 8,
wherein the semiconductor substrate (see annotated Fig.1) further includes:
a plurality of connection regions 7 (para.0046), each of which is the p-type;
a plurality of field relaxation regions 4 (para.0039), each of which is the p-type; and
a drift region 2/3/5 (para.0056) being the n-type,
wherein the connection regions 7 are disposed at a side closer to the bottom surface of the semiconductor substrate than the body regions 6,
wherein the connection regions 7 are connected to the body regions 6 at intersecting portions where the connection regions 7 respectively intersect the body regions 6,
wherein the field relaxation regions 4 are disposed at a side closer to the bottom surface of the semiconductor substrate than the connection regions 7 and the trenches 11,
wherein the field relaxation regions 4 extend in a third direction (Fig.2, para.0040, illustrates wherein layer 4 extends in the X direction, wherein X direction is the third direction) intersecting the first direction and the second direction in the top view of the semiconductor substrate (see annotated Fig.1), and are disposed to be spaced apart in a direction perpendicular to the third direction (X direction) in the top view of the semiconductor substrate,
wherein the field relaxation regions 4 are connected to the connection regions 7 at intersecting portions where the field relaxation regions 4 respectively intersect the connection regions 7,
wherein the drift region 2/3/5 is disposed at a first spacing portion between adjacent two of the connection regions 7, a second spacing portion between adjacent two of the field relaxation regions 4, and a location closer to the bottom surface of the semiconductor substrate than the field relaxation regions 4, and
wherein the drift region 2/3/5 is in contact with the body regions 6 at a side closer to the bottom surface of the semiconductor substrate than the body regions 6, and is in contact with the gate insulation film 12 at a side closer to the bottom surface of the semiconductor substrate than the gate insulation film 12.
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NOBORIO does not teach wherein the connection regions respectively extend in a second direction intersecting the first direction in a top view of the semiconductor substrate, and are disposed to be spaced apart in a direction perpendicular to the second direction in the top view of the semiconductor substrate.
Fig.2 of Ono teaches a power MOSFET includes an n-type drift layer and a p-type base layer formed in a layered manner on the n-type drift layer and wherein the n.sup.+-type source regions and the p.sup.+-type regions are arranged with a slant with respect to the longitudinal direction of the trench gates; wherein the connection regions 19 (para.0027, wherein regions 19 are arranged in a direction that is slant with respect to the longitudinal direction of the trench gates) respectively extend in a second direction intersecting the first direction in a top view of the semiconductor substrate, and are disposed to be spaced apart in a direction perpendicular to the second direction in the top view of the semiconductor substrate (wherein regions 19 are arranged to intersect the longitudinal direction of the trench gates).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have regions 19 arranged in a slant manner with respect to the longitudinal direction of the trench gates 17, as taught by Ono, in order to reduce the distance from each portion of the p-type base layer 11 located below each source region 18 to each p.sup.+-type region 19 which leads to the reduction of the underlying resistance (Ono, [para.0032]).
Regarding claim 2, Ono further teaches the field effect transistor according to claim 1, wherein each of the contact regions extends in the second direction to overlap corresponding one of the connection regions 19 (para.0027, wherein regions 19 are arranged in a direction that is slant with respect to the longitudinal direction of the trench gates) in the top view of the semiconductor substrate.
Regarding claim 3, Ono further teaches the field effect transistor according to claim 1, wherein the second direction obliquely intersects the first direction (para.0027, wherein the direction of regions 19 is the second direction and is slant with respect to the longitudinal direction (first direction) of the trench gates).
Regarding claim 4, Ono further teaches the field effect transistor according to claim 1, wherein each of the connection regions 19 (para.0027) has a side surface with a linear shape extending in the second direction (Ono, para.0027, wherein the direction of regions 19 is the second direction and is slant with respect to the longitudinal direction (first direction) of the trench gates).
Regarding claim 6, NOBORIO further teaches the field effect transistor according to Claim 1, wherein each of the field relaxation regions 4 (para.0039) extends longer in the third direction (X direction) than in the first direction (Y direction).
Regarding claim 7, NOBORIO further teaches the field effect transistor according to Claim 1, wherein each of the field relaxation regions 4 (para.0039) extends continuously across the trenches 11 (para.0052) in the third direction (X direction).
Regarding claim 8, NOBORIO further teaches the field effect transistor according to Claim 1, wherein each of the field relaxation regions 4 (para.0039) have lower p-type impurity concentration than each of the connection regions 7 (para.0046).
Regarding claim 9, the combination of NOBORIO and Ono further teaches the field effect transistor according to Claim 1, wherein each of the connection regions 7 (para.0046) extends in the first direction (Y direction) from a bottom surface of one of the trenches 11 (para.0052) to a bottom surface of adjacent one of the trenches 11.
Regarding claim 10, Ono further teaches the field effect transistor according to Claim 1, wherein each of the connection regions continuously extends across the trenches in the second direction (para. 0031, wherein the longitudinal direction of the trench gates 17 (forming direction of the trenches 14) crosses the forming direction of the p.sup.+-type regions 19 with a slant shown by the angle .alpha).
Regarding claim 11, NOBORIO further teaches the field effect transistor according to claim 1, the trenches 11 (para.0052) are spaced apart in the third direction (X direction) that is perpendicular to the first direction (Y direction).
Regarding claim 12, the combination of NOBORIO and Ono further teaches the field effect transistor according to Claim 1, wherein the second direction (Ono, para.0027, wherein the direction of regions 19 is the second direction and is slant with respect to the longitudinal direction (first direction) of the trench gates) and the third direction (NOBORIO, X direction) are parallel to the top surface of the semiconductor substrate (see annotated Fig.1).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT KIPKEMOI RONO whose telephone number is (571)270-5977. The examiner can normally be reached Mon-Fri, 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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