DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received 04 Aug 2022 for application number17/880,692. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/Declaration, and Claims.
Claims 1-40 and 42-43 are presented for examination.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 04 Aug 2022 were filed before the mailing of this Office Action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election of Species II, Modifications A3, B1, C6, D2, and E1 (claims 4-9, 13-15, 17, 19, 24-31, 36-40, and 43 are readable thereon) in the reply filed on 25 Jun 2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claims 1-3, 10-12, 16, 18, 20-23, 32-35, 39-40, and 43 have been withdrawn (Examiner notes that claims 39-40 are not listed as withdrawn in the Claims filed 25 Jun 2025).
Further, claim 25 has been withdrawn because this claim is directed towards a 2D material comprising graphene, which is grown using a non-elected species (i.e. Species I – see Specification, paragraph 0036).
Claim 27 has been withdrawn because this claim is directed towards a 2D material comprising compounds that are grown using a non-elected species/modification (i.e. Species I/Modifications A1/A2/B6 – see Specification, paragraphs 0036-0037).
Claim 31 has been withdrawn because this claim is directed towards a 2D material grown using a non-elected species/modification (i.e. Species I – see Specification, paragraph 0036).
Claims 37-38 have been withdrawn because this claim is directed towards a 2D material (and steps) comprising compounds that are grown using a non-elected species/modification (i.e. Modifications A1/B6 – see Specification, paragraphs 0036-0037).
Claims 39-40 have been withdrawn because this claim is directed towards a 2D material (and steps) comprising compounds that are grown using a non-elected species/modification (i.e. Modifications A2/B6 – see Specification, paragraphs 0036-0037).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 43, 4-7, 13-15, 17, 19, 24, 26, 28-30, 36, and 42 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thomas (US 2018/0308684 A1) in view of Oezyilmaz et al. [hereinafter as Oezyilmaz] (US 2023/0154747 A1).
In reference to claim 43, Thomas teaches A method of fabricating a semiconductor device comprising the steps of:
providing a substrate [substrate 40; Fig. 6, para 0236];
forming a buffer layer [the bottom semiconductor or dielectric layer 42, hereinafter as “42a”; Fig. 6, para 0236] on the substrate [40], the buffer layer [42a] including a III-Nitride semiconductor [para 0125 discloses the second layer, i.e. 42, may be a III-Nitride semiconductor],
directly growing an 2D material layer [2D layer 41, above the bottom 42, hereinafter as “41a”; Fig. 6, para 0236] on the buffer layer [42a] using metal oxide chemical vapor deposition (MOCVD) [para 0070 discloses the use of MOCVD]; and
growing a semiconductor epitaxial layer [the semiconductor or dielectric layer 42 above 41a, hereinafter as “42b”; Fig. 6, para 0236] including III-Nitride [para 0125 discloses the second layer, i.e. 42, may be a III-Nitride semiconductor] on the 2D material layer [41a] using metal oxide chemical vapor deposition (MOCVD) [para 0070 discloses the use of MOCVD], including
a. introducing triethylboron (TEB, (C2H5)3B)) and ammonia (NH3) into a chamber containing the substrate [para 0199 discloses that TEB and ammonia gas are introduced in the reactor];
b. flowing a gas in the chamber [para 0199 discloses that TEB and ammonia gas are introduced in the reactor]; and
c. heating the substrate to a temperature between 700°C and 1500°C inclusive [para 0199 discloses a temperature of greater than 700°C].
However, Thomas does not explicitly teach that the 2D material layer is amorphous.
Oezyilmaz teaches that the 2D material layer is amorphous [para 0116 discloses a 2D layer of amorphous material].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Thomas and Oezyilmaz before the effective filing date of the claimed invention, to include the amorphous 2D material as disclosed by Oezyilmaz into the method of Thomas in order to obtain a semiconductor fabricating method that grows amorphous 2D material.
One of ordinary skill in the art would be motivated to obtain a semiconductor fabricating method that grows amorphous 2D material to provide the predictable result of improving mechanical properties thereby enhancing device performance.
In reference to claim 4, Thomas and Oezyilmaz teach the invention of claim 43.
Thomas teaches The method of claim 43, wherein the epitaxial layer [42b] comprises a plurality of epitaxial layers [para 0237 discloses that 42 may comprise multiple layers].
In reference to claim 5, Thomas and Oezyilmaz teach the invention of claim 43.
Thomas teaches The method of claim 43, wherein the epitaxial layer [42b] comprises gallium nitride, aluminum nitride, indium nitride, or hexagonal boron nitride [para 0125 discloses that the second layer, i.e. 42, may be GaN, AlN, BN, etc.].
In reference to claim 6, Thomas and Oezyilmaz teach the invention of claim 43.
Thomas teaches The method of claim 43, wherein the epitaxial layer [42b] comprises a ternary alloy [para 0125 discloses that the second layer, i.e. 42, may be ternary alloys, like AlGaN].
In reference to claim 7, Thomas and Oezyilmaz teach the invention of claim 6.
Thomas teaches The method of claim 6, wherein the ternary alloy comprises AlxGa1-xN, InxGa1-xN, BxGa1-xN, InxA1-xN, GaxA1-xN, BxA1-xN, AlxIn1-xN, GaxIn1-xN, or h-GaxB1-xN, where 0<x<1 [para 0125 discloses that the second layer, i.e. 42, may be ternary alloys, like AlGaN; Examiner notes that an AlGaN substance, for example, inherently satisfies the ratios required by the claim].
In reference to claim 13, Thomas and Oezyilmaz teach the invention of claim 43.
Thomas teaches The method of claim 43, wherein the step of growing forms the semiconductor epitaxial layer having a thickness ranging from 10 nm to 10 µm inclusive [para 0199 disclose a BN layer that is 50 nm, which is in the claimed range].
In reference to claim 14, Thomas and Oezyilmaz teach the invention of claim 43.
Thomas teaches The method of claim 43, wherein the step of growing the semiconductor epitaxial layer [42b] on the 2D material layer [41a] includes using metal oxide chemical vapor deposition [para 0070 discloses the use of MOCVD] to grow the semiconductor epitaxial layer [42b].
In reference to claim 15, Thomas and Oezyilmaz teach the invention of claim 14.
Thomas teaches The method of claim 14, wherein the step of using metal oxide chemical vapor deposition [para 0070 discloses the use of MOCVD] to form the semiconductor epitaxial layer [42b] includes the steps of flowing hydrogen gas [para 0199 discloses the flow of hydrogen] in a chamber [para 0199 discloses a reactor] containing the substrate [40] and heating the substrate [40] to a temperature between 700°C to 1,500°C inclusive [para 0199 discloses a temperature of greater than 700°C].
In reference to claim 17, Thomas and Oezyilmaz teach the invention of claim 43.
Thomas teaches The method of claim 43,wherein the buffer layer [42a] comprises gallium nitride, aluminum nitride, indium nitride, or hexagonal boron nitride [para 0125 discloses that the second layer, i.e. 42, may be GaN, AlN, BN, etc.].
In reference to claim 19, Thomas and Oezyilmaz teach the invention of claim 43.
Thomas teaches The method of claim 43, wherein the step of growing uses metal organic chemical vapor deposition [para 0070 discloses the use of MOCVD] to grow the 2D material layer [41a].
In reference to claim 24, Thomas and Oezyilmaz teach the invention of claim 43.
Thomas teaches The method of claim 43,wherein the 2D material layer [41a] includes a plurality of 2D material layers [para 0237 discloses that 41 may comprise multiple layers].
In reference to claim 26, Thomas and Oezyilmaz teach the invention of claim 43.
Oezyilmaz teaches The method of claim 43, wherein the 2D material layer comprises hexagonal boron nitride (h-BN), amorphous boron nitride (aBN), polycrystalline boron nitride or cubic boron nitride c-BN (c-BN) [para 0116 discloses a 2D layer of amorphous boron nitride].
In reference to claim 28, Thomas and Oezyilmaz teach the invention of claim 43.
Oezyilmaz teaches The method of claim 43, wherein the 2D material layer has a thickness in the range of 0.1 nm to 100 nm inclusive [para 0059 discloses that a monolayer, i.e. the 2D layer, may be from a few angstroms to a few nanometers thick, which is within the claimed range].
In reference to claim 29, Thomas and Oezyilmaz teach the invention of claim 43.
Thomas teaches The method of claim 43, wherein the substrate includes a plurality of layers [the substrate may be interpreted as substrate 40 including one or more bottom semiconductor or dielectric layers 42].
In reference to claim 30, Thomas and Oezyilmaz teach the invention of claim 43.
Thomas teaches The method of claim 43,wherein the substrate [40] comprises sapphire, silicon, silicon carbide, silicon dioxide, molybdenum, titanium, tantalum, copper, or hafnium [paras 0080-0089 discloses the substrate may be Si, SiC, sapphire, etc.].
In reference to claim 36, Thomas and Oezyilmaz teach the invention of claim 43.
Oezyilmaz teaches The method of claim 43, wherein the 2D material layer comprises hexagonal boron nitride (h-BN), polycrystalline boron nitride (p-BN), cubic boron nitride (c-BN) or amorphous boron nitride (a-BN) [para 0116 discloses a 2D layer of amorphous boron nitride].
In reference to claim 42, Thomas and Oezyilmaz teach the invention of claim 43.
However, although Thomas and Oezyilmaz do not explicitly teach The method of claim 43,wherein the temperature is approximately 1280°C, Thomas teaches a temperature of greater than 700°C [para 0199 discloses a temperature of greater than 700°C].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Thomas and Oezyilmaz before the effective filing date of the claimed invention, to modify the temperature of Thomas to be approximately 1280°C, as it was well-known to use temperatures of approximately 1280°C in a MOCVD process to produce predictable results, and through routine optimization.
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thomas in view of Oezyilmaz further in view of Ryou et al. [hereinafter as Ryou] (US 2019/0198313 A1).
In reference to claim 8, Thomas and Oezyilmaz teach the invention of claim 43.
However, Thomas and Oezyilmaz do not explicitly teach The method of claim 43, wherein the epitaxial layer comprises a quaternary alloy.
Ryou teaches The method of claim 43, wherein the epitaxial layer comprises a quaternary alloy [para 0060 disclose an epitaxially grown layer made of AlxInyGa1-x-yN, i.e. a quaternary alloy].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Thomas, Oezyilmaz, and Ryou before the effective filing date of the claimed invention, to include the quaternary alloy as disclosed by Ryou into the method of Thomas and Oezyilmaz in order to obtain a semiconductor fabricating method that grows an epitaxial layer made of a quaternary alloy.
One of ordinary skill in the art would be motivated to obtain a semiconductor fabricating method that grows an epitaxial layer made of a quaternary alloy to provide the predictable result of having higher electron mobility and bandgap, thereby improving device performance.
In reference to claim 9, Thomas, Oezyilmaz, and Ryou teach the invention of claim 8.
Ryou teaches The method of claim 8, wherein the quaternary alloy comprises AlxInyGa1-x-yN,InxGayAl1-x-yN, or AlxGayIn1-x-yN, where 0 < x < 1 and 0< y < 1 [para 0060 disclose an epitaxially grown layer made of AlxInyGa1-x-yN, i.e. a quaternary alloy].
Conclusion
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/ANDREW CHUNG/
Examiner, Art Unit 2898