Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/9/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 18 (and dependent claims 19-20 and 29 dependent therefrom) and 27 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 recites the limitation “the lowermost portions of the lower surfaces of the first and second buffer patterns” in lines 23-24. There is insufficient antecedent basis for this limitation with respect to the first buffer pattern in the claim. For the sake of compact prosecution, claim 18 is interpreted in the instant Office action as follows: “the lowermost portions of the lower surfaces of the first and second buffer patterns” is equivalent to “the lowermost surface of the first buffer pattern and the lowermost portion of the lower surface of the second buffer pattern” based on antecedence earlier in the claim. This interpretation is to be confirmed by applicant in the next office action.
Claim 27 recites the limitation “the upper surface of the substrate” in line. There is insufficient antecedent basis for this limitation in the claim. For the sake of compact prosecution, claim 27 is interpreted in the instant Office action as follows: “the upper surface of the substrate” is equivalent to “the lower surface of the substrate” based on antecedence in claim 1. This interpretation is to be confirmed by applicant in the next office action.
Claim 27 recites the limitation “the uppermost surface of the second buffer pattern” in lines 3-4. There is insufficient antecedent basis for this limitation in the claim. For the sake of compact prosecution, claim 27 is interpreted in the instant Office action as follows: “the uppermost surface of the second buffer pattern” is equivalent to “the uppermost portion of the upper surface of the second buffer pattern” based on antecedence in claim 1. This interpretation is to be confirmed by applicant in the next office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5-10, 12-13, 16-20, and 27-29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 20200402981 A1).
Regarding claim 1, Kim discloses a semiconductor device (Fig. 3), comprising:
active regions (105) defined by a device isolation region (110) in a substrate (100);
trenches (“trenches” being the shape of the device enclosing the gates; [0021]: “first gate structure”) extending lengthwise in a first direction (1st Direction. See top-down view in Fig. 2 showing “extending lengthwise”) to intersect the active regions ([0021]: “through the second active pattern 105 and the isolation pattern 110”);
buried gate structures (160) buried in the trenches, respectively, and having upper surfaces located on a level lower than a level of upper surfaces of the active regions (See annotated figure);
a buffer structure (320/375/425) covering the active regions (indirectly vertically covering at least a portion), the device isolation region (directly vertically covering at least a portion), and the buried gate structures (vertically covering);
bit line structures (305) extending lengthwise in a second direction (2nd Direction. See top-down view in Fig. 2 showing “extending lengthwise”) intersecting the first direction (perpendicular intersecting) on the active regions (vertically on) and connected to the active regions (directly connected);
spacer structures (315) that cover sidewalls of the bit line structures (directly cover in the 1st direction) and are disposed on the buffer structure (vertically on);
storage node contacts (405) between the bit line structures (between in the 1st direction), penetrating through the buffer structure (405 is vertically higher and lower than the entirety of the buffer structure, thus “penetrating through”) and in contact with the active regions (direct contact); and
capacitor structures (540) in contact with (electrical contact) an upper surface of the storage node contacts,
wherein the buffer structure includes:
a first buffer pattern (320) extending along profiles of the upper surfaces of the active regions (indirectly on), the device isolation region (indirectly on), and the buried gate structures (indirectly on) and having an upper surface including concave portions (See annotated figure);
a second buffer pattern (375) including at least first portions filling (upper portions at least partially filling) the concave portions of the upper surface of the first buffer pattern; and
a third buffer pattern (425) on the first buffer pattern and the second buffer pattern,
wherein each of the bit line structures includes a first portion (a portion of 265, See annotated figure) on an upper surface of the buffer structure and second portions penetrating through the buffer structure (a portion of 265, See annotated figure),
wherein a lowermost portion of a lower surface of the second buffer pattern (C, See annotated figure) is at a vertical level farther away from a lower surface of the substrate in a third direction (See annotated figure for direction designation) than a vertical level of a lowermost portion of a lower surface of the first buffer pattern (A, See annotated figure), the third direction being perpendicular to the first and second directions (these directions are chosen as perpendicular),
wherein an uppermost portion of an upper surface of the second buffer pattern (D, See annotated figure) is at a vertical level farther away from the lower surface of the substrate in the third direction than a vertical level of an uppermost portion of the upper surface of the first buffer pattern (B, See annotated figure),
wherein the lowermost portions of the lower surfaces of the first and second buffer patterns face the substrate (these surfaces face towards 105 in the vertical direction),
wherein the uppermost portions of the upper surfaces of the first and second buffer patterns face away from the substrate in the third direction (these surfaces face away from 100 in the vertical direction),
wherein the spacer structures are in contact with side surfaces of the first portion of the bit line structure (315 is in direct contact with 305 in the 1st direction), and
wherein the third buffer pattern is in contact (indirect contact) with a lower surface of the first portion of the bit line structure.
Illustrated below is Fig. 2 and a marked and annotated figure of Fig. 3 of Kim.
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Regarding claim 2, Kim discloses the semiconductor device of claim 1 (Fig. 3), wherein the concave portions of the upper surface of the first buffer pattern are located on (indirectly on) the buried gate structures, and wherein the first portions of the second buffer pattern vertically overlap the buried gate structures (at least some of the first portions of 305/265 vertically overlap gates 160, as shown in the top-down view of Fig. 2).
Regarding claim 6, Kim discloses the semiconductor device of claim 1 (Fig. 3), wherein the second buffer pattern further includes second portions (lower portions) located on the first buffer pattern (vertically lower and on by being a single integral pattern) and connecting the first portions to each other (indirectly connecting by being inclusive within the same device).
Regarding claim 7, Kim discloses the semiconductor device of claim 6 (Fig. 3), wherein a thickness of the second portions (1st direction thickness) is smaller than a thickness of the first portions (1st direction thickness. Note: thickness is smaller because of the rounded tapering point.).
Regarding claim 8, Kim discloses the semiconductor device of claim 6 (Fig. 3), wherein the second portions are located on the first buffer pattern (at least indirectly on) located on the upper surfaces of the active regions and the device isolation region.
Regarding claim 9, Kim discloses the semiconductor device of claim 1 (Fig. 3), wherein a thickness of the first buffer pattern (1st direction thickness of an entirety of the pattern) is greater than a thickness of the third buffer pattern (1st direction thickness. Note: thickness is greater because there is at least a portion of 425 vertically overlapping 320 that is narrower than 320).
Regarding claim 10, Kim discloses the semiconductor device of claim 1 (Fig. 3), wherein each of the buried gate structures includes a word line (140) in a corresponding one of the trenches and a capping pattern (150) located on the word line (vertically on).
Regarding claim 27 as noted in the 112(b) rejections, Kim discloses the semiconductor device of claim 1 (Fig. 3), wherein an uppermost surface of the third buffer pattern (F, See annotated figure) is at a vertical level farther away from the lower surface of the substrate than the vertical level of the uppermost portion of the upper surface of the second buffer pattern (F is vertically farther from 100 than D).
Note that claim 1 was previously addressed above, however, it’s being addressed differently here based on the reading of the reference, particularly to the assignment of the third buffer pattern in order to address the dependent claim 5.
Regarding claim 1, Kim discloses a semiconductor device (Fig. 3), comprising:
active regions (105) defined by a device isolation region (110) in a substrate (100);
trenches (“trenches” being the shape of the device enclosing the gates; [0021]: “first gate structure”) extending lengthwise in a first direction (1st Direction. See top-down view in Fig. 2 showing “extending lengthwise”) to intersect the active regions ([0021]: “through the second active pattern 105 and the isolation pattern 110”);
buried gate structures (160) buried in the trenches, respectively, and having upper surfaces located on a level lower than a level of upper surfaces of the active regions (See annotated figure);
a buffer structure (320/375/185) covering the active regions (directly vertically covering at least a portion), the device isolation region (directly vertically covering at least a portion), and the buried gate structures (vertically covering);
bit line structures (305) extending lengthwise in a second direction (2nd Direction. See top-down view in Fig. 2 showing “extending lengthwise”) intersecting the first direction (perpendicular intersecting) on the active regions (vertically on) and connected to the active regions (directly connected);
spacer structures (315) that cover sidewalls of the bit line structures (directly cover in the 1st direction) and are disposed on the buffer structure (vertically on);
storage node contacts (405) between the bit line structures (between in the 1st direction), penetrating through the buffer structure (405 is vertically higher and lower than the entirety of the buffer structure, thus “penetrating through”) and in contact with the active regions (direct contact); and
capacitor structures (540) in contact with (electrical contact) an upper surface of the storage node contacts,
wherein the buffer structure includes:
a first buffer pattern (320) extending along profiles of the upper surfaces of the active regions (indirectly on), the device isolation region (indirectly on), and the buried gate structures (indirectly on) and having an upper surface including concave portions (See annotated figure);
a second buffer pattern (375) including at least first portions filling (partially filling) the concave portions of the upper surface of the first buffer pattern; and
a third buffer pattern (185) on the first buffer pattern and the second buffer pattern (indirectly on),
wherein each of the bit line structures includes a first portion (a portion of 265, See annotated figure) on an upper surface of the buffer structure and second portions penetrating through the buffer structure (a portion of 265, See annotated figure),
wherein a lowermost portion of a lower surface of the second buffer pattern (C, See annotated figure) is at a vertical level farther away from a lower surface of the substrate in a third direction (See annotated figure for direction designation) than a vertical level of a lowermost portion of a lower surface of the first buffer pattern (A, See annotated figure), the third direction being perpendicular to the first and second directions (these directions are chosen as perpendicular),
wherein an uppermost portion of an upper surface of the second buffer pattern (D, See annotated figure) is at a vertical level farther away from the lower surface of the substrate in the third direction than a vertical level of an uppermost portion of the upper surface of the first buffer pattern (B, See annotated figure),
wherein the lowermost portions of the lower surfaces of the first and second buffer patterns face the substrate (these surfaces face towards 105 in the vertical direction),
wherein the uppermost portions of the upper surfaces of the first and second buffer patterns face away from the substrate in the third direction (these surfaces face away from 100 in the vertical direction),
wherein the spacer structures are in contact with side surfaces of the first portion of the bit line structure (315 is in direct contact with 305 in the 1st direction), and
wherein the third buffer pattern is in contact (indirect contact) with a lower surface of the first portion of the bit line structure.
Regarding claim 5, Kim discloses the semiconductor device of claim 1 (Fig. 3), wherein the first buffer pattern and the third buffer pattern include silicon oxide ([0042]: “insulation patterns 185 and 320 may include an oxide, e.g., silicon oxide”), and wherein the second buffer pattern includes silicon nitride ([0039]: “315, 375 and 425 may include a nitride, e.g., silicon nitride”).
Regarding independent claim 12, Kim discloses a semiconductor device (Fig. 3), comprising:
active regions (105) defined by a device isolation region (110) in a substrate (100);
buried gate structures (160) intersecting the active regions ([0021]: “through the second active pattern 105 and the isolation pattern 110”);
word lines (140) buried in the substrate, extending lengthwise in a first direction (1st Direction. See top-down view in Fig. 2 showing “extending lengthwise”), and located on a level lower than a level of upper surfaces of the active regions (See annotated figure);
capping patterns (150) buried in the substrate, located on the word lines (vertically on), and having upper surfaces (at least a portion of the Upper Surfaces of 140, See annotated figure) located on a level lower than a level of the upper surfaces of the active regions;
a buffer structure (320/375/185) on the device isolation region (directly vertically covering at least a portion), the active regions (directly vertically covering at least a portion), and the capping patterns (indirectly on);
bit line structures (305) extending lengthwise in a second direction (2nd Direction. See top-down view in Fig. 2 showing “extending lengthwise”) intersecting the first direction (perpendicular intersecting) on the active regions (vertically on) and connected to the active regions (directly connected); and
spacer structures (315) that cover sidewalls of the bit line structures (directly cover in the 1st direction) and are disposed on the buffer structure (vertically on),
wherein each of the bit line structures includes a first portion (a portion of 265, See annotated figure) on an upper surface of the buffer structure and second portions penetrating through the buffer structure (a portion of 265, See annotated figure),
wherein the buffer structure includes a first region (a region including upper 320 and vertically overlapping 105/110) on the active regions (vertically on) and the device isolation region (vertically on), and a second region (a region including lower 320 and vertically overlapping 105/110) on the capping patterns (indirectly on),
wherein the first region has a first thickness (1st direction thickness of an upper portion of 320),
wherein the second region has a second thickness (1st direction thickness of a lower portion of 320) greater than the first thickness (“greater” because it includes an entirety of the u-shaped structure in the 1st direction),
wherein the buffer structure includes:
a first buffer pattern (320) extending along profiles of the upper surfaces of the active regions (indirectly on), the device isolation region (indirectly on), and the buried gate structures (indirectly on) and having an upper surface including concave portions (See annotated figure);
a second buffer pattern (375) including at least first portions filling (partially filling) the concave portions of the upper surface of the first buffer pattern; and
a third buffer pattern (185) that is on and in contact with the first buffer pattern (indirectly on and indirect contact), and below (185 is vertically at a level lower than at least some of pattern 375) and in contact with the second buffer pattern (indirect contact),
wherein a lowermost portion of a lower surface of the second buffer pattern (C, See annotated figure) is at a vertical level farther away from a lower surface of the substrate in a third direction (See annotated figure for direction designation) than a vertical level of a lowermost portion of a lower surface of the first buffer pattern (A, See annotated figure), the third direction being perpendicular to the first and second directions (these directions are chosen as perpendicular),
wherein an uppermost portion of an upper surface of the second buffer pattern (D, See annotated figure) is at a vertical level farther away from the lower surface of the substrate in the third direction than a vertical level of an uppermost portion of the upper surface of the first buffer pattern (B, See annotated figure),
wherein the lowermost portions of the lower surfaces of the first and second buffer patterns face the substrate (these surfaces face towards 105 in the vertical direction), and
wherein the uppermost portions of the upper surfaces of the first and second buffer patterns face away from the substrate in the third direction (these surfaces face away from 100 in the vertical direction).
Regarding claim 13, Kim discloses the semiconductor device of claim 12 (Fig. 3), wherein a lower surface of the buffer structure has a shape according to profiles of the upper surfaces of the substrate and the capping patterns (The method teaches the formation of the substrate and capping pattern profiles occurring up to method step of Fig. 11. The method teaches formation of the buffer structure occurs after these structures, beginning at Fig. 14. Thus, the lower surface of the buffer structure has a shape at least indirectly related to all shapes prior-formed.).
Regarding claim 16, Kim discloses the semiconductor device of claim 12 (Fig. 3), wherein the first region of the buffer structure includes at least a first silicon oxide layer (layer 320; [0042]: “insulation patterns 185 and 320 may include an oxide, e.g., silicon oxide”), and wherein the second region of the buffer structure includes the first silicon oxide layer and a silicon nitride layer ([0039]: “315, 375 and 425 may include a nitride, e.g., silicon nitride”) deposited on the first silicon oxide layer (375 is vertically higher and formed after 320, thus it is “deposited on” layer 320).
Regarding claim 17, Kim discloses the semiconductor device of claim 16 (Fig. 3), wherein the buffer structure further includes a second silicon oxide layer (layer 185; [0042]: “insulation patterns 185 and 320 may include an oxide, e.g., silicon oxide”) covering (indirectly covering in the 1st direction) the first silicon oxide layer and the silicon nitride layer in the first and second regions.
Note that claim 12 was previously addressed above, however, it’s being addressed differently here based on the reading of the reference, particularly to the assignment of the third buffer pattern in order to address the dependent claim 28.
Regarding independent claim 12, Kim discloses a semiconductor device (Fig. 3), comprising:
active regions (105) defined by a device isolation region (110) in a substrate (100);
buried gate structures (160) intersecting the active regions ([0021]: “through the second active pattern 105 and the isolation pattern 110”);
word lines (140) buried in the substrate, extending lengthwise in a first direction (1st Direction. See top-down view in Fig. 2 showing “extending lengthwise”), and located on a level lower than a level of upper surfaces of the active regions (See annotated figure);
capping patterns (150) buried in the substrate, located on the word lines (vertically on), and having upper surfaces (at least a portion of the Upper Surfaces of 140, See annotated figure) located on a level lower than a level of the upper surfaces of the active regions;
a buffer structure (320/375/330) on the device isolation region (directly vertically covering at least a portion), the active regions (directly vertically covering at least a portion), and the capping patterns (indirectly on);
bit line structures (305) extending lengthwise in a second direction (2nd Direction. See top-down view in Fig. 2 showing “extending lengthwise”) intersecting the first direction (perpendicular intersecting) on the active regions (vertically on) and connected to the active regions (directly connected); and
spacer structures (315) that cover sidewalls of the bit line structures (directly cover in the 1st direction) and are disposed on the buffer structure (vertically on),
wherein each of the bit line structures includes a first portion (a portion of 265, See annotated figure) on an upper surface of the buffer structure and second portions penetrating through the buffer structure (a portion of 265, See annotated figure),
wherein the buffer structure includes a first region (a region including upper 320 and vertically overlapping 105/110) on the active regions (vertically on) and the device isolation region (vertically on), and a second region (a region including lower 320 and vertically overlapping 105/110) on the capping patterns (indirectly on),
wherein the first region has a first thickness (1st direction thickness of an upper portion of 320),
wherein the second region has a second thickness (1st direction thickness of a lower portion of 320) greater than the first thickness (“greater” because it includes an entirety of the u-shaped structure in the 1st direction),
wherein the buffer structure includes:
a first buffer pattern (320) extending along profiles of the upper surfaces of the active regions (indirectly on), the device isolation region (indirectly on), and the buried gate structures (indirectly on) and having an upper surface including concave portions (See annotated figure);
a second buffer pattern (375) including at least first portions filling (partially filling) the concave portions of the upper surface of the first buffer pattern; and
a third buffer pattern (330) that is on and in contact with the first buffer pattern (directly on and directly contacting), and below (330 is vertically at a level lower than at least some of pattern 375) and in contact with the second buffer pattern (direct contact),
wherein a lowermost portion of a lower surface of the second buffer pattern (C, See annotated figure) is at a vertical level farther away from a lower surface of the substrate in a third direction (See annotated figure for direction designation) than a vertical level of a lowermost portion of a lower surface of the first buffer pattern (A, See annotated figure), the third direction being perpendicular to the first and second directions (these directions are chosen as perpendicular),
wherein an uppermost portion of an upper surface of the second buffer pattern (D, See annotated figure) is at a vertical level farther away from the lower surface of the substrate in the third direction than a vertical level of an uppermost portion of the upper surface of the first buffer pattern (B, See annotated figure),
wherein the lowermost portions of the lower surfaces of the first and second buffer patterns face the substrate (these surfaces face towards 105 in the vertical direction), and
wherein the uppermost portions of the upper surfaces of the first and second buffer patterns face away from the substrate in the third direction (these surfaces face away from 100 in the vertical direction).
Regarding claim 28, Kim discloses the semiconductor device of claim 12 (Fig. 3), wherein the buffer structure includes: the first region in which the first to third buffer patterns are stacked in sequence (a first/third/second sequence), and the second region in which the third buffer pattern is directly stacked on the first buffer pattern (330 is directly stacked on 320).
Regarding independent claim 18 as noted in the 112(b) rejection, Kim discloses a semiconductor device (Fig. 3), comprising:
an isolation region (110) defining an active region (105) within a substrate (100);
buried gate structures (160) intersecting the active region ([0021]: “through the second active pattern 105 and the isolation pattern 110”), extending lengthwise into the isolation region (extending lengthwise in the 1st Direction. See top-down view in Fig. 2 showing “extending lengthwise”), and having upper surfaces located on a level lower than a level of an upper surface of the active region (See annotated figure);
a first buffer pattern (320) on the buried gate structures (at least indirectly on) and the isolation region (indirectly on), and having an upper surface including concave portions (See annotated figure) on the buried gate structures (indirectly on);
a second buffer pattern (375) filling (partially filling) the concave portions of the upper surface of the first buffer pattern and including at least first portions (upper portions) vertically overlapping the buried gate structures (See the B-B´ cross-section of Fig. 3);
a bit line structure (305) on the active region (vertically on) and connected to the active region (directly connected); and
spacer structures (315) that cover sidewalls of the bit line structure (directly cover in the 1st direction) and are disposed on the second buffer pattern (vertically on),
wherein the bit line structure includes a first portion (a portion of 265, See annotated figure) on an upper surface of the second buffer pattern (indirectly on) and a second portion (a portion of 265, See annotated figure) penetrating through the first and second buffer patterns,
wherein the second buffer pattern is in contact with the first buffer pattern (at least indirect contact),
wherein a lowermost portion of a lower surface of the second buffer pattern (C, See annotated figure) is at a vertical level farther away from a lower surface of the substrate in a vertical direction (See annotated figure for direction designation) than a vertical level of a lowermost surface of the first buffer pattern (A, See annotated figure), the vertical direction being perpendicular to a horizontal upper surface of the isolation region (these directions are chosen as perpendicular),
wherein an uppermost portion of an upper surface of the second buffer pattern (D, See annotated figure) is at a vertical level farther away from the lower surface of the substrate in the vertical direction than a vertical level of an uppermost portion of the upper surface of the first buffer pattern (B, See annotated figure),
wherein the lowermost surface of the first buffer pattern and the lowermost portion of the lower surface of the second buffer pattern face the substrate (these surfaces face towards 105 in the vertical direction), and
wherein the uppermost portions of the upper surfaces of the first and second buffer patterns face away from the substrate in the vertical direction (these surfaces face away from 100 in the vertical direction).
Regarding claim 19, Kim discloses the semiconductor device of claim 18 (Fig. 3), wherein each of the buried gate structures includes a word line (140) and a capping pattern (150) on the word line (vertically on), and wherein the first buffer pattern is in contact with the capping pattern (indirect contact).
Regarding claim 20, Kim discloses the semiconductor device of claim 18 (Fig. 3), wherein the first portions of the second buffer pattern extend in a first horizontal direction (there is at least some thickness extending in the 1st direction), and wherein each of first and second portions of the bit line structure extends lengthwise in a second horizontal direction intersecting the first direction (2nd Direction. See top-down view in Fig. 2 showing “extends lengthwise”).
Regarding claim 29, Kim discloses the semiconductor device of claim 18 (Fig. 3), wherein the second buffer pattern includes: the first portions filling the concave portions of the first buffer pattern (the upper portions cited in the claim 18 rejection), and second portions (lower portions) disposed on the first buffer pattern (at least indirectly on) and connecting the first portions to each other (indirectly connecting by being inclusive within the same device).
Response to Arguments
Applicant's arguments filed 2/9/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claims independent 1, 12, and 18 that “Lee fails to disclose, inter alia, “wherein an uppermost portion […]” as recited in amended independent claim 1, and similarly recited in amended independent claims 12 and 18”. Remarks at pg. 14.
Examiner’s reply:
Applicant’s arguments with respect to claim(s) 1, 12, and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Kim is relied upon in the instant Office action as necessitated by the new limitations in the claim.
Applicant argues:
Applicant argues with respect to amended claims independent 1, 12, and 18 that “neither Ikeda, nor Ryu, nor any combination thereof, teaches or suggests all the recitations of amended independent claims 1, 12, and 18”. Remarks at pg. 14.
Examiner’s reply:
Applicant’s arguments with respect to claim(s) 1, 12, and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Kim is relied upon in the instant Office action as necessitated by the new limitations in the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817