Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 11, 2026 has been entered.
Response to Amendment
Amendment to claims 17 and 19 submitted March 11, 2026 is acknowledged and has since been entered. Cancellation of claim 18 and new claim 22 are further acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 17 and 19-20 are rejected under 35 U.S.C. 103 as being obvious over Wang (US 20200044070 A1) in further view of Ko (US 20200006557 A1).
Regarding Claim 17, Wang teaches a semiconductor structure (see Fig. 19), comprising:
a first transistor (see Fig. 18, defined by an upper left source/drain region 42 and gate stack 60) comprising:
a first fin (24) protruding from a substrate and spaced apart by an isolation feature (22, a shallow trench isolation, shown Fig. 19);
a first gate structure (60) over channel regions of the first fin (shown Fig. 19), wherein the first gate structure comprises a high-k dielectric layer (52, shown Fig. 19, see also [0036]) and a gate electrode (56) over the high-k dielectric layer, wherein the first gate structure extends lengthwise along a first direction (shown Fig. 18);
a first source/drain feature (42) disposed and spanning over the first fin (see also Fig. 17C);
a second transistor (see Fig. 18, defined by a lower left source/drain region 42 and gate stack 60) comprising:
a third fin (24) protruding from the substrate and spaced apart by the isolation feature;
a second gate structure (60) over channel regions of the third fin (shown Fig. 19);
a second source/drain feature (42) disposed and spanning over the third fin (see also Fig. 17C);
a first gate isolation structure (66 left) and a second gate isolation structure (66 right) each extending lengthwise along a second direction different from the first direction (see Fig. 19), wherein each of the first and second gate structures extends between the first and second gate isolation structures (as is understood by the repeating pattern shown in Fig. 18) and bottom surfaces of the first and second gate isolation structures are below bottom surfaces of the first and second gate structures (shown Fig. 19); and
a fin isolation structure (76) disposed between the first gate structure and the second gate structure (shown Fig. 19) in the second direction and between the first and second gate isolation structures in the first direction (shown Fig. 18), wherein the fin isolation structure provides isolation between the first transistor and the second transistor, and wherein in a cross-sectional view cut through the fin isolation structure and the first and second gate isolation structures, an entirety of a bottom surface (interpreted as a bottommost surface of the fin isolation structure) of the fin isolation structure is under a bottom surface of the first gate isolation structure (shown Fig. 19).
Wang does not explicitly teach patterning the semiconductor structure such that the first transistor comprises a second fin protruding from the substrate and the second transistor comprises a fourth fin protruding from the substrate.
Ko teaches a similar semiconductor structure (shown Figs. 12A-12C) wherein adjacent transistors separated by a fin cut structure (66, shown Fig. 12A) each comprise two fins protruding from the substrate (see also Fig. 12C).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the semiconductor structure of Wang with the teachings of Ko to accommodate other circuit requirements which may enable increased chip density (see also [0049]).
Specifically, this modification would teach that the first transistor of Wang further comprises a second fin structure protruding from the substrate and spaced apart by the isolation feature and the second transistor of Wang further comprises a fourth fin protruding from the substrate and spaced apart by the isolation feature.
Regarding Claim 19, Wang as modified by Ko teaches the semiconductor structure of claim 17, wherein the bottom surface of the first gate isolation structure is below a bottom surface of the isolation feature (shown Fig. 19).
Regarding Claim 20, Wang as modified by Ko teaches the semiconductor structure of claim 17, wherein the first fin is aligned with the third fin, and the second fin is aligned with the fourth fin (as modified by Ko, see also Ko: Fig. 12C).
Claims 22 is rejected under 35 U.S.C. 103 as being obvious over Wang (US 20200044070 A1) in view of Ko (US 20200006557 A1) and further in view of Huang (US 20220230926 A1).
Regarding Claim 22, Wang as modified by Ko teaches the semiconductor structure of claim 17, wherein the fin isolation structure includes a dielectric material layer (see Wang: [0040]). Wang and Ko do not explicitly teach that a fin isolation structure may include an air gap enclosed by a dielectric material layer.
Huang teaches a semiconductor structure wherein a fin isolation feature (shown Fig. 5) includes a void (60, see also [0031] describing the void being filled with air) enclosed by a dielectric material layer (58).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement a void enclosed by the dielectric material layer of Wang as this would decrease effective capacitance and parasitic capacitance of the resulting FinFETs, thus improving electrical performance of the semiconductor device (see also Huang: [0033]).
Specifically, this modification would teach that the fin isolation structure comprises an air gap enclosed by the dielectric material layer.
Response to Arguments
Applicant’s arguments with respect to claim 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claims 1-7, 9-16 and 21 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 1, Wang (US 20200044070 A1) being the most relevant prior art of record teaches a method (see Figs. 8A-18), comprising:
receiving a workpiece (see Fig. 8A) comprising:
a first semiconductor fin (24 left) and a second semiconductor fin (24 right) separated by a first isolation feature (22) over a substrate (20), and
a gate structure (60) comprising a first portion intersecting the first semiconductor fin and the second semiconductor fin and disposed directly over the first isolation feature (shown Fig. 8A, wherein the gate structure 60 extends over both a first fin and a second fin through ILD 48);
removing the first portion of the gate structure (shown Fig. 12A), portions of the first semiconductor fin, the second semiconductor fin (shown Fig. 14A), and the first isolation feature (shown Fig. 15A) disposed directly under the first portion of the gate structure to form a fin isolation trench (corresponding to opening 70 and recesses 72 and 74 shown Fig. 15A);
forming a dielectric layer (76) over the workpiece to substantially fill the fin isolation trench (shown Fig. 16A);
and planarizing the dielectric layer (shown Fig. 17A, see also [0041]) to form a fin isolation structure (76) in the fin isolation trench, wherein a bottom surface of the fin isolation structure is lower than a bottommost portion of the gate structure and is lower than a bottommost portion of the first isolation feature (shown Fig. 17A).
Wang further teaches a first etching process exposing a top surface of the gate electrode and a second etching process removing a first portion of the gate structure, the first and second semiconductor fin, and the first isolation feature under the first portion of the gate structure, thereby forming the fin isolation trench. The prior art does not explicitly teach or suggest the second etching process selectively removing a part of the first portion of the gate structure, wherein after the performing of the second etching process, the gate electrode extends over the first isolation feature and performing a third etching process to remove remaining parts of the first portion of the gate structure. The implementation of the second etching process advantageously increases aspect ratio of a CPODE trench as technologies progress toward smaller nodes.
As such, claim 1 is deemed patentable over the prior art. Claims 2-7, 9 and 21 are further deemed patentable due to their dependence on claim 1.
Regarding Claim 10, Wang (US 20200044070 A1) teaches a method, comprising:
receiving a workpiece (see Fig. 8A, prior to forming gate isolation structures and Fig. 9 for top-down view after formation of gate isolation structures) comprising:
a plurality of fins (24) extending lengthwise along a first direction (horizontal, shown Fig. 9) and over a substrate, a plurality of isolation features (22), wherein two adjacent fins of the plurality of fins are separated by a respective isolation feature of the plurality of isolation features (shown Fig. 9), and
a gate structure (60) extending lengthwise along a second direction (vertical, shown Fig. 9) and directly over the plurality of fins and the plurality of isolation features (see Figs. 8A and 9), the second direction being substantially perpendicular to the first direction;
forming a first trench and a second trench (see process described in [0033] to form gate isolation regions 66) to separate the gate structure into a first portion (see annotated below), a second portion (see annotated below), and a third portion (see annotated below), wherein the first portion is separated from the second portion and the third portion by the first trench and the second trench, respectively (shown Fig. 9);
forming a first isolation structure and a second isolation structure (66, shown Figs. 9 and 10) in the first trench and the second trench, respectively (described in [0033]);
after the forming of the first isolation structure and the second isolation structure, selectively removing the first portion of the gate structure (shown Figs. 12A-12C), portions of the plurality of fins and portions of the plurality of isolation features disposed directly under the first portion of the gate structure to form a third trench (shown Figs. 15A-15C); and
forming a third isolation structure (76, a fin isolation structure) in the third trench (shown Figs. 17A-17C).
PNG
media_image1.png
480
855
media_image1.png
Greyscale
Wang further teaches a first etching process exposing a top surface of the gate electrode and a second etching process removing a first portion of the gate structure, the first and second semiconductor fin, and the first isolation feature under the first portion of the gate structure, thereby forming the fin isolation trench. The prior art does not explicitly teach or suggest selectively recessing a part of the first portion of the gate structure, wherein, in a cross-sectional view cut through the plurality of fins, a top surface of the recessed first portion of the gate structure is planar and over top surfaces of the plurality of fins. The implementation of the selective recess process advantageously increases aspect ratio of a CPODE trench as technologies progress toward smaller nodes.
As such, claim 10 is deemed patentable over the prior art. Claims 11-16 are further deemed patentable due to their dependence on claim 10.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CASEY PAUL BOATMAN whose telephone number is (703)756-4778. The examiner can normally be reached M-F 7:30 AM - 5:30 PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.P.B./Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
Prosecution Insights