DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
Examiner notes the Remarks filed 10/23/2025 failed to acknowledge the objection to the specification in the Non-Final Rejection dated 07/24/2025. For clarity, the same objection from the Non-Final Rejection is restated below.
The disclosure is objected to because of the following informalities: Paragraph [0040] of the Applicant’s specification reads “Epitaxial source/drain structures 142 and 144...” Examiner notes that this appears to be a typographical error as the epitaxial source/drain structures are labeled as 162 and 164 in the remainder of the specification.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The previous rejection of claims 1-7 under 35 U.S.C. 112(b) has been withdrawn in light of the amendments made to claim 1.
The previous rejection of claim 12 under 35 U.S.C 112(b) has been withdrawn in light of the remarks made by the Applicant in the remarks filed on 10/23/2025.
Claim Objections
Claim 4 is objected to because of the following informalities: Examiner notes that line 2 of claim 4 reads “... over the epitaxial source/drain structures ...” which still includes the plural form of “structures” where claims 1-3 were amended to the singular form of “the epitaxial source/drain structure”. Appropriate correction is required.
Response to Amendment
Examiner acknowledges the amendments made to claims 1-3,8,9 and 21. Claims 15-20 stand as cancelled. No new claims have been added.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-14 and 21-26 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 21 and 22-26 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (hereinafter Yang) (US 20200105930 A1) in view of Pal et al. (hereinafter Pal) (US 20190252239 A1)
The applied Yang reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Regarding claim 21, Yang discloses
A method (See steps in Fig. 1) (Para. [0013]), comprising:
forming a semiconductor fin [204A,204B] (Para. [0023]) over a substrate [202] (Para. [0016]) (Step 102 Fig. 1);
forming isolation structures [203] laterally surrounding the semiconductor fin [204A,204B] (Para. [0018]) (Step 102 Fig. 1);
forming a gate structure [210] (Para. [0019]) over the semiconductor fin [204A,204B] (Para. [0019]) (Step 102 Fig. 1);
forming a gate spacer [220,222,224] (Para. [0032,0033]) along a sidewall of the gate structure [210] (Para. [0025]), wherein the gate spacer comprises:
a first spacer layer [220] (Para. [0024]);
a second spacer layer [222] (Para. [0025]) over the first spacer layer [220] (Para. [0025]); and
a third spacer layer [226] (Para. [0033]) over the second spacer layer [222] (Para. [0033]), wherein in a first cross-sectional view along the isolation structures, the third spacer layer [226] interfaces with the first spacer layer [210] (See Fig. 16A), a top surface of the second spacer layer [222] is lower than a top surface of the third spacer layer [226], and the top surface of the third spacer layer [226] is lower than a top surface of the first spacer layer [220] (Fig. 16A); and
forming an epitaxial source/drain structure [230,232] over the semiconductor fin [204A,204B] (Para. [0028,0030]) (Fig. 8, Fig. 11), wherein in the first cross-sectional view [Figs. 16A, 16B], the epitaxial source/drain structure [232] interfaces with the third spacer layer [226] (See Figs. 16A,16B) (Para. [0035])
Yang fails to disclose,
wherein in the first cross-sectional view along the isolation structures, the third spacer layer interfaces with the first spacer layer and the second spacer layer
Pal discloses,
a third spacer layer [518] interfacing with a first spacer layer [514] and a second spacer layer [516] (Paras. [0054,0058])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the direct contact of the third spacer layer with the first and second spacer layers as shown in Pal with the spacer layers of the method of Yang for the purpose of limiting exposure of the second spacer layer (Pal Para. [0058])
Regarding claim 23, Yang in view of Pal as applied to claim 21 above further discloses in Yang,
wherein in the first cross-sectional view, a gap [space between 222 and 230] is vertically between the epitaxial source/drain structure [230] and the second spacer layer [222] of the gate spacer (Fig. 16B) (Para. [0031]).
Regarding claim 24, Yang in view of Pal as applied to claim 21 above further discloses in Yang,
wherein in a second cross-sectional view along the semiconductor fin, the top surface of the third spacer layer [226] is lower than a top surface of the epitaxial source/drain structure [230,232] (See Figs. 16A,16B).
Regarding claim 25, Yang in view of Pal as applied to claim 21 above further discloses in Yang,
wherein a dielectric constant of the second spacer layer [222] is lower than dielectric constants of the first [220] and third spacer layers [226] (Para. 0037]).
Examiner notes the third spacer layer [226] is disclosed to have a dielectric constant between about 5 and about 6, and the spacer layer [222] may be formed of the same material as the low-k dielectric layer [228] and therefore have a dielectric constant between about 2.5 and about 3.5 (Para. [0037]). The first spacer layer [220] is disclosed to be formed of (SiCN), which has a dielectric constant value higher than about 2.5 and about 2.5.
Further, the materials of the respective spacer layers of Yang are formed of the same materials listed as possibilities for the spacer layers of the claimed application in paragraphs [0018,0019 and 0029] of the Applicant’s specification.
Regarding claim 26, Yang in view of Pal as applied to claim 21 above further discloses in Yang,
wherein in the first cross-sectional view (Fig. 16B), the epitaxial source/drain structure [230] is in contact with the second [222] and third spacer layers [236] and is separated from the first spacer layer [220].
Examiner notes that the term “separated” is understood to mean “set apart” as disclosed in Merriam-Webster dictionary under the definition of “to set or keep apart”. See PTO-892 form.
Claims 1-3,6-10,13,14,21 and 23-26 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20200105930 A1) in view of Tsai et al. (hereinafter Tsai) (US 20170250281 A1) and Pal (US 20190252239 A1)
The applied Yang and Tsai references have a common assignee with the instant application. Based upon the earlier effectively filed date of the references, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Regarding claim 1, Yang discloses,
A method, comprising:
forming a semiconductor fin [204A, 204B] (Para. [0017]) over a substrate [202] (Para. [0016]); (Step 102 Fig. 1)
forming isolation structures [203] (Para. [0018]) laterally surrounding the semiconductor fin [204A,204B] (Para. [0018]); (Step 102 Fig. 1)
forming a gate structure [210] (Para. [0019]) over the semiconductor fin [204A,204B] (Para. [0019]); (Step 102 Fig. 1)
forming a first spacer layer [220 Fig. 4A] (Para. [0024]) (Step 104 Fig. 1) and a second spacer layer [222 Fig. 5A] (Para. [0024]) (Step 106 Fig. 1) over the gate structure [210] and the semiconductor fin [204A,204B] (Para. [0024]);
etching back the second spacer layer [222] (Step 112 Fig. 1), such that a top surface of the second spacer layer [222] is lower than a top surface of the first spacer layer [220] (Para. [0032]) (See Figs. 12A and 13A);
after etching back the second spacer layer [222], forming a third spacer layer [226] (Step 114 Fig. 1) over the first spacer layer [220]
etching the first [220] and second [222] spacer layers and the semiconductor fin [204A,204B] to form a recess (Para. [0027,0029]) (Fig. 7, Fig. 10); and
forming an epitaxial source/drain structures [230,232] in the recesses (Para. [0028,0030]) (Fig. 8, Fig. 11).
Yang fails to disclose,
the third spacer layer interfacing the first spacer layer and the second spacer layer
after forming the third spacer layer etching the first, second, and third spacer layers and the semiconductor fin to form recesses
Tsai discloses,
etching first [116], second [117], third spacer layers [118] and a semiconductor fin [104] to form a recess [104R] (Para. [0016]) (Figs. 2E,2F)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the etching of all three spacer layers and semiconductor fin as shown by Tsai into the method of Yang for the purpose of allowing a selective etching of the spacer layers for a desired growth of the source and drain regions (Tsai Paras. [0016,0017]).
Yang in view of Tsai fails to disclose,
the third spacer layer interfacing the first spacer layer and the second spacer layer
Pal discloses,
a third spacer layer [518] interfacing with a first spacer layer [514] and a second spacer layer [516] (Paras. [0054,0058])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the direct contact of the third spacer layer with the first and second spacer layers as shown in Pal with the spacer layers of the modified method of Yang for the purpose of limiting exposure of the second spacer layer (Pal Para. [0058])
Regarding claim 2, Yang in view of Tsai and Pal as applied to claim 1 above further discloses in Yang,
further comprising etching back the third spacer layer [226] (Step 118 Fig. 1) to expose a sidewall of the first spacer layer [220] after forming the epitaxial source/drain structure [230,232] in the recess (Para. [0035]) (Fig. 16A).
Regarding claim 3, Yang in view of Tsai and Pal as applied to claim 2 above further discloses in Yang,
wherein etching back the third spacer layer [226] (Para. [0035]) is performed such that a top surface of the third spacer layer [226] is lower than a topmost end of the epitaxial source/drain structure [230,232] (See Fig 16B, 226 lower than top surface of 230 and 232).
Regarding claim 6, Yang in view of Tsai and Pal as applied to claim 1 above further discloses in Yang,
wherein,
forming the second spacer layer [222] (Step 106 Fig. 1) is performed such that the second spacer layer [222] has a first U-shape cross-section [See Fig. 5A] in a cross-sectional view along the isolation structures [203],
etching the first [220], second [222], and third spacer layers and the semiconductor fin [204A,204B] to form recesses (Fig. 7, Para. [0027]) is performed such that the second spacer layer [222] is changed to a second U-shape cross-section.
Examiner notes that although Yang does not directly show the second U-shape cross section, the first, second and third spacer layers and semiconductor fin of Yang in view of Tsai and Pal are etched back in the same manner shown in Fig. 5C of the claimed application, with the fins etch lower than a remaining portion of the first and second spacer layers between the semiconductor fins. Therefore, although the specific cross section along the isolation structures is not directly shown of the etching process, the reference of Yang in view of Tsai and Pal discloses the limitation of a second U-shape cross section.
Yang in view of Tsai and Pal as applied to claim 1 fails to disclose,
etching back the second spacer layer is performed such that the second spacer layer is changed from the first U-shape cross-section to a rectangular cross-section in the cross-sectional view along the isolation structures, and
etching the first, second, and third spacer layers and the semiconductor fin to form recesses is performed such that the second spacer layer is changed from the rectangular cross-section to a second U-shape cross-section.
Tsai discloses in Figs. 2E and 2F,
etching back a second spacer layer [117] (Para. [0015]) from the tops and outside of the fins [104] (Para. [0015]), leaving a rectangular portion of the second spacer layer [117]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the etching back of the second spacer layers of Tsai before the recessing of the spacer layers and fins of the modified method of Yang for the purpose of allowing a more selective growth of source and drain regions in the recessed portion.
Regarding claim 7, Yang in view of Tsai and Pal as applied to claim 1 above further discloses in Yang,
wherein the first [220] (Para. [0024]), second [222] (Para. [0025]), and third spacer layers [226] (Para. [0034]) are made of different dielectric materials.
Regarding claim 8, Yang discloses
A method (See steps in Fig. 1) (Para. [0013]), comprising:
forming first [204A] (Para. [0023]) and second semiconductor fins [204B] (Para. [0023]) over a substrate [202] (Para. [0016]) (Step 102 Fig. 1);
forming isolation structures [203] laterally surrounding the first and second semiconductor fins [204A,204B] (Para. [0018]) (Step 102 Fig. 1);
forming a gate structure [210] (Para. [0019]) over the first and second semiconductor fins [204A,204B] (Para. [0019]) (Step 102 Fig. 1);
forming a first spacer layer [220 Fig. 4A] (Para. [0024]) (Step 104 Fig. 1) and a second spacer layer [222 Fig. 5A] (Para. [0025]) (Step 106 Fig. 1) over the gate structure [210] and the first and second semiconductor fins [204A, 204B] (Figs. 4A and 5A) (Para. [0024,0025]);
etching back the second spacer layer [222] (Para. [0027]) (Figs. 7 and 10) (Step 112 Fig. 1) to remove portions of the second spacer layer [222] outside a space laterally [left of 204A (Fig. 7), right of 204B (Fig. 10)] between the first [204A Fig. 7] and second semiconductor fins [204B Fig. 10], wherein a remaining portion of the second spacer layer [222 Fig. 7] is laterally between the first and second semiconductor fins [right of 204A Fig.7] (Para. [0027]);
forming a third spacer layer [226 Fig. 14A] over the first [220] and second spacer layers [222] (Para. [0033]);
performing an etching process to etch the first [220] and second [222] spacer layers and the first and second semiconductor fins [204A,204B] to form recesses (Para. [0027,0029]); (Fig. 7, Fig. 10), wherein after the etching process is complete, the third spacer layer [226] interfaces with the first spacer layer [220] (Fig. 16A) (Para. [0035]); and
forming epitaxial source/drain structures [230,232] in the recesses (Para. [0028,0030]) (Fig. 8, Fig. 11), wherein in a first cross-sectional view along the isolation structures [Figs. 16A, 16B], one of the epitaxial source/drain structures [232] interfaces with the third spacer layer [226] (see Figs. 16A and 16B) (Para. [0035])
Yang fails to disclose,
performing an etching process to etch the first, second and third spacer layers
wherein after the etching process is complete, the third spacer layer interfaces with the first spacer layer and the second spacer layer;
Tsai discloses,
etching first [116], second [117], third spacer layers [118] and a semiconductor fin [104] to form a recess [104R] (Para. [0016]) (Figs. 2E,2F)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the etching of all three spacer layers and semiconductor fin as shown by Tsai into the method of Yang for the purpose of allowing a selective etching of the spacer layers for a desired growth of the source and drain regions (Tsai Paras. [0016,0017]).
Yang in view of Tsai fails to disclose,
wherein after the etching process is complete, the third spacer layer interfaces with the first spacer layer and the second spacer layer;
Pal discloses,
an etching process (Paras. [0054,0058]), wherein after the etching process is complete, the third spacer layer [518] interfaces with the first spacer layer [514] and the second spacer layer [516] (Paras. [0054,0058])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the direct contact of the third spacer layer with the first and second spacer layers as shown in Pal with the spacer layers of the modified method of Yang for the purpose of limiting exposure of the second spacer layer (Pal Para. [0058])
Regarding claim 9, Yang in view of Tsai and Pal as applied to claim 8 above further discloses in Yang,
wherein forming the third spacer layer [226] (Step 114 Fig. 1) is performed after etching back the second spacer layer [222] (Para. [0027]) (Figs. 7 and 10) (Step 112 Fig. 1)
Regarding claim 10, Yang in view of Tsai and Pal as applied to claim 9 above further discloses in Yang,
further comprising etching back the third spacer layer [226] (Para. [0035]) to expose a sidewall of the first spacer layer [220] (Fig. 16A).
Regarding claim 13, Yang in view of Tsai and Pal as applied to claim 8 above further discloses in Yang
wherein the second spacer layer [222] is thicker (Para. [0025]) than the first spacer layer [220] (Para. [0024]).
Regarding claim 14, Yang in view of Tsai and Pal as applied to claim 8 above further discloses in Fig. 5B of Yang,
wherein forming the first spacer layer [220] and the second spacer layer [222] is performed such that an entirety of the space laterally between the first and second semiconductor fins [204A,204B] is filled with the first spacer layer [220] and the second spacer layer [222] (Para. [0025]) (See Fig. 5B).
Claims 4,5 ,11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Tsai and Pal as applied to claims 2,8 and 21 above, and further in view of Chen et al. (hereinafter Chen) (US 20200135880 A1).
Regarding claim 4, Yang in view of Tsai and Pal discloses the method outlined in the rejection of claim 2 above but fails to disclose,
further comprising forming a contact etch stop layer over the epitaxial source/drain structures, wherein the contact etch stop layer is in contact with the first and third spacer layers.
Chen discloses in Fig. 13C,
forming a contact etch stop layer [94] (Para. [0043]) over epitaxial source/drain structures [92] (Para. [0043])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the contact etch stop layer of Chen between the low-k dielectric layer and device of Yang in view of Tsai and Pal for the purpose of providing a material having a different etch rate than the low-k dielectric layer above (Chen Para. [0043]), further protecting the device under the contact etch stop layer.
Regarding claim 5, Yang in view of Tsai, Pal and Chen as applied to claim 4 above further discloses,
wherein the contact etch stop layer [Chen 94] is separated from the second spacer layer [Yang 222] by the third spacer layer [226 Yang].
Examiner notes when the contact etch stop layer of Chen is placed over the source/drain structures of Yang in view of Tsai, the etch stop layer will be placed over the third spacer [226] and source/drain [230,232] of Fig. 16B of Yang. In this configuration, the third spacer layer [226] separates the etch stop layer above the source/drain regions from the second spacer [222] under the third spacer [226] shown in Fig. 16B.
Examiner notes that the term “separated” is understood to mean “set apart” as disclosed in Merriam-Webster dictionary under the definition of “to set or keep apart”. See PTO-892 form.
Regarding claim 11, Yang in view of Tsai and Pal discloses the method outlined in the rejection of claim 9 above and further discloses in Yang,
an interlayer dielectric layer [228 Fig. 17] (Para. [0037])
Yang in view of Tsai and Pal fails to disclose,
forming a contact etch stop layer over the epitaxial source/drain structures, wherein the contact etch stop layer is in contact with a sidewall of the first spacer layer;
and forming an interlayer dielectric layer over the contact etch stop layer.
Chen discloses,
forming a contact etch stop layer [94] (Para. [0043]) over epitaxial source/drain structures [92] (Para. [0043]) under an ILD [96] (Para. [0043])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the contact etch stop layer of Chen between the low-k dielectric layer and device of Yang in view of Tsai and Pal for the purpose of providing a material having a different etch rate than the low-k dielectric layer above (Chen Para. [0043]), further protecting the device under the contact etch stop layer.
Examiner notes when the contact etch stop layer of Chen is placed over the source/drain structures of Yang in view of Tsai, the etch stop layer will be placed over the third spacer [226] and source/drain [230,232] of Fig. 16B and the gate regions [210A,210B] of Yang. In this configuration, the contact etch stop layer will be in contact with a sidewall of the first spacer layer [220] shown in Fig. 16A.
Regarding claim 12, Yang in view of Tsai, Pal and Chen as applied to claim 11 above further discloses,
wherein the contact etch stop layer [Chen 94 Fig. 13] is separated from the remaining portion of the second spacer layer [Yang 222]
Examiner notes when the contact etch stop layer of Chen is placed over the source/drain structures of Yang in view of Tsai, the etch stop layer will be placed over the third spacer [226] and source/drain [230,232] of Fig. 16B of Yang. In this configuration, the third spacer layer [226] separates the etch stop layer above the source/drain regions from the second spacer [222] under the third spacer [226] shown in Fig. 16B.
Examiner notes that the term “separated” is understood to mean “set apart” as disclosed in Merriam-Webster dictionary under the definition of “to set or keep apart”. See PTO-892 form.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Pal as applied to claim 21 above, and further in view of Chen et al. (hereinafter Chen) (US 20200135880 A1).
Regarding claim 22, Yang in view of Pal discloses the method outlined in the rejection of claim 21 above but fails to disclose,
further comprising forming a contact etch stop layer over the epitaxial source/drain structure, wherein in the first cross-sectional view, the contact etch stop layer is in contact with the first spacer layer and the third spacer layer.
Chen discloses in Fig. 13,
forming a contact etch stop layer [94] (Para. [0043]) over epitaxial source/drain structures [92] (Para. [0043])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the contact etch stop layer of Chen between the low-k dielectric layer and device of Yang in view of Pal for the purpose of providing a material having a different etch rate than the low-k dielectric layer above (Chen Para. [0043]), further protecting the device under the contact etch stop layer.
Examiner notes when the contact etch stop layer of Chen is placed over the source/drain structures of Yang in view of Pal, the etch stop layer will be placed over the third spacer [226] and source/drain [230,232] of Fig. 16B and the gate regions [210A,210B] of Yang. In this configuration, the contact etch stop layer will be in contact with a sidewall of the first spacer layer [220] shown in Fig. 16A.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Examiner particularly notes (US 20200251571 A1) which discloses forming a third spacer layer after etching back a second spacer layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNTER J NELSON whose telephone number is (571)270-5318. The examiner can normally be reached Mon-Fri. 8:30am-5:00 ET.
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/H.J.N./Examiner, Art Unit 2828
/XINNING(Tom) NIU/Primary Examiner, Art Unit 2828