DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4, 9, 11 and 24-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over SUN (CN 202111121658.4 using US 20230100307 as a reference) in view of NAKANO (US 20130313635).
Regarding claim 1, SUN discloses a method of producing a power semiconductor device, the method comprising:
forming a plurality of trench gate structures (the gate trenches 101 and the layers in them, see fig 1, para 101) in an active cell region (the region B of the device in which the body and source will be formed, see fig 1, para 16 and fig 8, para 42) of a semiconductor substrate (semiconductor layer 110 and 120, see fig 1, para 18), the plurality of trench gate structures extending into an inactive cell region (the region A of the device in which the sources will not be formed, see fig 1, para 16 and fig 8) of the semiconductor substrate that adjoins the active cell region;
covering the plurality of trench gate structures with an electrically insulating material (fig 8, 141, para 43);
forming, using a common mask, first contact openings (the contact openings between the gates 131 in the right region B, see fig 9, para 45) in the electrically insulating material between adjacent trench gate structures in the active cell region and second contact openings (the openings 105 above the gates 132 in the left region A, see fig 9, para 45) vertically aligned with the trench gate structures in the inactive cell region; and
implanting, using a common implantation process (the implantation process through the mask, see fig 2, para 22), a dopant species (the ions, see para 22) into the semiconductor substrate (the dopants are implanted into 120, see fig 2, para 22) to form first counter-doped regions between the adjacent trench gate structures in the active cell region (the doped regions 121 in the right region B, see fig 2, para 22) and second counter-doped regions underneath the trench gate structures in the inactive cell region (the doped regions 122 below the trenches in the left region A, see fig 2, para 22).
SUN fails to explicitly disclose a method wherein the implanting a dopant species into the semiconductor substrate is done through the first contact openings and the second contact openings.
NAKANO teaches a method implanting, using a common implantation process (the implantation process shown in fig 3C that forms 28and 29 simultaneously, see fig 3C, para 155), a dopant species into the semiconductor substrate through the first contact openings and the second contact openings (the implantation is done through openings in 45 in the gate region and between gate regions, see fig 3C), to form first counter-doped regions between the adjacent trench gate structures (the regions 28 are formed between the trench gate structures, see fig 3C and 2, para 126) and second counter-doped regions underneath the trench gate structures (region 30 is formed under the trench gate structure, see fig 2 and 3C, para 127).
SUN and NAKANO are analogous art because they both are directed towards methods of making trench gate semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of SUN with the implantation through openings in an electrically insulating material of NAKANO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of SUN with the implantation through openings in an electrically insulating material of NAKANO in order to suppress an increase in the on-resistance (see NAKANO para 168).
Regarding claim 2, SUN and NAKANO disclose the method of claim 1.
SUN further discloses a method, further comprising:
after the common implantation process, forming first contacts in the first contact openings (the metal contacts 142 which contact 124 in the right device region, see fig 10, para 49) and second contacts in the second contact openings (the contacts 142 which contact 132 in the left region of the device, see fig 10, para 49),
wherein the first contacts and the second contacts are at different potentials (the different contacts 142 are capable of being held at different potentials, see fig 10, para 49-50).
Regarding claim 4, SUN and NAKANO disclose the method of claim 1.
SUN further discloses a method, wherein forming the first contact openings and the second contact openings comprises:
etching into the semiconductor substrate between the adjacent trench gate structures in the active cell region and into a gate electrode material of the trench gate structures in the inactive cell region (132 and 123 are etched in fig 9, see para 47).
Regarding claim 9, SUN and NAKANO disclose the method of claim 1, further comprising:
forming a trench shielding structure in the inactive cell region and that laterally surrounds the plurality of trench gate structures, wherein the trench shielding structure is electrically floating (the left-most conductor 132 which is not connected electrically to anything and therefore floating in fig 5, see fig 5, para 33);
forming, using the common mask, a third contact opening vertically aligned with the trench shielding structure in the inactive cell region (the far left contact opening in fig 2, see para 22); and
implanting, using the common implantation process, the dopant species into the semiconductor substrate to counter-dope the semiconductor substrate underneath the trench structure in the inactive cell region (a doped region 122 is formed below the left-most trench, see fig 2, para 23).
SUN fails to explicitly disclose a method wherein the implanting a dopant species into the semiconductor substrate is done through a contact opening.
NAKANO teaches a method comprising implanting, using the common implantation process, the dopant species into the semiconductor substrate through the third contact opening to counter-dope the semiconductor substrate underneath the trench structure (the region 29 underneath the gate trench 12 is doped, see fig 3C, para 155).
SUN and NAKANO are analogous art because they both are directed towards methods of making trench gate semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of SUN with the implantation through openings in an electrically insulating material of NAKANO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of SUN with the implantation through openings in an electrically insulating material of NAKANO in order to suppress an increase in the on-resistance (see NAKANO para 168).
Regarding claim 11, SUN and NAKANO disclose the method of claim 1, further comprising:
forming a trench structure in the inactive cell region (the left-most trench 101 in fig 1, see para 22);
forming, using the common mask, a third contact opening vertically aligned with the trench structure in the inactive cell region (the left-most opening 105 in region A, see fig 9); and
implanting, using the common implantation process, the dopant species into the semiconductor substrate to counter-dope the semiconductor substrate underneath the trench structure in the inactive cell region (a doped region 122 is formed below the left-most trench, see fig 2, para 23),
wherein the counter-doped semiconductor substrate underneath the trench structure in the inactive cell region is electrically floating (122 is not connected to anything electrically and is therefore floating, see fig 2).
SUN fails to explicitly disclose a method wherein the implanting a dopant species into the semiconductor substrate is done through a contact opening.
NAKANO teaches a method comprising implanting, using the common implantation process, the dopant species into the semiconductor substrate through the third contact opening (the implantation process shown in fig 3C which forms the p-doped regions 29 under the gate trench through a contact opening in 45, see fig 3C, para 155) to counter-dope the semiconductor substrate underneath the trench structure (29 is formed under the gate trench 15, see fig 3C, para 121),
SUN and NAKANO are analogous art because they both are directed towards methods of making trench gate semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of SUN with the implantation through openings in an electrically insulating material of NAKANO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of SUN with the implantation through openings in an electrically insulating material of NAKANO in order to suppress an increase in the on-resistance (see NAKANO para 168).
Regarding claim 24, SUN and NAKANO disclose the method of claim 1.
SUN further discloses a method, wherein a drift zone extends below the plurality of trench gate structures in the active cell region and the inactive cell region (drift layer 120 extends below the gate trenches 101, see fig 2, para 18), and
wherein the first counter- doped regions form a superjunction structure with adjoining regions of the drift zone (121 forms a junction with 120, see fig 2, para 23).
Regarding claim 25, SUN and NAKANO disclose the method of claim 1.
SUN further discloses a method, wherein a drift zone extends below the plurality of trench gate structures in the active cell region and the inactive cell region (drift layer 120 extends below the gate trenches 101, see fig 2, para 18), and
wherein the second counter-doped regions form a superjunction structure with adjoining regions of the drift zone (122 forms a junction with 120, see fig 2, para 23).
Claim(s) 3, 5-6 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over SUN (CN 202111121658.4 using US 20230100307 as a reference) in view of NAKANO (US 20130313635) and further in view of SHIMOMURA (US 20230411512).
Regarding claim 3, SUN and NAKANO disclose the method of claim 2.
SUN fails to explicitly disclose a method, further comprising:
forming a patterned power metallization layer above the electrically insulating material such that a first part of the patterned power metallization layer contacts the first contacts and a second part of the patterned power metallization layer partly contacts the second contacts; and
forming a passivation on any part of the first contacts and the second contacts not covered by the patterned power metallization layer.
SHIMOMURA teaches a method, further comprising:
forming a patterned power metallization layer (the layer comprising SM and GM, see fig 12, para 58) above the electrically insulating material (SM and GM is formed above IL< see fig 12, para 58) such that a first part of the patterned power metallization layer contacts the first contacts (GM contacts the CP that contacts the gate electrode in PER, see fig 12, para 58) and a second part of the patterned power metallization layer partly contacts the second contacts (SM contacts the contacts CP in CR, see fig 12, para 58); and
forming a passivation on any part of the first contacts and the second contacts not covered by the patterned power metallization layer (CV is formed at least indirectly on CP, see fig 12, para 59).
SUN, NAKANO and SHIMOMURA are analogous art because they both are directed towards methods of making trench gate semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of SUN and NAKANO with the metallization of SHIMOMURA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of SUN and NAKANO with the metallization of SHIMOMURA in order to reduce the on-resistance (see SHIMOMURA para 72).
Regarding claim 5, SUN and NAKANO disclose the method of claim 1.
SUN fails to explicitly disclose a method, wherein in the inactive cell region, the plurality of trench gate structures intersect a trench gate bus structure that electrically interconnects a gate electrode material of the trench gate structures.
SHIMOMURA teaches a method, wherein in the inactive cell region, the plurality of trench gate structures intersect a trench gate bus structure that electrically interconnects a gate electrode material of the trench gate structures (gate pad GM extends directly above gate electrode GE in PER, see fig 12, para 58-59).
SUN, NAKANO and SHIMOMURA are analogous art because they both are directed towards methods of making trench gate semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of SUN and NAKANO with the metallization of SHIMOMURA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of SUN and NAKANO with the metallization of SHIMOMURA in order to reduce the on-resistance (see SHIMOMURA para 72).
Regarding claim 6, SUN and NAKANO disclose the method of claim 5.
SUN fails to explicitly disclose a method, further comprising:
forming, using the common mask, a third contact opening vertically aligned with the trench gate bus structure in the inactive cell region; and
implanting, using the common implantation process, the dopant species into the semiconductor substrate through the third contact opening to counter-dope the semiconductor substrate underneath the trench gate bus structure in the inactive cell region.
SHIMOMURA teaches a method the method of claim 5, further comprising:
forming, using the common mask, a third contact opening vertically aligned with the trench gate bus structure in the inactive cell region (the opening in IF1-3 formed in PER over the gate trench GT, see fig 3, para 41); and
implanting, using the common implantation process, the dopant species into the semiconductor substrate through the third contact opening to counter-dope the semiconductor substrate underneath the trench gate bus structure in the inactive cell region (forming NC in PER below the gate trench by ion implantation through a hole in IF1-3, see fig 3, para 41).
SUN, NAKANO and SHIMOMURA are analogous art because they both are directed towards methods of making trench gate semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of SUN and NAKANO with the metallization of SHIMOMURA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of SUN and NAKANO with the metallization of SHIMOMURA in order to reduce the on-resistance (see SHIMOMURA para 72).
Regarding claim 10, SUN and NAKANO disclose the method of claim 1.
SUN fails to explicitly disclose a method, further comprising:
forming a trench gate bus structure in the inactive cell region;
forming, using the common mask, a third contact opening vertically aligned with the trench gate bus structure in the inactive cell region;
implanting, using the common implantation process, the dopant species into the semiconductor substrate through the third contact opening to counter-dope the semiconductor substrate underneath the trench gate bus structure in the inactive cell region; and
electrically connecting a metal line in the trench gate bus structure to gate electrodes in the plurality of trench gate structures.
SHIMOMURA teaches a method, further comprising:
forming a trench gate bus structure in the inactive cell region (gate pad GM extends directly above gate electrode GE in PER, see fig 12, para 58-59);
forming, using the common mask, a third contact opening vertically aligned with the trench gate bus structure in the inactive cell region (the opening in IF1-3 formed in PER over the gate trench GT, see fig 3, para 41);
implanting, using the common implantation process, the dopant species into the semiconductor substrate through the third contact opening to counter-dope the semiconductor substrate underneath the trench gate bus structure in the inactive cell region (forming NC in PER below the gate trench by ion implantation through a hole in IF1-3, see fig 3, para 41); and
electrically connecting a metal line in the trench gate bus structure to gate electrodes in the plurality of trench gate structures (an electrode CP connects GE to GM in PER, see fig 12, para 57).
SUN, NAKANO and SHIMOMURA are analogous art because they both are directed towards methods of making trench gate semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of SUN and NAKANO with the metallization of SHIMOMURA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of SUN and NAKANO with the metallization of SHIMOMURA in order to reduce the on-resistance (see SHIMOMURA para 72).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over SUN (CN 202111121658.4 using US 20230100307 as a reference) in view of NAKANO (US 20130313635) and further in view of TAKAYA (US 20100224932).
Regarding claim 7, SUN and NAKANO disclose the method of claim 1.
SUN fails to explicitly disclose a method, wherein the first counter-doped regions and the second counter- doped regions merge with one another along a border region between the active cell region and the inactive cell region.
TAKAYA teaches a method, wherein the first counter-doped regions and the second counter-doped regions merge with one another along a border region between the active cell region and the inactive cell region (The doped regions 51 below the trenches merge with the doped regions 52 between the trenches, see fig 3, para 64).
SUN, NAKANO and TAKAYA are analogous art because they both are directed towards methods of making trench gate semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of SUN and NAKANO with the doped region configuration of TAKAYA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of SUN and NAKANO with the doped region configuration of TAKAYA in order to suppress an increase in the on-resistance (see TAKAYA para 16).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over SUN (CN 202111121658.4 using US 20230100307 as a reference) in view of NAKANO (US 20130313635) and further in view of HSIEH (US 20070114599).
Regarding claim 8, SUN and NAKANO disclose the method of claim 1.
SUN fails to explicitly disclose a method, wherein the dopant species is implanted into the semiconductor substrate through the first contact openings and the second contact openings at an angle relative to a first main surface of the semiconductor substrate.
HSIEH teaches a method, wherein the dopant species is implanted into the semiconductor substrate through the first contact openings and the second contact openings at an angle relative to a first main surface of the semiconductor substrate (the implant 228' through the contact openings 244 at an angle, see fig 5G, para 26).
SUN, NAKANO and HSIEH are analogous art because they both are directed towards methods of making trench gate semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of SUN and NAKANO with the angle deposition of HSIEH because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of SUN and NAKANO with the angle deposition of HSIEH in order to improve source contact (see HSIEH para 20).
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over SUN (CN 202111121658.4 using US 20230100307 as a reference) in view of NAKANO (US 20130313635) and further in view of KYOGOKU (US 11201210).
Regarding claim 23, SUN discloses a method of producing a power semiconductor device, the method comprising:
forming a plurality of trench gate structures (the gate trenches 101 and the layers in them, see fig 1, para 101) in an active cell region (the region B of the device in which the body and source will be formed, see fig 1, para 16 and fig 8, para 42) of a semiconductor substrate (semiconductor layer 110 and 120, see fig 1, para 18), the plurality of trench gate structures extending into an inactive cell region (the region A of the device in which the sources will not be formed, see fig 1, para 16 and fig 8) of the semiconductor substrate that adjoins the active cell region;
covering the plurality of trench gate structures with an electrically insulating material (fig 8, 141, para 43);
forming, using a common mask, first contact openings (the contact openings between the gates 131 in the right region B, see fig 9, para 45) in the electrically insulating material between adjacent trench gate structures in the active cell region and second contact openings (the openings 105 above the gates 132 in the left region A, see fig 9, para 45) vertically aligned with the trench gate structures in the inactive cell region; and
implanting, using a common implantation process (the implantation process through the mask, see fig 2, para 22), a dopant species (the ions, see para 22) into the semiconductor substrate (the dopants are implanted into 120, see fig 2, para 22) to form first counter-doped regions between the adjacent trench gate structures in the active cell region (the doped regions 121 in the right region B, see fig 2, para 22) and second counter-doped regions underneath the trench gate structures in the inactive cell region (the doped regions 122 below the trenches in the left region A, see fig 2, para 22).
SUN fails to explicitly disclose a method comprising implanting a dopant species into the semiconductor substrate through the first contact openings and the second contact openings; and
wherein the first counter-doped regions extend deeper into the semiconductor substrate than the second counter-doped regions.
NAKANO teaches a method comprising implanting, using a common implantation process (the implantation process shown in fig 3C that forms 28and 29 simultaneously, see fig 3C, para 155), a dopant species into the semiconductor substrate through the first contact openings and the second contact openings (the implantation is done through openings in 45 in the gate region and between gate regions, see fig 3C), to form first counter-doped regions between the adjacent trench gate structures (the regions 28 are formed between the trench gate structures, see fig 3C and 2, para 126) and second counter-doped regions underneath the trench gate structures (region 30 is formed under the trench gate structure, see fig 2 and 3C, para 127).
SUN and NAKANO are analogous art because they both are directed towards methods of making trench gate semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of SUN with the implantation through contact openings in an insulating layer of NAKANO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of SUN with the implantation through contact openings in an insulating layer of NAKANO in order to suppress an increase in the on-resistance (see NAKANO para 168).
SUN and NAKANO fails to explicitly disclose a method wherein the first counter-doped regions extend deeper into the semiconductor substrate than the second counter-doped regions.
KYOGOKU teaches a method wherein the first counter-doped regions extend deeper into the semiconductor substrate than the second counter-doped regions (the first counter-doped regions 34 between the gate trenches extend deeper into the substrate 26 than do the second doped regions 32 below the gate trenches, see fig 1, para 41).
SUN, NAKANO and KYOGOKU are analogous art because they both are directed towards methods of making trench gate semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of SUN and NAKANO with the doped region depth of KYOGOKU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of SUN and NAKANO with the doped region depth of KYOGOKU in order to reduce on-resistance (see KYOGOKU para 113).
Response to Arguments
Applicant's arguments filed 2/23/2026 have been fully considered but they are not persuasive.
Regarding claims 1 and 23, the applicant argues that SUN in view of NAKANO fail to disclose the claimed method because neither reference fully discloses a method comprising “implanting, using a common implantation process, a dopant species into the semiconductor substrate through the first contact openings and the second contact openings to form first counter-doped regions between the adjacent trench gate structures in the active cell region and second counter-doped regions underneath the trench gate structures in the inactive cell region”. This argument is unpersuasive. The primary reference used, SUN, discloses every part of that limitation except that the implantation is carried out through holes in an insulating layer on the substrate. SUN discloses, in figure 2, implanting, using a common implantation process (the implantation process through the mask 102, see fig 2, para 22), a dopant species (the ions, see fig 2, para 22) into the semiconductor substrate (the dopants are implanted into 120, see fig 2, para 22) to form first counter-doped regions between the adjacent trench gate structures in the active cell region (the doped regions 121 in the right region B between the trenches, see fig 2, para 22) and second counter-doped regions underneath the trench gate structures in the inactive cell region (the doped regions 122 below the trenches in the left region A, see fig 2, para 22); which differs from the claimed method only in that the implantation is performed through a mask 102 rather than through contact holes in the insulating layer 141 (see SUN fig 9, element 141, para 44). The secondary reference NAKANO discloses the implantation of doped regions below and between the gate trenches through holes in the insulating layer 45 (see NAKANO fig 3C, para 155) on the substrate 33 as opposed to a mask over the substrate. This is the thing that NAKANO is relied upon to disclose in the rejection.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
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