DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 01/22/2026.
Claims 1-12, 14-18, 25, 26, and new claim 27 are pending in this application.
Claims 13, and 19-24 have been cancelled.
Remarks
2. Applicant's arguments have been fully considered, but are moot in view of a new ground of rejection. See details below.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claims 25, 26, and 27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Paul et al. (US 10,840,146)
Regarding claim 25, Paul discloses a multi-stack semiconductor device comprising:
a substrate 20 (see fig. 15B);
a lower nanosheet transistor (below dielectric layer 48) comprising:
a lower channel structure 12;
a lower gate structure 70 surrounding the lower channel structure 12;
lower source/drain regions 44 at both ends of the lower channel structure 12; and
at least one lower inner spacer 42 isolating the lower source/drain regions 44 from the lower gate structure 70;
an upper nanosheet transistor (above dielectric layer 48), on the lower nanosheet transistor in a first direction (vertical or Z direction), and comprising:
an upper channel structure 12;
an upper gate structure 70 surrounding the upper channel structure 12;
upper source/drain regions 46 at both ends of the upper channel structure 12; and
at least one upper inner spacer 42 isolating the upper source/drain regions 46 from the upper gate structure 70; and
an isolation structure (comprising dielectric layer 48, portions of inner spacer 42 laterally in contact with dielectric layer 48, thin semiconductor layer 15, and portion of gate structure 70) between the lower and upper channel structures 12,
wherein the isolation structure comprises at least a portion of a gate dielectric layer (high-k gate dielectric layer and/or thin oxide layer comprised in the gate structure 70, see col. 9, lines 13-36) included in the lower and upper gate structures 70 and at least one isolation layer 15 (col. 3, lines 1-15) that is between the at least one lower inner spacer 42 and the at least one upper inner spacer 42 in the first direction (Z direction), and
wherein the at least one isolation layer 15 is disconnected in a second direction (lateral or X direction) by the gate dielectric layer (in the gate structure 70) in a portion of the isolation structure that is between the lower gate structure 70 and the upper gate structure 70 in the first direction, wherein the second direction intersects the first direction.
Regarding claim 26, Paul discloses the multi-stack semiconductor device of claim 25, wherein the at least one isolation layer 15 is disconnected in the second direction (X direction) by an interfacial layer (thin oxide layer, col. 9, line 13-36) included in the gate dielectric layer, and wherein the interfacial layer comprises silicon oxide or silicon oxynitride.
Regarding claim 27, Paul discloses the multi-stack semiconductor device of claim 25, wherein the at least one isolation layer 15 comprises a material having an etch selectivity which is the same as an etch selectivity of the lower and upper channel structures 12. See col. 3, lines 1-15.
Allowance
5. Claims 1-12, and 14-18 have been allowed.
Reasons for allowance can be found in Applicant’s argument/remarks of 08/28/2025.
Conclusion
6. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818
March 7, 2026
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