DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 1-20 are pending in this application.
Claims 11-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on February 20, 2025.
The Examiner notes that claims 1-10, 16-20 are examined and claims 11-15 are withdrawn.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed March 10, 2026. Claims 1, 5, 6, and 8 are amended. Claims 11-15 remain withdrawn. The Examiner notes that claims 1-10 and 16-20 are examined.
Response to Arguments
Applicant’s arguments, see pages 10-14, filed March 10, 2026, with respect to the rejections of claims 16 under 35 U.S.C. 103 have been fully considered and are persuasive. Specifically, the argument that the modification of Seng by Kim is not an obvious simple substitution because of the interconnections running through the dielectric elements of Seng is found persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of updated search and consideration (see below).
Applicant’s arguments with respect to objections to claims and specification have been fully considered and are persuasive. Objections to claims and specification have been withdrawn.
Claim Interpretation
The Examiner notes that the following limitations from claim 1 direct to a product-by-process claim limitation:
“a plurality of first non-conductive bonding structures each protruding from the first surface to a top surface of a corresponding one of the plurality of first non-conductive bonding structures;
a plurality of second non-conductive bonding structures each protruding from the second surface to a bottom surface of a corresponding one of the plurality of second non- conductive bonding structures;
wherein the first non-conductive bonding structure is directly bonded to the second non- conductive bonding structure by a dielectric-dielectric bond.”
The Examiner determines that when two non-conductive bonding structures are bonded by a dielectric-dielectric bond (known in the art for example as a “direct bond” or a “fusion bond”) the resulting product is identical to a dielectric structure consisting of a single material manufactured by other means. Therefore, the Examiner interprets any dielectric structure substantially identical to the claimed structure to read on the invention as claimed, even if it was formed by a different manufacturing process.
“When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not.” In re Spada, 911 F.2d 705, 709 (Fed. Cir. 1990). Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product. In re Best, supra.
Claim Rejections - 35 USC § 102/103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 8-10, 16, 18, and 20 are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Su (US 2013/0256895 A1).
With respect to claim 1, Su teaches in Fig. 3:
A semiconductor device assembly, comprising: a first semiconductor die (substrate 15, dielectric layer 130, and conductor pad 100a) having a first surface (top surface);
a first electrical contact (barrier film 110a which may be made of tantalum/tantalum nitride and interconnect structure 50a) coupled to the first semiconductor die (15, 130, and 100a) and protruding from the first surface (top surface) to an upper surface (upper surface of 50a) of the first electrical contact,
a plurality of first non-conductive bonding structures (bottom portion of support structure 70b, which may be a dielectric polymer) each protruding from the first surface (top of 130 which is part of the first die)
wherein a portion of the first surface between the first electrical contact (50a and 110a) and each of the plurality of first non-conductive bonding structures (70b) is void of the first electrical contact and the plurality of first non-conductive bonding structures (see Fig. 2),
and wherein the plurality of first non-conductive bonding structures (70b) are positioned peripheral to the first electrical contact with respect to a center of the first semiconductor die (para. 31, support structures 70a, 70b, 70c and 70d may be provided at the periphery of the semiconductor substrate);
a second semiconductor die having a second surface (substrate 20, dielectric 135, and conductor pad 105a);
a plurality of second non-conductive bonding structures (top portion of 70b) each protruding from the second surface (bottom of top semiconductor substrate)
a second electrical contact (micro bumps 55a and barrier film 115a) coupled to the second semiconductor die and protruding from the second surface to a lower surface of the second electrical contact (see Fig. 3),
wherein a portion of the second surface between the second electrical contact and each of the plurality of second non-conductive bonding structures is void of the second electrical contact and the plurality of second non-conductive bonding structures (see Fig. 3),
wherein the plurality of second non-conductive bonding structures are positioned peripheral to the second electrical contact with respect to a center of the second semiconductor die (see Fig. 5, two of the adhesive pillars 70A are at the outside of the device),
and a solder joint coupling the first electric contact to the second electric contact (solder interface 145),
Further, Su teaches a structure substantially identical to structure formed by the following product by process limitations:
a plurality of first non-conductive bonding structures each protruding from the first surface to a top surface of a corresponding one of the plurality of first non-conductive bonding structures (70b is equivalent to the first and second non-conductive bonding structures after they have been bonded together);
a plurality of second non-conductive bonding structures each protruding from the second surface to a bottom surface of a corresponding one of the plurality of second non- conductive bonding structures (70b is equivalent to the first and second non-conductive bonding structures after they have been bonded together);
and wherein the top surface of each of the plurality of first non- conductive bonding structures is coplanar with the upper surface of the first electrical contact (after bonding, the first and second bonding structure fuse together into a single structure, so the location of the upper surface of the non-conductive bonding structure does hold patentable weight),
and wherein the lower surface is spaced apart from a plane containing the bottom surface (after bonding, the first and second bonding structure fuse together into a single structure, so the location of the upper surface of the non-conductive bonding structure does hold patentable weight);
wherein the first non-conductive bonding structure is directly bonded to the second non- conductive bonding structure by a dielectric-dielectric bond (after a dielectric bond the non-conductive bonding structure is indistinguishable from a single dielectric structure).
In the event that Su does not anticipate the product-by-process limitations of claim 16, it would be obvious over Su to create a device that meets the product-by-process limitations because the difference between the claimed invention and the device of Su is that the dielectric bonding structure of the claimed invention was previously made from two different dielectric structures leading to only a slight difference in shape or chemical structure at the interface of the non-conductive bonding structure that the ordinary artisan would expect to have similar properties.
With respect to claim 2, Su further teaches:
further comprising a substrate (circuit board 25), wherein a third surface of the first semiconductor die (bottom of 15) couples to the substrate,
the third surface different than the first surface.
With respect to claim 3, Su further teaches:
further comprising an underfill material (underfill 80) disposed between the first semiconductor die (15, 130, and 100a) and the second semiconductor die (20, 135, and 105a).
With respect to claim 4, Su further teaches:
wherein the first electrical contact (50a and 110a) couples to a through-silicon via of the first semiconductor die (TSV 120a).
With respect to claim 8, Su further teaches:
a first cross section of the plurality of first non-conductive bonding structures and the first electrical contact along a first plane parallel to the first surface has a first area that is smaller than a second area of the first surface (bonding structures do not cover the full surface of the surface of the die);
or a second cross section of the plurality of second non-conductive bonding structures and the second electrical contact along a second plane parallel to the second surface has a third area that is smaller than a fourth area of the second surface.
With respect to claim 9, Su further teaches:
a third surface (bottom)of the first semiconductor die opposite the first surface, wherein first circuitry is disposed at the third surface;
or second circuitry (top) disposed at the second surface.
The Examiner takes the position that although circuitry disposed at the claimed surfaces is not explicitly stated in Su, in order for the conductive interconnects to connect circuitry within the two dies to teach other through the bond pads there must be circuitry at least disposed on the second surface.
In the event that the prior art does not teach circuitry disposed at the third or second surface, which the Examiner does not concede, it would be obvious to a person of ordinary skill in the art to meet the claim limitation because although Su does not explicitly state that the circuitry is disposed on the surface, Seng teaches that there is circuitry contained within the semiconductor dies and it would be obvious to rearrange the parts such that the circuitry is disposed at the surface (MPEP 2144.04(VI)(C)).
With respect to claim 10, Su further teaches:
wherein the first electrical contact and the second electrical contact are configured to communicatively couple the first semiconductor die and the second semiconductor die (first and second die are connected through 45a).
The Examiner notes that the limitation “are configured to communicatively couple the first semiconductor die and the second semiconductor die” recites an intended use of the semiconductor device assembly. For the purpose of this action, the Examiner takes the position that limitation is met as long as the prior art teaches two semiconductor dies electrically connected through a conducting bond.
With respect to claim 16, Su teaches:
A semiconductor device assembly, comprising:
a stack of multiple semiconductor dies, each semiconductor die of the multiple semiconductor dies coupled to another semiconductor die of the multiple semiconductor dies through one or more respective couplings (first die including semiconductor substrate 15, dielectric 130, and contacts 100a, second die including semiconductor substrate 20, dielectric 135, and contact 105a. The dies are connected through interconnect 45 and support structure 70b); and
the one or more respective couplings, each of the one or more respective couplings comprising:
a first respective non-conductive bonding structure protruding from a first respective semiconductor die (bottom portion of 70b);
a first respective electrical contact protruding from the first respective semiconductor die (interconnect structure 50a and barrier film 110a),
wherein a portion of the first respective semiconductor die is uncovered by the first respective non-conductive bonding structure and the first respective electrical contact between the first respective non- conductive bonding structure and the first respective electrical contact (see Fig. 3, a portion of the die is not covered by 70b, 110a, and 50a);
a second respective non-conductive bonding structure protruding from a second respective semiconductor die (top portion of 70b);
a second respective electrical contact protruding from the second respective semiconductor die (interconnect 55a and barrier film 115a),
wherein a portion of the second respective semiconductor die is uncovered by the second respective non-conductive bonding structure and the second respective electrical contact between the second respective non-conductive bonding structure and the second respective electrical contact (70b, 115a, and 55a does not cover the entire surface of the top die); and
a respective soldering joint (145) coupling the first respective electrical contact and the second respective electrical contact,
Further, Su teaches a structure substantially identical to structure formed by the following product by process limitations:
wherein the first respective non-conductive bonding structure is directly coupled to the second respective non-conductive bonding structure through a dielectric bond (a dielectric bond fuses two dielectric elements such that they are indistinguishable from a single dielectric element after the fusing)
In the event that Su does not anticipate the product-by-process limitations of claim 16, it would be obvious over Su to create a device that meets the product-by-process limitations because the difference between the claimed invention and the device of Su is that the dielectric bonding structure of the claimed invention was previously made from two different dielectric structures leading to only a slight difference in shape or chemical structure at the interface of the non-conductive bonding structure that the ordinary artisan would expect to have similar properties.
With respect to claim 18, Su further teaches:
further comprising a substrate (circuit board 25) coupled to the stack of multiple semiconductor dies.
With respect to claim 20, Su further teaches:
wherein each of the one or more respective couplings further comprises an underfill material (underfill material layer 80) disposed between the first respective semiconductor die and the second respective semiconductor die.
Claims 5-7, 17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Su (US 2013/0256895 A1) as applied to independent claims 1 and 16 above and further in view of Jun (US 2022/0415837 A1).
With respect to claim 5, Su teaches all limitations of claim 1 upon which claim 5 depends. Su fails to teach:
wherein the plurality of first non-conductive bonding structures and the plurality of second non-conductive bonding structures each comprises silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride, or a combination thereof.
Jun teaches:
wherein the plurality of first non-conductive bonding structures and the plurality of second non-conductive bonding structures each comprises silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride, or a combination thereof (para. 72 “. Examples of such dielectrics include, but are not limited to, any of various carbon doped oxide materials (such as an organosilicate glass), a porous SiOx material,”).
Su teaches the claimed invention except for a different dielectric material is used for a non-conductive bonding structure. Jun teaches it is known to use silicon oxide as a non-conductive bonding structure. The ordinary artisan would be motivated to use the claimed materials as the dielectric bonding structure for the purpose of improving stress absorption in the device and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
With respect to claim 6, Jun further teaches:
wherein the first non-conductive bonding structure (dielectric layer 315) comprises a different material than the second non-conductive bonding structure (dielectric layer 325). (para. 72 “In various embodiments, the first dielectric exhibits good stress absorption characteristics—e.g., wherein the first dielectric has a Young's modulus which (for example) is below 25 Gigapascals (GPa) and, in some embodiments, below 10 GPa. Examples of such dielectrics include, but are not limited to, any of various carbon doped oxide materials (such as an organosilicate glass), a porous SiOx material, or the like. By contrast, the second dielectric—of the one or more second (interior) layers of the device—corresponds to a greater Young's modulus (for example, where the second dielectric is silicon dioxide). By way of illustration and not limitation, a Young's modulus for the second dielectric is greater than 50 GPa, in various embodiments.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Jun into the device of Su to use non-conductive bonding structures of different compositions. The ordinary artisan would have been motivated to modify Su in the manner set forth above for the purpose of tuning the Young’s modulus of the layer to improve stress characteristics of the layers (para. 72 of Jun) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
With respect to claim 7, Su teaches all limitations of claim 1 upon which claim 7 depends. Su fails to teach:
further comprising an encapsulant that at least partially encapsulates the first semiconductor die and the second semiconductor die.
Jun teaches:
further comprising an encapsulant (encapsulation structure 140) that at least partially encapsulates the first semiconductor die (chiplet 370a) and the second semiconductor die (chiplet 370d).
Su discloses the claimed invention except for the encapsulation material. Jun discloses that it is known in the art to provide a bonded chips with a surrounding encapsulation material. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the device of Su with the encapsulation material of Jun, in order to protect the device from environmental damage. See MPEP 2144.
With respect to claim 17, Su teaches all limitations of claim 16 upon which claim 17 depends. Su fails to teach:
wherein the first respective bonding structures and the second respective bonding structures each comprises silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride, or a combination thereof.
Jun teaches:
wherein the first respective bonding structures and the second respective bonding structures each comprises silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride, or a combination thereof. (para. 72 “. Examples of such dielectrics include, but are not limited to, any of various carbon doped oxide materials (such as an organosilicate glass), a porous SiOx material,”).
Su teaches the claimed invention except for a different dielectric material is used for a non-conductive bonding structure. Jun teaches it is known to use silicon oxide as a non-conductive bonding structure. The ordinary artisan would be motivated to use the claimed materials as the dielectric bonding structure for the purpose of improving stress absorption in the device and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
With respect to claim 19, Su teaches all limitations of claim 16 upon which claim 19 depends. Su fails to teach:
further comprising an encapsulant that at least partially encapsulates the stack of multiple semiconductor dies.
Jun teaches:
further comprising an encapsulant (encapsulation structure 140) that at least partially encapsulates the stack of multiple semiconductor dies (chiplets 370a-370e).
Su discloses the claimed invention except for the encapsulation material. Jun discloses that it is known in the art to provide a bonded chips with a surrounding encapsulation material. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the device of Su with the encapsulation material of Jun, in order to protect the device from environmental damage. See MPEP 2144.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights