Prosecution Insights
Last updated: April 19, 2026
Application No. 17/882,441

MULTISTEP ETCH FOR DIRECT CHIP ATTACH (DCA) SUBSTRATES, AND ASSOCIATED SYSTEMS AND DEVICES

Non-Final OA §103
Filed
Aug 05, 2022
Examiner
NGUYEN, DUY T V
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Micron Technology, Inc.
OA Round
3 (Non-Final)
79%
Grant Probability
Favorable
3-4
OA Rounds
2y 10m
To Grant
96%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allow Rate
828 granted / 1052 resolved
+10.7% vs TC avg
Strong +17% interview lift
Without
With
+17.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
57 currently pending
Career history
1109
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
51.5%
+11.5% vs TC avg
§102
25.0%
-15.0% vs TC avg
§112
14.2%
-25.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1052 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 1. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/24/2025 has been entered. Status of the Application 2. Acknowledgement is made of the amendment received on 9/23/2025. Claims 1-20 are pending in this application. Claim Objections 3. The claims are objected because of the following reasons: Re claim 11, line 3: delete “has” and insert --have--. Re claim 12, line 3: after “the base” insert --;--. Re claim 16, line 5: after “base” insert --;--. Appropriate correction is required. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 4. Claims 1-3, 6, 7 and 11-19 are rejected under 35 U.S.C. 103 as being unpatentable over Shen et al. (US 8,158,888) in view of Kung et al. (US 2003/0218250). Re claim 1, Shen teaches, under BRI, Figs. 2A, 2C & 3A-H, abstract, cols. 3-6, a semiconductor device, comprising: -a substrate (310, 370, 380) including a first plurality of conductive contacts (324), a second plurality of conductive contacts (320, 322), and a mask material (370, 380) having a surface, wherein the mask material (370, 380) includes (a) a first recess (defined by 380) formed in the surface having a first depth and (b) a plurality of second recesses (defined by 370, 380) formed in the surface, each second recess of the plurality of second recesses having a second depth greater than the first depth (indicated), and wherein an exposed portion of each of the first plurality of conductive contacts (324) is exposed from the mask material (370, 380) in in one of the plurality of the second recesses (Figs. 2A & 3G); -a semiconductor die (chip 400) including a lower surface, wherein the lower surface is positioned in the first recess (indicated); and -a plurality of conductive features (410) electrically coupling individual ones of the die (400) to corresponding ones of the exposed portions of the first plurality of conductive contacts (324) (Fig. 3H). PNG media_image1.png 331 825 media_image1.png Greyscale PNG media_image2.png 327 835 media_image2.png Greyscale Shen does not explicitly teach wherein the exposed portion of each of the first plurality of conductive contacts protrudes from the mask material; and the semiconductor die having bond pads. Kung teaches, Fig. 14, [0036, 0040], wherein the exposed portion of each of the first plurality of conductive contacts (160) protrudes from the mask material (170); and the semiconductor die having bond pads (310). As taught by Kung, one of ordinary skill in the art would utilize & modify the above teaching into Shen to obtain the exposed portion of each of the first plurality of conductive contacts protrudes from the mask material, and the semiconductor die having bond pads and to couple individually ones of the bond pads to corresponding one of the exposed portion of the first plurality of conductive contacts as claimed, because bond pads are known as essential features of semiconductor die and also aids in achieving a high layout density of integrated circuit package substrate. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kung in combination with Shen due to above reason. Re claim 2, Shen teaches the substrate further includes a base (310), wherein the first plurality of conductive contacts (324) extend from the base (310), and wherein the mask material (370, 380) substantially covers the base (310) around the conductive contacts (324) (Fig. 3G). Re claim 3, Shen teaches the mask material (370, 380) is a solder mask (col. 5, 4th-5th pars.). Re claims 6 & 7, Shen/Kung does not explicitly teach the first recess has a depth of between 5-20 um; and the second recess has a depth of between 5-25 um. Shen does teach thickness of solder mask (370, 380) (e.g. 30 um & 20-12 um) (col. 5, 4th-5th pars.). It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ & modify the teaching as taught by Shen to obtain the first recess has a depth of between 5-20 um; and the second recess has a depth of between 5-25 um as claimed, because depths of recesses are known to affect device properties and would depend on the desired device density and the desired device characteristics. One of ordinary skill in the art would have been led to the recited depths through routine experimentation to achieve desired characteristics of the formed device. Re claim 11, Shen teaches, Figs. 2A & 3D, the second plurality of conductive contacts (320, 322) has upper surface coplanar with upper surface of the first plurality of conductive contacts (324), and wherein the mask material (370, 380) covers the upper surfaces of the second plurality of conductive contacts (320, 322). Re claim 12, Shen teaches, under BRI, Figs. 2A, 2C & 3A-H, abstract, cols. 3-6, a substrate, comprising: -a base (310) having an upper surface; -a first plurality of conductive contacts (324) extending from the upper surface of the base (310); -a second plurality of conductive contacts (320, 322) extending from the upper surface of the base (310) (Fig. 2A); and -a mask material (370, 380) over the upper surface of the base (310) and having a stepped upper surface including (a) an upper surface portion (e.g., upper surface of 380) extending to a first height above the upper surface of the base (310), (b) a mid surface portion (e.g., upper surface of 370) extending to a second height above the upper surface of the base (310) less than the first height, and (c) a plurality of lower surface portions (e.g., side portions of 370 right below upper surfaces of pads 324) extending to a third height above the upper surface of the base (310) less than the second height, wherein an exposed portion of each of the first plurality of conductive contacts (324) is exposed form the mask material (370, 380), and wherein upper surfaces of the exposed portion (of 324) are at fourth height above the upper surface of the base (310) that is less than the second height (Fig. 3G). PNG media_image3.png 329 845 media_image3.png Greyscale Shen does not explicitly teach the upper surface of the exposed portions are at the fourth height is greater than the third height. Kung teaches, Fig. 14, the upper surface of the exposed portions (of 160) are at the fourth height (at surface of 130) is greater than the third height (formed by surface 170 contacting with side of 130). PNG media_image4.png 311 483 media_image4.png Greyscale As taught by Kung, one of ordinary skill in the art would utilize & modify the above teaching to obtain upper surface of the exposed portions are at the fourth height greater than the third height as claimed, in achieving a high layout density of integrated circuit package substrate. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kung in combination with Shen due to above reason. Re claim 13, in combination cited above, Shen teaches, Fig. 3G, the second plurality of conductive contacts (320, 322) extending extend from the upper surface of the base (310) beneath the mid surface portion and to the fourth height such that the mask material (370, 380) covers an upper portion of each of the second plurality of conductive contacts (320, 322), and wherein upper surfaces of the second plurality of conductive contacts (320, 322) are coplanar with upper surfaces of the first plurality of conductive contacts (324). Re claim 14, Shen teaches, Fig. 3G, the mask material (370, 380) substantially covers upper surface of the base (310) around the first plurality of the conductive contacts (324). Re claim 15, Shen teaches the mask material (370, 380) is a solder mask (col. 5, 4-5th pars). Re claim 16, Shen teaches, under BRI, Figs. 2A, 2C & 3A-H, abstract, cols. 3-6, a semiconductor device, comprising: -a substrate including a base (310) having an upper surface; a first plurality of conductive contacts (324) extending from the upper surface of the base (310); a second plurality of conductive contacts (320, 322) extending from the upper surface of the base (310); and a mask material (370, 380) over the upper surface of the base (310) and having a stepped upper surface including (a) an upper surface portion (e.g., upper surface of 380) extending to a first height above the upper surface of the base (310), (b) a mid surface portion (e.g., upper surface of 370) extending to a second height above the upper surface of the base (310) less than the first height, and (c) a plurality of lower surface portions (e.g., side portions of 370 right below upper surfaces of pads 324) extending to a third height above the upper surface of the base (310) less than the second height, wherein an exposed portion of each of the first plurality of conductive contacts (324) is exposed from the mask material (370, 380), wherein upper surfaces of the exposed portions of the first plurality of conductive contacts (324) are at a fourth height above the upper surface of the base (310) that is less the second height; -a semiconductor die (400) including a lower surface, wherein the lower surface is positioned over the mid surface portion (upper surface of 370) and the plurality of lower surface portions (side portions of 370 right below upper surfaces of pads 324) and beneath the upper surface portion (upper surface of 380); and -a plurality of conductive features (410) electrically coupled to individually ones of the die (400) to corresponding ones of the exposed portions of the first plurality of conductive contact (324). PNG media_image3.png 329 845 media_image3.png Greyscale PNG media_image2.png 327 835 media_image2.png Greyscale Shen does not explicitly teach the upper surface of the exposed portions are at the fourth height is greater than the third height; and the semiconductor die having bond pads. Kung teaches, Fig. 14, [0036, 0040], the upper surface of the exposed portions (of 160) are at the fourth height (at surface of 130) is greater than the third height (formed by surface 170 contacting with side of 130); and the semiconductor die having bond pads (310). PNG media_image4.png 311 483 media_image4.png Greyscale As taught by Kung, one of ordinary skill in the art would utilize & modify the above teaching into Shen to obtain the upper surface of the exposed portions are at the fourth height is greater than the third height and the semiconductor die having bond pads and to couple individually ones of the bonds to corresponding one of the upper portion of the first plurality of conductive contacts as claimed, because bond pads are known as essential features of semiconductor die and also aids in achieving a high layout density of integrated circuit package substrate. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kung in combination with Shen due to above reason. Re claim 17, Shen teaches the mid surface portion (upper surface of 370) defines a recess, and wherein the semiconductor die (400) is positioned at least partially in the recess (in top view of Fig. 3H) (or consider 410 of 400 in recess defined by 370). Re claim 18, in combination cited above, Shen teaches, Fig. 3G, the second plurality of conductive contacts (320, 322) extending extend from the upper surface of the base (310) beneath the mid surface portion and to the fourth height such that the mask material (370, 380) covers an upper portion of each of the second plurality of conductive contacts (320, 322), and wherein upper surfaces of the second plurality of conductive contacts (320, 322) are coplanar with upper surfaces of the first plurality of conductive contacts (324). Re claim 19, Shen teaches, Fig. 3G, the mask material (370, 380) substantially covers the upper surface of the base (310) around the first plurality of conductive contacts (324). 5. Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Shen as modified by Kung as applied to claim 1 above, and further in view of Lesartre et al. (US 2020/0066676). The teachings of Shen/Kung have been discussed above. Re claims 4 & 5, Shen teaches, Fig. 3H, the plurality of conductive features (410) are pillars & the semiconductor die (400). Shen/Kung does not explicitly teach copper pillars and memory die. Lesartre teaches copper pillars and memory die (Fig. 2, [0023]). As taught by Lesartre, one of ordinary skill in the art would utilize & modify the above teaching to obtain copper pillars and memory die as claimed, because it aids in achieving a high density package substrate. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Lesartre in combination with Shen/Kung due to above reason. 6. Claims 8-10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Shen as modified by Kung as applied to claims 1 & 16 above, and further in view of Huang et al. (US 2022/0367334). The teachings of Shen/Kung have been discussed above. Re claim 8, Shen does not explicitly teach the plurality of conductive features have a height of between 10-80 um. Huang teaches the conductive features have a height of between 10-80 um (e.g., pillar height 25-55 um, Table 1). As taught by Huang, one of ordinary skill in the art would utilize & modify the above teaching to obtain the conductive features have a height of between 10-80 um as claimed, because height of conductive features is known to affect device properties and would depend on the desired device density and the desired device characteristics. One of ordinary skill in the art would have been led to the recited height through routine experimentation to achieve desired characteristics of the formed device. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Huang in combination with Shen due to above reason. Re claim 9, in combination cited above, Huang teaches, Fig. 1, an underfill material (UF) in the first and second recesses (defined between SM10B & SM10A). Re claim 10, in combination cited above, Shen teaches, Fig. 3H, a molded under material (300, U) in the first recess and encapsulating the semiconductor die (400); and Huang teaches, Fig. 1A, the molded underfill (UL) in the second recesses (defined by SM10A). Re claim 20, Shen/Kung does not explicitly teach the conductive features have a height of between 5-20 um. Huang teaches a height of between 3-7 microns (Table 1). As taught by Huang, one of ordinary skill in the art would utilize and modify the above teaching to obtain the conductive features having a height of between 5-20 um as claimed, because a height of conductive features is known to affect device properties and would depend on the desired device density and the desired device characteristics. One of ordinary skill in the art would have been led to the recited height through routine experimentation to achieve desired characteristics of the formed device. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Huang in combination with Shen/Kung due to above reason. Response to Arguments 7. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection. The claims amended with newly added features, interpretation and rejection under the cited prior arts also changed to meet the claimed invention. Conclusion 8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DUY T NGUYEN/Primary Examiner, Art Unit 2818 3/18/25
Read full office action

Prosecution Timeline

Aug 05, 2022
Application Filed
Apr 09, 2025
Non-Final Rejection — §103
Jul 14, 2025
Response Filed
Aug 01, 2025
Final Rejection — §103
Sep 23, 2025
Response after Non-Final Action
Oct 24, 2025
Request for Continued Examination
Nov 03, 2025
Response after Non-Final Action
Mar 22, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
79%
Grant Probability
96%
With Interview (+17.1%)
2y 10m
Median Time to Grant
High
PTA Risk
Based on 1052 resolved cases by this examiner. Grant probability derived from career allow rate.

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