DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment with respect to claims 1, and 15 filed on 12/11/2025 have been fully considered for examination based on their merits. The previously presented claims 2-14, and 16-20 have been considered.
Response to Arguments
Applicant’s arguments, see Remarks, pages 8-14, filed 12/11/2025, with respect to the rejection(s) of claim(s) 1-20 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of PARTHASARATHY.
Regarding Independent claims 1. The Applicant argues (see Remarks, page 11) that none of the prior art teaches the amended limitation of independent claim 1, now recites, “wherein the delta doping layer…is in physical direct contact…well region to limit a…well region.” The Applicant further argues that BERGER fails to disclose and amended feature of claim 1. The Examiner agrees that the amended limitation to claim 1 overcomes the rejection of record. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned. The BERGER reference is no more considered for rejecting any of the claim limitations in this Office Action. PARTHASARATHY teaches the high-power or high voltage transistor, wherein the heavily doped region (126/127) having first conductivity type is in physical direct contact with the lightly doped region (121) having second conductivity type. The motivation behind having PARTHASARATHY art with rest of the references to collectively disclose the different level doped regions to prevents the punch-through effects between the regions in a switching circuit configurations (PARTHASARATHY, [0032]).
Regarding Claims 2-20. The independent Claim(s) 15, and dependent claims 2-14, and 16-20 follow similar arguments as Claim 1, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 4-6, 10 and 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Keiji Wada et al, (hereinafter WADA), US 20140027784 A1, in view of Daniel M. Kinzer et al, (hereinafter KINZER), US 6194741 B1, further in view of Li-Ting Wang et al, (hereinafter WANG), US 20150255575 A1, further in view of Vijay Parthasarathy et al, (hereinafter PARTHASARATHY), US 20030080381 A1, and further in view of Ralf Siemieniec et al, (hereinafter SIEMIENIEC), US 20220246745 A1, and further in view of Qingchun Zhang et al, (hereinafter ZHANG), US 20090189228 A1.
Regarding Claim 1, WADA teaches in Figure 19, a silicon carbide semiconductor power transistor (Figures. 1-3, 201, a silicon carbide semiconductor device), comprising:
a substrate made of silicon carbide (SiC) (80, single crystal substrate);
a first drift layer (81a, lower drift layer) disposed on a plane of the substrate (80, single crystal substrate);
a second drift layer (81b, upper drift layer) formed on the first drift layer (81a, lower drift layer), wherein
a plurality of V-grooves (TR, a trench) is formed in the second drift layer (81b, upper drift layer);
a plurality of buried doped regions (73, relaxing region) disposed in the first drift layer (81a, lower drift layer) below the plurality of V-grooves (TR, a trench), and each of the buried doped regions (73, relaxing region) is a predetermined distance (Ltr, a distance between relaxing region 73, and trench, TR) from a bottom (BT, bottom of Trench) of each of the V-grooves (TR, a trench);
a plurality of gates (92, gate electrode) disposed in the plurality of V-grooves (TR, a trench) of the second drift layer (81b, upper drift layer);
a gate insulation layer (91, gate oxide film) disposed between the second drift layer (81b, upper drift layer) and each of the gates (92, gate electrode);
a plurality of source regions (94, source electrode) disposed in the well region (82, P body layer, has a P-type and with impurity concentrations, [0136]) between the V-grooves (TR, a trench), wherein the source regions (94, source electrode) and the buried doped regions (73, relaxing region) are electrically connected (84, p- contact region);
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Though WADA teaches the plurality of V-grooves are of honeycomb structure (Fig. 20), WADA does not explicitly disclose, a silicon carbide semiconductor power transistor, wherein a plurality of V-grooves is formed in the second drift layer, and the V-grooves are parallel to each other.
KINZER teaches a silicon carbide semiconductor power transistor (Fig. 1, 20, silicon carbide die), wherein a plurality of V-grooves (Figs. 3/4, 30, grooves/trenches) is formed in the second drift layer (Fig. 3, 22, drift region), and the V-grooves (Figs. 3/4, 30, grooves/trenches) are parallel to each other (Fig. 4, [Col. 3, Lines 1-5]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified WADA to incorporate the teachings of KINZER, such that a silicon carbide semiconductor power transistor, wherein a plurality of V-grooves is formed in the second drift layer, and the V-grooves are parallel to each other, so that to have much lower breakdown voltages due to the blocking performance of the SiC trench device and therefore the gate breakdown at the trench corner was improved (KINZER, [Col. 1, Lines 15-25]).
WADA as modified by KINZER does not explicitly disclose a silicon carbide semiconductor power transistor, comprising: a delta doping layer disposed in the second drift layer, and the V-grooves are across the delta doping layer; a well region disposed on the delta doping layer in the second drift layer,
WANG teaches a silicon carbide semiconductor power transistor (Figure 1, 100, semiconductor transistor device), comprising:
a delta doping layer (Figs. 1/4I, 110(a/b/c)/410) disposed in the second drift layer (Figs. 1/4I, 108/408, second semiconductor layer), and the V-grooves (Fig. 1/4I, 116/416, contact gate electrode/gate recess region) are across the delta doping layer (Figs. 1/4I, 110(a/b/c)/410);
a well region (Fig. 1/4, 134(a/b)/106/406, S/D regions/first semiconductor layer, [0011]) disposed on the delta doping layer (Figs. 1/4I, 110(a/b/c)/410) in the second drift layer (Figs. 1/4I, 108/408, second semiconductor layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified WADA as modified by KINZER to incorporate the teachings of WANG, such that a silicon carbide semiconductor power transistor, comprising: a delta doping layer disposed in the second drift layer, and the V-grooves are across the delta doping layer; a well region disposed on the delta doping layer in the second drift layer. The use of delta doping layer with very high doping concentrations which are formed during the formation of the source/drain region was to reduce to the interface resistance (WANG, [0010]).
WADA as modified by KINZER and WANG does not explicitly disclose, a silicon carbide semiconductor power transistor, comprising: wherein, the delta doping layer is in physical direct contact with an entire bottom of the well region to limit a junction profile variation of the well region, the delta doping laver has a first conductive type, and the well region has a second conductive type.
PARTHSARATHY teaches in Figure 6, a silicon carbide semiconductor power transistor (Fig. 6, 120, a high-power or high-voltage transistor), comprising: wherein, the delta doping layer (Fig. 6, 126/127, doped region (or buried layer or buried region) having higher doping concentration, [0025]) is in physical direct contact (annotated Figure 6) with an entire bottom of the well region (Fig. 6, 121, doped region having lower doping concentration, [0022], [0025]) to limit a junction profile variation ([0029]) of the well region (Fig. 6, 121, doped region having lower doping concentration, [0022], [0025]), the delta doping layer (Fig. 6, 126/127, doped region (or buried layer or buried region) having higher doping concentration, [0025]) has a first conductive type (Fig. 6, 126/127, doped region having second conductivity type, [0025]), and the well region (Fig. 6, 121, doped region having lower doping concentration, [0022], [0025]) has a second conductive type (Fig. 6, 121, doped region having first conductivity type, [0022]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified WADA as modified by KINZER and WANG to incorporate the teachings of PARTHASARATHY, such that a silicon carbide semiconductor power transistor, comprising: wherein, the delta doping layer is in physical direct contact with an entire bottom of the well region to limit a junction profile variation of the well region, the delta doping layer has a first conductive type, and the well region has a second conductive type. The different doping concentrations as mentioned above, for example 127 having higher doping concentration and 121 having lower doping concentration thus prevent punch-through between the regions in a switching circuit, 150 (PARTHASARATHY, Fig. 2, [0032]).
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WADA as modified by KINZER, WANG and PARTHASARATHY does not explicitly disclose, a silicon carbide semiconductor power transistor, comprising: a plurality of well pick-up regions disposed in the second drift layer and each of the well pick-up regions passes through the source regions and contacts with the well region; a plurality of conductive trenches disposed in the second drift layer, wherein each of the conductive trenches is made of conductive material, and in direct contact with each of the plurality of source electrodes, and each of the conductive trenches passes through the well pick-up regions and contacts with the well region; and a plurality of doping portions on sidewalls of the plurality of conductive trenches in the well region.
SIEMIENIEC teaches a silicon carbide semiconductor power transistor (Figure 2, 200, silicon carbide device), comprising:
a plurality of well pick-up regions (Fig. 2, 260, highly n-doped region) disposed in the second drift layer (Fig. 2, 230, lightly n-doped drift region) and each of the well pick-up regions (Fig. 2, 260, highly n-doped region) passes through the source regions (Fig. 2, 120, source region) and contacts with the well region (Fig. 2, 110, body region);
a plurality of conductive trenches (Fig. 2, 130, trench-gate) disposed in the second drift layer (Fig. 2, 230, drift region), wherein each of the conductive trenches (Fig. 2, 130, trench-gate) is made of conductive material (Fig. 2, 130, TiC gate electrode, [0037], [0049]), and in direct contact (annotated Figure 2) with each of the plurality of source electrodes regions (Fig. 2, 120, source region), and each of the conductive trenches (Fig. 2, 130, trench-gate) passes through the well pick-up regions (Fig. 2, 260, highly n-doped region) and contacts with the well region (Fig. 2, 110, body region); and
a plurality of doping portions (Fig. 2, 120/130, source region/body region, [0034], [0101]) on sidewalls (annotated Figure 2) of the plurality of conductive trenches (Fig. 2, 130, trench-gate) in the well region (Fig. 2, 110, body region).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have WADA as modified by KINZER, WANG and PARTHASARATHY to incorporate the teachings of SIEMIENIEC, such that a silicon carbide semiconductor power transistor, comprising: a plurality of well pick-up regions disposed in the second drift layer and each of the well pick-up regions passes through the source regions and contacts with the well region; a plurality of conductive trenches disposed in the second drift layer, wherein each of the conductive trenches is made of conductive material, and in direct contact with each of the plurality of source electrodes, and each of the conductive trenches passes through the well pick-up regions and contacts with the well region; and a plurality of doping portions on sidewalls of the plurality of conductive trenches in the well region. This configuration of silicon carbide, where by using titanium carbide as a material for the gate electrode, the electrical resistance of the gate electrode may be significantly reduced in comparison to a polysilicon gate electrode. Further, the homogeneity of the switching of transistor cells may be improved and/or switching losses may be reduced, for example, for devices with high switching frequencies (SIEMIENIEC, [0033]).
WADA as modified by KINZER, WANG, PARTHASARATHY and SIEMIENIEC does not explicitly disclose, a silicon carbide semiconductor power transistor, comprising: a plurality of source electrodes disposed on the second drift layer to be in direct contact with the well pick-up regions and the plurality of source regions.
ZHANG teaches in Figures 2/3, a silicon carbide semiconductor power transistor (Figs. 2/3, MOSFET(30)/IGBT(65), [0018-0019]), comprising: a plurality of source electrodes (Figs. 2/3, 38/78, source region/emitter region, [0012]), disposed on the second drift layer (Figs. 2/3, 54/89, N-drift region, [0012]) to be in direct contact with the well pick-up regions (Figs. 2/3, 33/34/83/84, the well region, [0012]) and the plurality of source regions (Figs. 2/3, 38/78, source region/emitter region, [0012]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have WADA as modified by KINZER and WANG, PARTHASARATHY and SIEMIENIEC to incorporate the teachings of ZHANG, such that a silicon carbide semiconductor power transistor, comprising: a plurality of source electrodes disposed on the second drift layer to be in direct contact with the well pick-up regions and the plurality of source regions, so that to develop a MOSFET/IGBT device, includes implanting at least one P-type well (33/34/83/84) in to N-type semiconductor body to depts that define at least one N-type source region (38/78) at least partially surrounded by the P-type well (33/34/83/84) to create a conductive path for carriers from the source region (38) (ZHANG, [0016], [0029]).
Regarding Claim 2, WADA as modified by KINZER, WANG, PARTHASARATHY, SIEMIENIEC and ZHANG teaches the silicon carbide semiconductor power transistor of claim 1.
WADA further teaches the silicon carbide semiconductor power transistor (Figures. 1-3, 201, a silicon carbide semiconductor device), wherein the plane of the substrate is a {0001} plane (Fig. 24, (000-1) plane, [0044], [0048], [0074], [0123-0126])), a {11-20} plane (Figs. 25/26, (11-20) plane, [0045], [0127]) or a {1100} plane (Figs. 24/27, (01-10) plane, [0047], [0129]).
Regarding Claim 4, WADA as modified by KINZER, WANG, PARTHASARATHY, SIEMIENIEC and ZHANG teaches the silicon carbide semiconductor power transistor of claim 1.
WADA further teaches the silicon carbide semiconductor power transistor (Figures. 1-3, 201, a silicon carbide semiconductor device), wherein a tilt angle (off angle, [0123]) between a sidewall (Fig. 23, sidewall surfaces, S1/S2, [0123]) and the bottom of each of the V-grooves (Fig. 23, SR, combined surface, [0123]) is 30° to 65° (Fig. 23. 62°, [0123]).
Regarding Claim 5, WADA as modified by KINZER, WANG, PARTHASARATHY, SIEMIENIEC and ZHANG teaches the silicon carbide semiconductor power transistor of claim 1.
WADA further teaches the silicon carbide semiconductor power transistor (Figures. 1-3, 201, a silicon carbide semiconductor device), wherein the substrate (80, single crystal substrate; the silicon carbide layer has a first main surface, the drift layer forms the first main surface and has a first conductivity type, [0009]), the first drift layer (81a, lower drift layer; the drift layer forms the first main surface has a first conductivity type, [0009]), the second drift layer (81b, upper drift layer; the drift layer forms the first main surface has a first conductivity type, [0009]), and the source regions (94, source electrode; the source region is provided on the body region to be spaced apart from the drift layer by the body region, forms the second main surface, and has the first conductivity type, [0009])) have the first conductive type (n-type or a first conductivity type [0009], [0070]), and the buried doped regions have the second conductive type (73, relaxing region; the silicon carbide layer includes a relaxing region provided within the drift layer and having the second conductivity typed).
WANG further teaches a silicon carbide semiconductor power transistor (Figure 1, 1, semiconductor device, [0025]), wherein the delta doping layer (Figs. 1/4I, 110(a/b/c)/410) has a first conductive type (Figs. 1/4I, 108/408, second semiconductor layer).
SIEMIENIEC further teaches a silicon carbide semiconductor power transistor (Figure 2, 200, silicon carbide device), wherein the well pick-up regions have a second conductive type (Fig. 2, 260, highly n-doped region).
Regarding Claim 6, WADA as modified by KINZER, WANG, PARTHASARATHY, SIEMIENIEC and ZHANG teaches the silicon carbide semiconductor power transistor of claim 1.
WANG further teaches the silicon carbide semiconductor power transistor (Figure 1, 1, semiconductor device, [0025]), wherein dopants in the delta doping layer are at least one selected from Si, Ge, and Sn (Claim 6, [0022]).
Regarding Claim 10, WADA as modified by KINZER, WANG, PARTHASARATHY, SIEMIENIEC and ZHANG teaches the silicon carbide semiconductor power transistor of claim 1.
WADA further teaches the silicon carbide semiconductor power transistor (Figures. 1-3, 201, a silicon carbide semiconductor device), wherein a doping concentration of the well region (82, P body layer, has a P-type and with impurity concentrations, [0136]) is ranged from 5E15/cm3 to 1E18/cm3 (an impurity concentration on a surface side of p body region 82P was from 1x1016 cm-3 to 5x1017 cm-3, an impurity concentration on a bottom side of p body region 82P was from 5x1017 cm-3 to 3x1018 cm-3, [0151]).
Regarding Claim 12, WADA as modified by KINZER, WANG, PARTHASARATHY, SIEMIENIEC and ZHANG teaches the silicon carbide semiconductor power transistor of claim 1.
WADA further teaches the silicon carbide semiconductor power transistor (Figures. 1-3, 201, a silicon carbide semiconductor device), wherein a width of each of the buried doped regions (73, relaxing region; a width of relaxing region, 73, was set to 2 µm, [0115]) is 1.5-2.0 times than a width of the bottom of each of the V-grooves (TR, a trench; a width of opening of trench, TR was set to 3 µm). (Based on the above dimensions from the prior art, the width of each of the buried doped regions is at least 1.83 times than a width of the bottom of each of the V-grooves; annotated Figure 19, the micrometers and with the scale of centimeters and back calculated the relations for confirmation).
Regarding Claim 13 WADA as modified by KINZER, WANG, PARTHASARATHY, SIEMIENIEC and ZHANG teaches the silicon carbide semiconductor power transistor of claim 1.
WADA further teaches the silicon carbide semiconductor power transistor (Figures. 1-3, 201, a silicon carbide semiconductor device), wherein a depth of an upper surface of the buried doped regions in the first drift layer is 0.2 µm to 1.5 µm (Ltr, a distance between the relaxing region and bottom surface of the trench is not greater than 4 µm, [0016]), and the predetermined distance is 0.3 µm to 1 µm (depth of trench + Ltr = 1.65 µm + (not greater than 4 µm, [0084], [0016]).
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Regarding Claim 14, WADA as modified by KINZER, WANG, PARTHASARATHY, SIEMIENIEC and ZHANG teaches the silicon carbide semiconductor power transistor of claim 1.
WADA further teaches the silicon carbide semiconductor power transistor (Figures. 1-3, 201, a silicon carbide semiconductor device), further comprising:
a plurality of gate electrodes (92) disposed on the plurality of gates (91, gate oxide film); and a drain electrode (98) disposed on a back of the substrate (80, single crystal substrate).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over WADA, in view of KINZER, further in view of WANG, further in view of PARTHASARATHY, further in view of SIEMIENIEC, further in view of ZHANG, and further in view of Yu Saitoh et al, (hereinafter SAITOH), US 20180114843 A1.
Regarding Claim 3, WADA as modified by KINZER, WANG, PARTHASARATHY, SIEMIENIEC and ZHANG teaches the silicon carbide semiconductor power transistor of claim 1.
WADA as modified by KINZER, WANG, PARTHASARATHY, SIEMIENIEC and ZHANG, does not explicitly disclose the silicon carbide semiconductor power transistor, wherein the plane of the substrate has an off-axis orientation equal to 5° or less.
SAITOH further teaches the silicon carbide semiconductor power transistor (Figure 1, 1, semiconductor device, [0025]) of claim 1, wherein the plane of the substrate has an off-axis orientation equal to 5° or less (Fig. 4, the off direction may be a direction with an azimuth angle {0001} plane relative to the <1-100> direction. Azimuth angle is 5°, for example. In other words, the off direction may be a direction within 5°, [0049]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have WADA as modified by KINZER, WANG, PARTHASARATHY, SIEMIENIEC and ZHANG, to incorporate the teachings of SAITOH, such that a silicon carbide semiconductor power transistor, wherein the plane of the substrate has an off-axis orientation equal to 5° or less, so that the silicon carbide semiconductor device capable of achieving reduced variation in threshold voltage (SAITOH, [0027]).
Claim(s) 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over WADA, in view of KINZER, further in view of WANG, further in view of PARTHASARATHY, further in view of SIEMIENIEC, further in view of ZHANG, and further in view of Daniel J. Lichtenwalner et al, (hereinafter LICHTENWALNER), US 20180166530 A1.
Regarding Claim 7, WADA as modified by KINZER, WANG, PARTHASARATHY, SIEMIENIEC and ZHANG teaches the silicon carbide semiconductor power transistor of claim 1.
WADA further teaches the silicon carbide semiconductor power transistor (Figures. 1-3, 201, a silicon carbide semiconductor device), further comprising the first drift layer (81a, lower drift layer) and the second drift layer (81b, upper drift layer), the source regions (94, source electrode) and the buried doped regions (73, relaxing region).
WADA as modified by KINZER, WANG, PARTHASARATHY, SIEMIENIEC and ZHANG does not teach the silicon carbide semiconductor power transistor, further comprising a strap of doped region disposed in the first drift layer and the second drift layer to connect the source regions and the buried doped regions.
LICHTENWALNER teaches in Figure 2B, a silicon carbide semiconductor power transistor (200, power MOSFET), further comprising a strap of doped region (272, more heavily doped portion) disposed in the first drift layer (220, n-type silicon carbide drift region), or and the second drift layer (230, n-type silicon carbide current spreading layer or CSL) to connect the source regions (Fig. 7F, 274, silicon carbide source regions) and the buried doped regions (240, a silicon carbide shielding region).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have WADA as modified by KINZER, WANG, PARTHASARATHY, SIEMIENIEC and ZHANG to incorporate the teachings of LICHTENWALNER, such that the silicon carbide semiconductor power transistor, further comprising a strap of doped region disposed in the first drift layer and the second drift layer to connect the source regions and the buried doped regions, so that the more heavily-doped portions, 272 of the p-wells 270 may provide a good electrical connection between the source contact 290 and the p-type shielding regions 240 (LICHTENWALNER, Figure 2B, [0068]).
Regarding Claim 8, WADA as modified by KINZER, WANG, PARTHASARATHY, SIEMIENIEC, ZHANG, and LICHTENWALNER teaches the silicon carbide semiconductor power transistor of claim 7.
LICHTENWALNER further teaches in Figures 2B/5, the silicon carbide semiconductor power transistor (200, power MOSFET), wherein the strap of doped region (272, more heavily doped portion) has an extension (270/470A, P-wells) direction perpendicular (the power MOSFET 400A has p-wells 470A that are formed in stripes that extend perpendicular to the gate trenches 280, [0084]) to an extension direction of the plurality of V-grooves (280, gate trenches).
Regarding Claim 9, WADA as modified by KINZER, WANG, PARTHASARATHY, SIEMIENIEC, ZHANG, and LICHTENWALNER teaches the silicon carbide semiconductor power transistor of claim 7.
LICHTENWALNER further teaches in Figures 2B/5, the silicon carbide semiconductor power transistor (200, power MOSFET), wherein gates (284, gate electrode) are symmetrically (annotated Figures 2B and 2C) and disposed on both sides of the strap of doped region (272/270, more heavily doped portion/P-wells).
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Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over WADA, in view of KINZER, further in view of WANG, further in view of PARTHASARATHY, further in view of SIEMIENIEC, further in view of ZHANG, and further in view of Katsunori Ueno, (hereinafter UENO), US 5895939 A.
Regarding Claim 11, WADA as modified by KINZER, WANG, PARTHASARATHY, SIEMIENIEC and ZHANG, teaches the silicon carbide semiconductor power transistor of claim 1.
WADA as modified by KINZER, WANG, PARTHASARATHY, SIEMIENIEC and ZHANG does not teach the silicon carbide semiconductor power transistor, wherein a doping concentration of the plurality of buried doped regions is ranged from 5E15/cm3 to 1E18/cm3.
UENO teaches in Figure 1, the silicon carbide semiconductor power transistor (SiC FET, [Col. 2, Line 65 – Col. 3, Line 5]), wherein a doping concentration of the plurality of buried doped regions is ranged from 5E15/cm3 to 1E18/cm3 (Fig. 1, p+ buried region, 20, with impurity concentration preferably from 1x1016 to 1x1019 cm-3 [Col. 7, Lines 30-35]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have WADA as modified by KINZER, WANG, PARTHASARATHY, SIEMIENIEC and ZHANG to incorporate the teachings of UENO, such that the silicon carbide semiconductor power transistor, wherein a doping concentration of the plurality of buried doped regions is ranged from 5E15/cm3 to 1E18/cm3, so that the beneficial effects of the p+ buried regions, 20, resulting in a MOSFET with high controllable current and high avalanche withstand capability (UENO, Fig. 3B, [Col. 60-67]).
Claim(s) 15-18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over WADA, in view of WANG, further in view of SIEMIENIEC, further in view LICHTENWALNER, further in view of PARTHASARATHY, and further in view of ZHANG.
Regarding Claim 15, WADA teaches in Figure 19, a method of manufacturing a silicon carbide semiconductor power transistor (Figures. 1-3, 201, a silicon carbide semiconductor device), comprising:
forming a first drift layer (81a, lower drift layer) on an upper surface of a silicon carbide (SiC) substrate (80, single crystal substrate);
forming a plurality of buried doped regions (73, relaxing region) in the first drift layer (81a, lower drift layer), and the buried doped regions (73, relaxing region) are parallel to each other (annotated Figure 19);
forming a second drift layer (81b, upper drift layer) on the first drift layer (81a, lower drift layer) to cover the plurality of buried doped regions (73, relaxing region);
forming a source region (94, source electrode) in the surface of the doped epitaxy layer (82, P body layer, has a P-type and with impurity concentrations, [0136]), wherein the source region (94, source electrode) and the buried doped regions (73, relaxing region) are electrically connected via the strap of doped region (84, p- contact region);
forming a plurality of well pick-up regions (84, p contact region) in the surface of the doped epitaxy layer (82, P body layer) between the buried doped regions (73, relaxing region) to pass through the source region (83, n region) and contact with the well region (182, P body layer);
forming a plurality of V-grooves (TR, a trench) is in the doped epitaxy layer (82, P body layer, has a P-type and with impurity concentrations, [0136]) and the second drift layer (81b, upper drift layer) over the plurality of buried doped regions (73, relaxing region), wherein the V-grooves (TR, a trench) is pass through the source region (94, source electrode), the well region (82, P body layer, has a P-type and with impurity concentrations, [0136]), and each of the buried doped regions (73, relaxing region) is a predetermined distance (Ltr, a distance between relaxing region 73, and trench, TR) from a bottom (BT, bottom of Trench) of each of the V-grooves (TR, a trench);
forming a gate insulation layer (91, gate oxide film) in the plurality of V-grooves (TR, a trench); and
forming a plurality of gates (92, gate electrode) on the gate insulation layer (91, gate oxide film).
WADA does not teach a method of manufacturing a silicon carbide semiconductor power transistor, comprising: forming a delta doping layer in a surface of the second drift layer; forming a doped epitaxy layer as a well region on the delta doping layer, wherein an entire bottom of the well region is in direct contact with the delta doping layer; forming a strap of doped region through the delta doping layer from a surface of the doped epitaxy layer to the plurality of buried doped regions; forming a plurality of V-grooves, wherein the V-grooves is pass through the delta doping layer.
WANG teaches a method of manufacturing a silicon carbide semiconductor power transistor (Figure 1, 100, semiconductor transistor device), comprising:
forming a delta doping layer (Figs. 1/4I, 110(a/b/c)/410) in a surface of the second drift layer (Figs. 1/4I, 108/408, second semiconductor layer);
forming a doped epitaxy layer as a well region (Fig. 1/4, 134(a/b)/106/406, S/D regions/first semiconductor layer, [0011]) on the delta doping layer (Figs. 1/4I, 110(a/b/c)/410), wherein an entire bottom of the well region Fig. 1/4, 134(a/b)/106/406, S/D regions/first semiconductor layer, [0011] to limit a junction profile variation of the well region;
forming a plurality of V-grooves (Fig. 1/4I, 116/416, contact gate electrode/gate recess region), wherein the V-grooves (Fig. 1/4I, 116/416, contact gate electrode/gate recess region) is pass through the delta doping layer (Figs. 1/4I, 110(a/b/c)/410).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified WADA to incorporate the teachings of WANG, such that a method of manufacturing a silicon carbide semiconductor power transistor, comprising: forming a delta doping layer in a surface of the second drift layer; forming a doped epitaxy layer as a well region on the delta doping layer, wherein an entire bottom of the well region is in direct contact with the delta doping layer; forming a strap of doped region through the delta doping layer from a surface of the doped epitaxy layer to the plurality of buried doped regions; forming a plurality of V-grooves, wherein the V-grooves is pass through the delta doping layer. The use of delta doping layer with very high doping concentrations which are formed during the formation of the source/drain region was to reduce to the interface resistance (WANG, [0010]).
WADA as modified by WANG does not teach a method of manufacturing a silicon carbide semiconductor power transistor, comprising: forming a plurality of well pick-up regions in the surface of the doped epitaxy layer between the buried doped regions to pass through the source region and contact with the well region; forming a plurality of conductive trenches in the second drift layer to pass through the plurality of well pick-up regions and contact with the well region, wherein each of the conductive trenches is made of conductive material; forming a plurality of doping portions on sidewalls of the plurality of conductive trenches in the well region; forming a plurality of source electrodes and a plurality of gate electrodes on the doped epitaxy layer, wherein each of the plurality of source electrodes is in direct contact with each of the plurality of conductive trenches.
SIEMIENIEC teaches, a method of manufacturing a silicon carbide semiconductor power transistor (Figure 2, 200, silicon carbide device), comprising:
forming a plurality of well pick-up regions (Fig. 2, 260, highly n-doped region) in the surface of the doped epitaxy layer (Fig. 2, 230, lightly n-doped drift region) between the buried doped regions to pass through the source region (Fig. 2, 120, source region) and contact with the well region (Fig. 2, 110, body region);
forming a plurality of conductive trenches (Fig. 2, 130, trench-gate) in the second drift layer (Fig. 2, 230, lightly n-doped drift region) to pass through the plurality of well pick-up regions (Fig. 2, 260, highly n-doped region) and contact with the well region (Fig. 2, 110, body region), wherein each of the conductive trenches (Fig. 2, 130, trench-gate) is made of conductive material (Fig. 2, 130, TiC gate electrode, [0037], [0049]),
forming a plurality of doping portions (Fig. 2, 120/130, source region/body region, [0034], [0101]) on sidewalls (annotated Figure 2) of the plurality of conductive trenches (Fig. 2, 130, trench-gate) in the well region (Fig. 2, 110, body region).
forming a plurality of source electrodes (Fig. 2, 120, source region) and a plurality of gate electrodes (Fig. 2, 130, trench-gate) on the doped epitaxial layer (Fig. 2, 230, epitaxial semiconductor layer, [0053]) wherein each of the plurality of source electrodes (Fig. 2, 120, source region) is in direct contact (annotated Figure 2) with each of the plurality of conductive trenches (Fig. 2, 130, trench-gate).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have WADA as modified by WANG to incorporate the teachings of SIEMIENIEC, such that a method of manufacturing a silicon carbide semiconductor power transistor, comprising: forming a plurality of well pick-up regions in the surface of the doped epitaxy layer between the buried doped regions to pass through the source region and contact with the well region; forming a plurality of conductive trenches in the second drift layer to pass through the plurality of well pick-up regions and contact with the well region; forming a plurality of doping portions on sidewalls of the plurality of conductive trenches in the well region, wherein each of the conductive trenches is made of conductive material; forming a plurality of source electrodes and a plurality of gate electrodes on the doped epitaxy layer, wherein each of the plurality of source electrodes is in direct contact with each of the plurality of conductive trenches. This configuration of silicon carbide, where by using titanium carbide as a material for the gate electrode, the electrical resistance of the gat electrode may be significantly reduced in comparison to a polysilicon gate electrode. Further, the homogeneity of the switching of transistor cells may be improved and/or switching losses may be reduced, for example, for devices with high switching frequencies (SIEMIENIEC, [0033]).
WADA as modified by WANG and SIEMIENIEC does not teach a method of manufacturing a silicon carbide semiconductor power transistor, comprising: forming a strap of doped region through the delta doping layer from a surface of the doped epitaxy layer to the plurality of buried doped regions.
LICHTENWALNER teaches in Figure 2B, a method of manufacturing a silicon carbide semiconductor power transistor (200, power MOSFET), comprising:
forming a strap of doped region (272, more heavily doped portion) through the delta doping layer (270, P-wells) from a surface of the doped epitaxy layer (260, silicon carbide layer formed by epitaxially growth, lightly doped) to the plurality of buried doped regions (240, carbide shielding region);
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have WADA as modified by WANG and SIEMIENIEC to incorporate the teachings of LICHTENWALNER, such that a method of manufacturing a silicon carbide semiconductor power transistor, comprising: forming a strap of doped region through the delta doping layer from a surface of the doped epitaxy layer to the plurality of buried doped regions, so that the more heavily-doped portions, 272 of the p-wells 270 may provide a good electrical connection between the source contact 290 and the p-type shielding regions 240 (LICHTENWALNER, Figure 2B, [0068]).
WADA as modified by WANG and SIEMIENIEC and LICHTENWALNER does not explicitly disclose a method of manufacturing a silicon carbide semiconductor power transistor, comprising: wherein the delta doping layer has a first conductive type; the well region has a second conductive type, and the delta doping layer is in direct contact with an entire bottom of the well region to limit a junction profile variation of the well region.
PARTHSARATHY teaches in Figure 6, a silicon carbide semiconductor power transistor (Fig. 6, 120, a high-power or high-voltage transistor), comprising: wherein, the delta doping layer (Fig. 6, 126/127, doped region (or buried layer or buried region) having higher doping concentration, [0025]) is in physical direct contact (annotated Figure 6) with an entire bottom of the well region (Fig. 6, 121, doped region having lower doping concentration, [0022], [0025]) to limit a junction profile variation ([0029]) of the well region (Fig. 6, 121, doped region having lower doping concentration, [0022], [0025]), the delta doping layer (Fig. 6, 126/127, doped region (or buried layer or buried region) having higher doping concentration, [0025]) has a first conductive type (Fig. 6, 126/127, doped region having second conductivity type, [0025]), and the well region (Fig. 6, 121, doped region having lower doping concentration, [0022], [0025]) has a second conductive type (Fig. 6, 121, doped region having first conductivity type, [0022]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified WADA as modified by WANG and SIEMIENIEC and LICHTENWALNER to incorporate the teachings of PARTHASARATHY, such that a silicon carbide semiconductor power transistor, comprising: wherein, the delta doping layer is in physical direct contact with an entire bottom of the well region to limit a junction profile variation of the well region, the delta doping layer has a first conductive type, and the well region has a second conductive type. The different doping concentrations as mentioned above, for example 127 having higher doping concentration and 121 having lower doping concentration thus prevent punch-through between the regions in a switching circuit, 150 (PARTHASARATHY, Fig. 2, [0032]).
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WADA as modified by WANG and SIEMIENIEC, LICHTENWALNER and PARTHASARATHY does not explicitly disclose, a method of manufacturing a silicon carbide semiconductor power transistor, comprising: forming a plurality of source electrodes and a plurality of gate electrodes on the doped epitaxy layer, wherein each of the plurality of source electrodes is in direct contact with each of the plurality of conductive trenches, each of the plurality of well pick-up regions, and each of the source region.
ZHANG teaches in Figures 2/3, a method of manufacturing a silicon carbide semiconductor power transistor (Figs. 2/3, MOSFET(30)/IGBT(65), [0018-0019]), comprising: forming a plurality of source electrodes (Figs. 2/3, 38/78, source region/emitter region, [0012]) and a plurality of gate electrodes (Figs. 2/3, 45/85, gate contact, [0015]) on the doped epitaxy layer (Figs. 2/3, 46/66, epitaxial growth of a P-type regrown channel layer [0032]), wherein each of the plurality of source electrodes (Figs. 2/3, 38/78, source region/emitter region, [0012]) is in direct contact with each of the plurality of well pick-up regions (Figs. 2/3, 33/34/83/84, the well region, [0012]), and each of the source region (Figs. 2/3, 38/78, source region/emitter region, [0012]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have WADA as modified by WANG and SIEMIENIEC, LICHTENWALNER and PARTHASARATHY to incorporate the teachings of ZHANG, such that a method of manufacturing a silicon carbide semiconductor power transistor, comprising: forming a plurality of source electrodes and a plurality of gate electrodes on the doped epitaxy layer, wherein each of the plurality of source electrodes is in direct contact with each of the plurality of conductive trenches, each of the plurality of well pick-up regions, and each of the source region, so that to develop a MOSFET/IGBT device, includes implanting at least one P-type well (33/34/83/84) in to N-type semiconductor body to depts that define at least one N-type source region (38/78) at least partially surrounded by the P-type well (33/34/83/84) to create a conductive path for carriers from the source region (38) (ZHANG, [0016], [0029]).
Regarding Claim 16, WADA as modified by WANG and SIEMIENIEC, LICHTENWALNER, PARTHASARATHY and ZHANG teaches the method of manufacturing a silicon carbide semiconductor power transistor (Figures. 1-3, 201, a silicon carbide semiconductor device) of claim 15.
WADA further teaches the method of manufacturing a silicon carbide semiconductor power transistor (Figures. 1-3, 201, a silicon carbide semiconductor device), wherein the gate electrodes (Fig. 14, 92) are disposed on the plurality of gates (Figs. 12/14, 91, gate oxide film).
Regarding Claim 17, WADA as modified by WANG and SIEMIENIEC, LICHTENWALNER, PARTHASARATHY and ZHANG teaches the method of manufacturing a silicon carbide semiconductor power transistor (Figures. 1-3, 201, a silicon carbide semiconductor device) of claim 16.
WADA further teaches the method of manufacturing a silicon carbide semiconductor power transistor (Figures. 1-3, 201, a silicon carbide semiconductor device), wherein after forming the source electrodes (94) and the gate electrodes (92), further comprising: forming a drain electrode (98) on a bottom surface of the SiC substrate (80, single crystal substrate).
Regarding Claim 18, WADA as modified by WANG and SIEMIENIEC, LICHTENWALNER, PARTHASARATHY and ZHANG teaches the method of manufacturing a silicon carbide semiconductor power transistor (Figures. 1-3, 201, a silicon carbide semiconductor device) of claim 15.
WADA further teaches the method of manufacturing a silicon carbide semiconductor power transistor (Figures. 1-3, 201, a silicon carbide semiconductor device), wherein the upper surface of the SiC substrate is a {0001} plane (Fig. 24, (000-1) plane, [0044], [0048], [0074], [0123-0126]), a {11-20} plane (Figs. 25/26, (11-20) plane, [0045], [0127]), or a {1100} plane (Figs. 24/27, (01-10) plane, [0047], [0129]).
Regarding Claim 20, WADA as modified by WANG and SIEMIENIEC, LICHTENWALNER, PARTHASARATHY and ZHANG teaches the method of manufacturing a silicon carbide semiconductor power transistor (Figures. 1-3, 201, a silicon carbide semiconductor device) of claim 15.
WADA further teaches the method of manufacturing a silicon carbide semiconductor power transistor (Figures. 1-3, 201, a silicon carbide semiconductor device), wherein the step of forming the plurality of V-grooves (Fig. 23, SR, combined surface, [0123]) comprises forming a tilt angle (off angle, [0123]) of 30° to 65° (Fig. 23. 62°, [0123]) between a sidewall (Fig. 23, sidewall surfaces, S1/S2, [0123]) and the bottom of each of the V-grooves (Fig. 23, SR, combined surface, [0123]).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over WADA, in view of WANG, further in view of SIEMIENIEC, further in view of LICHTENWALNER, further in view of PARTHASARATHY, further in view of ZHANG and further in view of SAITOH.
Regarding Claim 19, WADA as modified by WANG and SIEMIENIEC, LICHTENWALNER, PARTHASARATHY and ZHANG teaches the method of manufacturing a silicon carbide semiconductor power transistor (Figures. 1-3, 201, a silicon carbide semiconductor device) of claim 15.
WADA as modified by WANG and SIEMIENIEC, LICHTENWALNER, PARTHASARATHY and ZHANG, does not teach the method of manufacturing a silicon carbide semiconductor power transistor, wherein the upper surface of the SiC substrate has an off-axis orientation equal to 5° or less.
SAITOH further teaches the method of manufacturing a silicon carbide semiconductor power transistor (Figure 1, 1, semiconductor device, [0025]) of claim 15, wherein the upper surface of the SiC substrate has an off-axis orientation equal to 5° or less (Fig. 4, the off direction may be a direction with an azimuth angle {0001} plane relative to the <1-100> direction. Azimuth angle is 5°, for example. In other words, the off direction may be a direction within 5°, [0049]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have WADA as modified by WANG and SIEMIENIEC, LICHTENWALNER, PARTHASARATHY and ZHANG, to incorporate the teachings of SAITOH, such that a silicon carbide semiconductor power transistor, wherein the plane of the substrate has an off-axis orientation equal to 5° or less, so that the silicon carbide semiconductor device capable of achieving reduced variation in threshold voltage (SAITOH, [0027]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20030075719 A1 – Figure 2C
STATEMENT OF RELEVANCE – A delta doped layer (14) which may be either n-type or p-type silicon carbide. A delta doped channel is a fully open channel to near pinch-off voltage, by using a very thin, highly doped channel, [0013].
US 20060125001 A1 – Figure 2A
STATEMENT OF RELEVANCE – A highly doped region of p-type conductivity may extend about 0.4 micrometer into the buffer layer (12) of the substrate (10).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SESHA SAIRAMAN SRINIVASAN/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812