DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The present amendment, filed on or after 1/26/2026, has been entered. The Applicant has amended claims 1 and 5-7, canceled claims 2-4 and added claims 21-22 as new claims. Accordingly, claims 1 and 5-22 remain pending in the application.
Applicant’s amendments to the title and claims have overcome each and every objection previously set forth in the Non-Final Office Action mailed on 10/24/ 2025.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim21 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yun (US 2023/0086084 A1).
Regarding claim 21, Yun teaches a semiconductor structure (nanosheet transistor device 100 comprising nanosheet stacks 120-1, Figs, 1A-B. and D, [0008]-[0010] and [00190]) comprising:
a bottom nanosheet device (lower transistor T-L, Fig. 1B, [0023]) comprising a bottom stack of spaced apart bottom device semiconductor channel material nanosheets (lower nanosheets NS-L, Figs. 1B and D, [0023]), each bottom device semiconductor channel material nanosheet (each of the lower nanosheets NS-L, Figs. 1B and D, [0020]) of the bottom stack of spaced apart bottom device semiconductor channel material nanosheets (lower nanosheets NS-L, Fig. 1B, [0024]) has a first width (width of lowernanosheets NS-L in Y direction, Fig. 1B, [0031]);
a top nanosheet device (upper transistor T-U, Fig. 1B, [0023]) located above the bottom nanosheet device (lower transistor T-L, Fig. 1B) and comprising a top stack of spaced apart top device semiconductor channel material nanosheets (upper nanosheets NS-U, Figs. 1B and D, [0023]), wherein each top device semiconductor channel material nanosheet (each of the upper nanosheets NS-U, Figs. 1B, [0020]) of the top stack of spaced apart top device semiconductor channel material nanosheets (upper nanosheets NS-U, Figs. 1B), has a second width (width of upper nanosheets NS-U in Y direction, Fig. 1B, [0031]), wherein the first width (width of lower nanosheets NS-L in Y direction, Fig. 1B) is greater than the second width (width of upper nanosheets NS-U in Y direction, Fig. 1B) and the bottom stack of spaced apart bottom device semiconductor channel material nanosheets (lower nanosheets NS-L, Figs. 1B) and the top stack of spaced apart top device semiconductor channel material nanosheets (upper nanosheets NS-U, Figs. 1B) are arranged in a step configuration ([0031]: “The nanosheet stack 120-1 may thus represent a stepped nanosheet ("sNS") structure.”);
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a dielectric oxide structure (see the “dielectric oxide structure” labeled in Illustrative Fig. 1, which is an annotated version of Fig. 1D, [0037]; while the isolation region IL appears as a continuous single layer, the manufacturing of the device illustrated in Figs 2A-2N shows that the dielectric oxide structure and the bottom-top device separating inner spacer labeled in Illustrative Fig. 1 are different layers formed at different processing steps (the bottom-top device separating inner spacer is formed as insulating material 228 at a step shown in Fig. 2X, and the dielectric oxide structure is formed as isolation layer 228 ([0065]: “an oxide material”) at a step shown in Fig. 2Y); a similar approach was also taken for a similar device by Park (US 2023/0352528 A1, Figs 6-13)) located between the bottom nanosheet device (lower transistor T-L, Illustrative Fig. 1) and the top nanosheet device (upper transistor T-U, Illustrative Fig. 1), wherein the dielectric oxide structure (dielectric oxide structure, Illustrative Fig. 1) is spaced apart from a bottommost top device semiconductor channel nanosheet (bottommost top device semiconductor channel nanosheet, Illustrative Fig. 1) and a topmost bottom device semiconductor channel nanosheet (topmost bottom device semiconductor channel nanosheet, Illustrative Fig. 1)); and
a bottom-top device separating inner spacer (bottom-top device separating inner spacer, Illustrative Fig. 1) located between the top nanosheet device (upper transistor T-U, Illustrative Fig. 1) and the bottom nanosheet device (lower transistor T-L, Illustrative Fig. 1) and adjacent to the dielectric oxide structure (dielectric oxide structure, Illustrative Fig. 1), wherein the bottom-top device separating inner spacer (bottom-top device separating inner spacer, Illustrative Fig. 1) has a topmost surface (top surface 1, Illustrative Fig. 1) that is coplanar with a topmost surface (top surface 1, Illustrative Fig. 1) of the dielectric oxide structure (dielectric oxide structure, Illustrative Fig. 1).
Claim 22 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jo (US 2022/0336582 A1).
Regarding claim 22, Jo teaches a semiconductor structure (multi-stack semiconductor device, Figs. 1A-B [0027]) comprising:
a bottom nanosheet device (comprising the second lower nanosheet stack 10L from the right in Fig 1B, shown as bottom nanosheet device in Illustrative Fig. 2 which is an annotated version of Jo’s Fig. 1B, [0029]) comprising a bottom stack of spaced apart bottom device semiconductor channel material nanosheets (lower nanosheet layers LNL, Illustrative Fig. 2, [0036]), each bottom device semiconductor channel material nanosheet (each nanosheet of lower nanosheet layers LNL, Illustrative Fig. 2) of the bottom stack of spaced apart bottom device semiconductor channel material nanosheets (lower nanosheet layers LNL, Illustrative Fig. 2) has a first width (width W2, Illustrative Fig. 2, [0042]);
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a top nanosheet device (comprising the second upper nanosheet stack 10U from the right in Fig 1B, shown as top nanosheet device in Illustrative Fig. 2, [0029]) located above the bottom nanosheet device (bottom nanosheet device, Illustrative Fig. 2) and comprising a top stack of spaced apart top device semiconductor channel material nanosheets (upper nanosheet layers UNL, Illustrative Fig. 2, [0036]), wherein each top device semiconductor channel material nanosheet (each nanosheet of upper nanosheet layers UNL, Illustrative Fig. 2) of the top stack of spaced apart top device semiconductor channel material nanosheets (upper nanosheet layers UNL, Illustrative Fig. 2), has a second width (width W1, Illustrative Fig. 2, [0042]), wherein the first width (width W2, Illustrative Fig. 2) is greater than the second width (width W1, Illustrative Fig. 2) and the bottom stack of spaced apart bottom device semiconductor channel material nanosheets (lower nanosheet layers LNL, Illustrative Fig. 2) and the top stack of spaced apart top device semiconductor channel material nanosheets (upper nanosheet layers UNL, Illustrative Fig. 2) are arranged in a step configuration (Illustrative Fig. 2);
a dielectric oxide structure (isolation layer 102, Illustrative Fig. 2, [0033]: “SiO”) located between the bottom nanosheet device (bottom nanosheet device in Illustrative Fig. 2) and the top nanosheet device (top nanosheet device in Illustrative Fig. 2), wherein the dielectric oxide structure (isolation layer 102, Illustrative Fig. 2) is spaced apart from a bottommost top device semiconductor channel nanosheet (bottommost top device nanosheet, Illustrative Fig. 2) and a topmost bottom device semiconductor channel nanosheet (topmost bottom device nanosheet, Illustrative Fig. 2) and the dielectric oxide structure (isolation layer 102, Illustrative Fig. 2) has a first sidewall (first sidewall, Illustrative Fig. 2) and a second sidewall (second sidewall, Illustrative Fig. 2) that is opposite the first sidewall (first sidewall, Illustrative Fig. 2), wherein the first sidewall (first sidewall, Illustrative Fig. 2) of the dielectric oxide structure (isolation layer 102, Illustrative Fig. 2) does not extend beyond a first sidewall (third sidewall, Illustrative Fig. 2) of the top stack of spaced apart top device semiconductor channel material nanosheets (upper nanosheet layers UNL, Illustrative Fig. 2) and the second sidewall (second sidewall, Illustrative Fig. 2) of the dielectric oxide structure (isolation layer 102, Illustrative Fig. 2) is vertically aligned with a second sidewall (fourth sidewall, Illustrative Fig. 2) of the top stack of spaced apart top device semiconductor channel material nanosheets (upper nanosheet layers UNL, Illustrative Fig. 2), wherein the second sidewall (fourth sidewall, Illustrative Fig. 2) of the top stack of spaced apart top device semiconductor channel material nanosheets (upper nanosheet layers UNL, Illustrative Fig. 2) is opposite the first sidewall (third sidewall, Illustrative Fig. 2) of the top stack of spaced apart top device semiconductor channel material nanosheets (upper nanosheet layers UNL, Illustrative Fig. 2).
Allowable Subject Matter
Claims 1 and 5-20 are allowed, where claims 1 is the independent claim.
Regarding the amended claim 1, now also disclosing the limitation that “the dielectric oxide structure includes a second sidewall … that is vertically aligned with a second sidewall of the top stack of spaced apart top device semiconductor channel material nanosheets” by incorporating the limitations of previously objected claim 4 in claim 1, overcame the 35 U.S.C. 103 rejection on claim 1 based on Song (US 2023/0378264 A1) made in the non-final office action. Regarding the closest prior art, Song, which still remains to be the most relevant prior art, teaches a semiconductor structure (semiconductor device, Fig. 45, [0172]) comprising:
a bottom nanosheet device (see bottom nanosheet device as labeled in Illustrative Fig. 3 below, which is an annotated version of Fig. 45) comprising a bottom stack of spaced apart bottom device semiconductor channel material nanosheets (lower nanosheets BNW1, Illustrative Fig. 3, [0030]), each bottom device semiconductor channel material nanosheet (each of the lower nanosheets BNW1, Illustrative Fig. 3) of the bottom stack of spaced apart bottom device semiconductor channel material nanosheets (lower nanosheets BNW1, Illustrative Fig. 3) has a first width (width W1, Illustrative Fig. 3, [0151]);
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a top nanosheet device (top nanosheet device, Illustrative Fig. 3) located above the bottom nanosheet device (bottom nanosheet device, Illustrative Fig. 3) and comprising a top stack of spaced apart top device semiconductor channel material nanosheets (upper nanosheets UNW1, Illustrative Fig. 3, [0030]), wherein each top device semiconductor channel material nanosheet (each of the top nanosheets UNW101, Illustrative Fig. 3) of the top stack of spaced apart top device semiconductor channel material nanosheets (top nanosheet UNW101, Illustrative Fig. 3), has a second width (width W2, Illustrative Fig. 3, [0151]), wherein the first width (width W1, Illustrative Fig. 3) is greater than the second width (width W2, Illustrative Fig. 3) and the bottom stack of spaced apart bottom device semiconductor channel material nanosheets (lower nanosheets BNW1, Illustrative Fig. 3) and the top stack of spaced apart top device semiconductor channel material nanosheets (upper nanosheets UNW101, Illustrative Fig. 3) are arranged in a step configuration (Illustrative Fig. 3);
a dielectric oxide structure (vertical walls of the gate insulating layer 122 around the first separation layer 1011, labeled as dielectric oxide structure in Illustrative Fig. 3, [0074]: silicon oxide) located between the bottom nanosheet device (bottom nanosheet device, Illustrative Fig. 3) and the top nanosheet device (top nanosheet device, Illustrative Fig. 3), wherein the dielectric oxide structure (dielectric oxide structure, Illustrative Fig. 3) is spaced apart from a bottommost top device semiconductor channel nanosheet (bottommost nanosheet, Illustrative Fig. 3) and a topmost bottom device semiconductor channel nanosheet (bottommost nanosheet, Illustrative Fig. 3); and
a bottom-top device separating inner spacer (first separation layer 1011, Illustrative Fig. 3, [0050]: SiN) located between the top nanosheet device (top nanosheet device, Illustrative Fig. 3) and the bottom nanosheet device (bottom nanosheet device, Illustrative Fig. 3), wherein the bottom-top device separating inner spacer (first separation layer 1011, Illustrative Fig. 3) has a first sidewall (first sidewall of 1011, Illustrative Fig. 3) that is vertically aligned to a first sidewall (first sidewall of UNW101, Illustrative Fig. 3) of the top stack of spaced apart top device semiconductor channel material nanosheets (upper nanosheets UNW101, Illustrative Fig. 3), and a second sidewall (second sidewall of 1011, Illustrative Fig. 3) opposite the first sidewall (first sidewall of 1011, Illustrative Fig. 3), that is in direct physical contact with a first sidewall (first sidewall of 122, Illustrative Fig. 3) of the dielectric oxide structure (dielectric oxide structure, Illustrative Fig. 3), wherein the dielectric oxide structure (dielectric oxide structure in Illustrative Fig. 3) includes a second sidewall (second sidewall of 1011, Illustrative Fig. 3) that is opposite the first sidewall (first sidewall of 1011, Illustrative Fig. 3) of the dielectric oxide structure (dielectric oxide structure in Illustrative Fig. 3). that is vertically aligned with a second sidewall of the top stack of spaced apart top device semiconductor channel material nanosheets, wherein the second sidewall of the top stack of spaced apart top device semiconductor channel material nanosheets is opposite the first sidewall of the top stack of spaced apart top device semiconductor channel material nanosheets.
Song, however does not teach that the second sidewall that is opposite the first sidewall of the dielectric oxide structure is vertically aligned with a second sidewall of the top stack of spaced apart top device semiconductor channel material nanosheets. There has been no prior art identified that can, by itself or in combination with Song other prior art, to render the invention disclosed in claim 1 anticipated or obvious.
Accordingly, claim 1 is allowed, as the references of the Prior Art of record considered pertinent to the applicant’s disclosure and examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding the limitation that “the dielectric oxide structure includes a second sidewall … that is vertically aligned with a second sidewall of the top stack of spaced apart top device semiconductor channel material nanosheets” when this limitations is accompanied by the remaining limitations of claim 1.
Consequently, claims 5-20 are also allowed due to their dependency on allowed claim 1.
Response to Arguments
It has been acknowledged that the applicant amended claims 1, and 5-7, and canceled claims 2-4 per response dated on 1/26/2026. In addition, Applicant has added claims 21-22 as new claims. Applicant’s remarks have been fully considered. As detailed in the office action above, claims 1 and 5-20 are allowed, because the Applicant incorporated the previously objected claim 4, which included allowable subject matter, with independent claim 1, and further prior art search did not lead to a prior art that can render amended claim 1 anticipated or obvious.
However, new claims are rejected by new prior art. As detailed in the office action above, claim 21 is rejected under 35 U.S.C. 102 based on Yun (US 2023/0086084 A1), and claim 22 is rejected under 35 U.S.C. 102 based on Jo (US 20220336582 A1).
For the purpose of compact prosecution, the Examiner notes that incorporating more structural limitations related to the dielectric oxide structure and bottom-top device separating inner spacer might make independent claims 21 and 22 inventive and non-obvious.
The Examiner is available for an interview at Applicant’s convenience if the Applicant would like to discuss the application.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ILKER OZDEN whose telephone number is (703)756-5775. The examiner can normally be reached Monday - Friday 8:30am-5:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812