DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0341447 A1 to Siemieniec et al. (hereinafter “Siemieniec” – previously cited reference) in further view of US 2007/0194374 A1 to Bhalla et al. (hereinafter “Bhalla” – newly cited reference).
Regarding claim 1, Siemieniec discloses a transistor device (semiconductor component with FET structures; paragraph [0043]), comprising:
a SiC semiconductor body that includes a first semiconductor layer (SiC semiconductor body 100 having doped drift zone 131; Fig. 6; paragraph [0098]);
a plurality of trenches each extending from a first surface of the first semiconductor layer into the first semiconductor layer (gate electrodes 150 and trench contacts 316 disposed within trenches extending from top surface of drift zone 131 and into drift zone 131 as shown in Fig. 6; paragraphs [0102], [0107]); and
a plurality of transistor cells each coupled to a source node (transistor cells TC each coupled to a common source terminal S as shown in Fig. 6; paragraphs [0048], [0104]), wherein the first semiconductor layer includes a plurality of mesa regions each formed between two neighboring ones of the trenches (plurality of mesas 181, 182 disposed within drift zone 131 between neighboring trenches as shown in Fig. 6; paragraph [0103], [0108]), wherein, in each of the mesa regions, at least one of the plurality of transistor cells is at least partially integrated (transistor cells TC integrated into the mesa regions 181, 182 as shown in Fig. 6; paragraphs [0103]-[0104], [0107]), wherein a source region of each of the transistor cells is connected to the source node via a respective source contact that adjoins the source region (source areas 110 of each transistor cell TC is connected to the common source terminal S via trench contacts 316 which adjoin areas 110; Figs. 5A and 6; paragraphs [0047]-[0048], [0103], [0107]-[0111]), wherein each of the source contacts is arranged in a respective one of the trenches (each trench contact 316 is disposed within trench; Fig. 6; paragraph [0110]).
Siemieniec fails to disclose each of the source contacts is spaced apart from a bottom of the respective trench. However, Siemieniec does disclose that the load electrode 310 material which constitutes the trench contacts 316 may have sublayers 311, 312 disposed thereunder which provides suggestion that the trench contacts 316 could be disposed at a position other than at the bottom of the trench.
Bhalla discloses a source contact that adjoins the source region; each of the source contacts is arranged in a respective one of the trenches and is spaced apart from a bottom of the respective trench (source metal 190 disposed within upper part of trench above insulating material within trench and on either side of upper portion of source-connecting electrode 140 within trench, where metal 190 contacts source regions 170; Figs. 2C and 3L-3O; paragraphs [0020], [0023], [0026]-[0027]).
Siemieniec and Bhalla are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec to incorporate the teaching of Bhalla in order to potentially provide reduction of gate-drain capacitance and gate-drain charge, increased shielding of the gate electrode, lower on-resistance, and enhanced avalanche and short-circuit robustness.
Regarding claim 9, Siemieniec discloses a method, comprising:
forming a plurality of trenches in a first semiconductor layer of a SiC semiconductor body (SiC semiconductor body 100 having doped drift zone 131 with trenches disposed therein as shown in Fig. 6; paragraphs [0098], [0102], [0107]), each trench extending from a first surface of the first semiconductor layer into the first semiconductor layer (gate electrodes 150 and trench contacts 316 disposed within trenches extending from top surface of drift zone 131 and into drift zone 131 as shown in Fig. 6; paragraphs [0102], [0107]);
forming source contacts, wherein each source contact is arranged in a respective one of the trenches (each trench contact 316 is disposed within trench; Fig. 6; paragraph [0110]); and
forming a plurality of transistor cells such that a source region of each transistor cell is coupled to a source node via a respective source contact that adjoins the source region (source areas 110 of each transistor cell TC is connected to the common source terminal S via trench contacts 316 which adjoin areas 110; Figs. 5A and 6; paragraphs [0047]-[0048], [0103], [0107]-[0111]) and such that each transistor cell is at least partially integrated in a respective one of a plurality of mesa regions each formed between two neighboring ones of the trenches (transistor cells TC integrated into the plurality of mesas 181, 182 disposed within drift zone 131 between neighboring trenches as shown in Fig. 6; paragraph [0103]-[ 0104], [0107]-[0108]).
Siemieniec fails to disclose each of the source contacts is spaced apart from a bottom of the respective trench. However, Siemieniec does disclose that the load electrode 310 material which constitutes the trench contacts 316 may have sublayers 311, 312 disposed thereunder which provides suggestion that the trench contacts 316 could be disposed at a position other than at the bottom of the trench.
Bhalla discloses a source contact that adjoins the source region; each source contact is arranged in a respective one of the trenches and is spaced apart from a bottom of the respective trench (source metal 190 disposed within upper part of trench above insulating material within trench and on either side of upper portion of source-connecting electrode 140 within trench, where metal 190 contacts source regions 170; Figs. 2C and 3L-3O; paragraphs [0020], [0023], [0026]-[0027]).
Siemieniec and Bhalla are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec to incorporate the teaching of Bhalla in order to potentially provide reduction of gate-drain capacitance and gate-drain charge, increased shielding of the gate electrode, lower on-resistance, and enhanced avalanche and short-circuit robustness.
Claims 1-3, 5-9 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0341447 A1 to Siemieniec et al. (hereinafter “Siemieniec” – previously cited reference) in further view of US 2020/0083335 A1 to Leomant et al. (hereinafter “Leomant” – previously cited reference).
Regarding claim 1, Siemieniec discloses a transistor device (semiconductor component with FET structures; paragraph [0043]), comprising:
a SiC semiconductor body that includes a first semiconductor layer (SiC semiconductor body 100 having doped drift zone 131; Fig. 6; paragraph [0098]);
a plurality of trenches each extending from a first surface of the first semiconductor layer into the first semiconductor layer (gate electrodes 150 and trench contacts 316 disposed within trenches extending from top surface of drift zone 131 and into drift zone 131 as shown in Fig. 6; paragraphs [0102], [0107]); and
a plurality of transistor cells each coupled to a source node (transistor cells TC each coupled to a common source terminal S as shown in Fig. 6; paragraphs [0048], [0104]), wherein the first semiconductor layer includes a plurality of mesa regions each formed between two neighboring ones of the trenches (plurality of mesas 181, 182 disposed within drift zone 131 between neighboring trenches as shown in Fig. 6; paragraph [0103], [0108]), wherein, in each of the mesa regions, at least one of the plurality of transistor cells is at least partially integrated (transistor cells TC integrated into the mesa regions 181, 182 as shown in Fig. 6; paragraphs [0103]-[0104], [0107]), wherein a source region of each of the transistor cells is connected to the source node via a respective source contact that adjoins the source region (source areas 110 of each transistor cell TC is connected to the common source terminal S via trench contacts 316 which adjoin areas 110; Figs. 5A and 6; paragraphs [0047]-[0048], [0103], [0107]-[0111]), wherein each of the source contacts is arranged in a respective one of the trenches (each trench contact 316 is disposed within trench; Fig. 6; paragraph [0110]).
Siemieniec fails to disclose each of the source contacts is spaced apart from a bottom of the respective trench. However, Siemieniec does disclose that the load electrode 310 material which constitutes the trench contacts 316 may have sublayers 311, 312 disposed thereunder which provides suggestion that the trench contacts 316 could be disposed at a position other than at the bottom of the trench.
Leomant discloses each of the source contacts is arranged in a respective one of the trenches and is spaced apart from a bottom of the respective trench (silicide field plate 16 tied to source potential from n-type source region 34 is disposed within trench 15 and spaced apart from bottom thereof; Fig. 2; paragraphs [0017], [0034]-[0038]). Further, if the silicide or polysilicon field plate 16 of Fig. 2 were simply rearranged at the top of the trench 15, it would form a very good ohmic connection with the n-type source region 34 with an oxide and a cavity disposed within the trench 15 thereunder, which is a near identical arrangement to that which is disclosed in Figs. 6-8, for example, of Applicant’s Drawings.
Siemieniec and Leomant are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec to incorporate the teaching of Leomant in order to potentially provide reduction of gate-drain capacitance and gate-drain charge, increased shielding of the gate electrode, lower on-resistance, and enhanced avalanche and short-circuit robustness.
Regarding claim 2, Siemieniec in view Leomant discloses the transistor device of claim 1. Siemieniec fails to disclose wherein at least some of the plurality of trenches comprise a cavity between the respective trench bottom and the source contact.
However, Leomant discloses wherein at least some of the plurality of trenches comprise a cavity between the respective trench bottom and the source contact (trenches 13, 13’ comprising cavity 17 disposed between bottom of each trench and silicide field plate 16 tied to source potential from n-type source region 34 as shown in Fig. 2; paragraphs [0020], [0034]).
Siemieniec and Leomant are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec to incorporate the teaching of Leomant in order to potentially provide reduced parasitic capacitance, improved electric field distribution, enhanced thermal isolation, lower on-resistance, and mechanical stress relief.
Regarding claim 3, Siemieniec in view Leomant discloses the transistor device of claim 1. Siemieniec further discloses wherein the semiconductor body further comprises a second semiconductor layer, wherein at least a section of the second semiconductor layer forms a drain region of the transistor device, and wherein the first semiconductor layer is formed on top of the second semiconductor layer (highly doped base area 139 disposed under drift zone 131 and forming drain region with second load electrode 320 and drain terminal D as shown in Fig. 6; paragraphs [0050]-[0051]).
Regarding claim 5, Siemieniec in view Leomant discloses the transistor device of claim 1. Siemieniec further discloses wherein each transistor cell comprises: a body region adjoining the source region (body region 120 adjoining source area 110 as shown in Fig. 6; paragraph [0047]); a drift region (drift structure 130; Fig. 6; paragraph [0047]); and a gate electrode arranged adjacent to the body region and dielectrically insulated from the body region by a gate dielectric (gate electrode 155 arranged adjacent to body area 120 and insulated therefrom via gate dielectric layer 159 as shown in Fig. 6; paragraph [0052]).
Regarding claim 6, Siemieniec in view Leomant discloses the transistor device of claim 5. Siemieniec further discloses wherein each transistor cell further comprises: a compensation region arranged adjacent to the drift region and connected to the source contact (current distribution area 137 arranged adjacent drift structure 130 and coupled to trench contacts 316 as shown in Figs. 4B and 6; paragraphs [0085], [0107]).
Regarding claim 7, Siemieniec in view Leomant discloses the transistor device of claim 6. Siemieniec further discloses wherein each transistor cell further comprises: a JFET region of the same doping type as the body region and more highly doped than the body region (p-type shielding region 162 having higher doping concentration than body region 120; Fig. 6; paragraph [0053]), wherein the JFET region is spaced apart from the gate dielectric and adjoins at least one of the drift region and a current spreading region of the same doping type as the drift region (region 162 spaced apart from layer 159 and adjoining drift region 131; Fig. 6).
Regarding claim 8, Siemieniec in view Leomant discloses the transistor device of claim 7. Siemieniec further discloses wherein the JFET region adjoins the source contact, and wherein the body region is connected to the source contact through the JFET region (body region 120 connected to trench contact 316 through region 162; Fig. 6).
Regarding claim 9, Siemieniec discloses a method, comprising:
forming a plurality of trenches in a first semiconductor layer of a SiC semiconductor body (SiC semiconductor body 100 having doped drift zone 131 with trenches disposed therein as shown in Fig. 6; paragraphs [0098], [0102], [0107]), each trench extending from a first surface of the first semiconductor layer into the first semiconductor layer (gate electrodes 150 and trench contacts 316 disposed within trenches extending from top surface of drift zone 131 and into drift zone 131 as shown in Fig. 6; paragraphs [0102], [0107]);
forming source contacts, wherein each source contact is arranged in a respective one of the trenches (each trench contact 316 is disposed within trench; Fig. 6; paragraph [0110]); and
forming a plurality of transistor cells such that a source region of each transistor cell is coupled to a source node via a respective source contact that adjoins the source region (source areas 110 of each transistor cell TC is connected to the common source terminal S via trench contacts 316 which adjoin areas 110; Figs. 5A and 6; paragraphs [0047]-[0048], [0103], [0107]-[0111]) and such that each transistor cell is at least partially integrated in a respective one of a plurality of mesa regions each formed between two neighboring ones of the trenches (transistor cells TC integrated into the plurality of mesas 181, 182 disposed within drift zone 131 between neighboring trenches as shown in Fig. 6; paragraph [0103]-[ 0104], [0107]-[0108]).
Siemieniec fails to disclose each of the source contacts is spaced apart from a bottom of the respective trench. However, Siemieniec does disclose that the load electrode 310 material which constitutes the trench contacts 316 may have sublayers 311, 312 disposed thereunder which provides suggestion that the trench contacts 316 could be disposed at a position other than at the bottom of the trench.
Leomant discloses each of the source contacts is arranged in a respective one of the trenches and is spaced apart from a bottom of the respective trench (silicide field plate 16 tied to source potential from n-type source region 34 is disposed within trench 15 and spaced apart from bottom thereof; Fig. 2; paragraphs [0017], [0034]-[0038]). Further, if the silicide or polysilicon field plate 16 of Fig. 2 were simply rearranged at the top of the trench 15, it would form a very good ohmic connection with the n-type source region 34 with an oxide and a cavity disposed within the trench 15 thereunder, which is a near identical arrangement to that which is disclosed in Figs. 6-8, for example, of Applicant’s Drawings.
Siemieniec and Leomant are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec to incorporate the teaching of Leomant in order to potentially provide reduction of gate-drain capacitance and gate-drain charge, increased shielding of the gate electrode, lower on-resistance, and enhanced avalanche and short-circuit robustness.
Regarding claim 16, Siemieniec in view of Leomant discloses the transistor device of claim 2. Siemieniec fails to disclose a dielectric layer formed between the cavity and the respective source contact.
However, Leomant discloses a dielectric layer formed between the cavity and the respective source contact (first region of insulating material 18 formed between cavity 17 and silicide field plate 16 tied to source potential from n-type source region 34; Fig 2; paragraphs [0020], [0034]).
Siemieniec and Leomant are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec to incorporate the teaching of Leomant in order to potentially at least provide higher transistor cell density and vertical current flow which allows for reduced on-resistance and faster switching speeds in power applications.
Regarding claim 17, Siemieniec in view of Leomant discloses the transistor device of claim 16. Siemieniec fails to disclose a further dielectric layer formed between the cavity and a semiconductor material of the SiC semiconductor body.
However, Leomant discloses a further dielectric layer formed between the cavity and a semiconductor material of the SiC semiconductor body (second region of insulating material 18 formed between cavity 17 and body region 33; Fig. 2; paragraph [0034]).
Siemieniec and Leomant are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec to incorporate the teaching of Leomant in order to potentially at least provide higher transistor cell density and vertical current flow which allows for reduced on-resistance and faster switching speeds in power applications.
Regarding claim 18, Siemieniec in view of Leomant discloses the transistor device of claim 2. Siemieniec fails to disclose wherein a pressure in the cavity is less than 1% of atmospheric pressure.
However, Leomant discloses wherein a pressure in the cavity is less than 1% of atmospheric pressure (cavity 17 may have vacuum level of pressure; paragraphs [0024]-[0025]).
Siemieniec and Leomant are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec to incorporate the teaching of Leomant in order to potentially at least provide improved electron mobility and device speed and better high-temperature operation and higher power handling.
Regarding claim 19, Siemieniec in view of Leomant discloses the transistor device of claim 1. Siemieniec fails to disclose wherein at least some of the plurality of trenches are filled with a solid dielectric between the respective trench bottom and the source contact.
However, Leomant discloses wherein at least some of the plurality of trenches are filled with a solid dielectric between the respective trench bottom and the source contact (first region of insulating material 18 formed between base 14 of trench 13 and silicide field plate 16 tied to source potential from n-type source region 34; Fig 2; paragraphs [0020], [0034], [0037]).
Siemieniec and Leomant are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec to incorporate the teaching of Leomant in order to potentially at least provide higher transistor cell density and vertical current flow which allows for reduced on-resistance and faster switching speeds in power applications.
Regarding claim 20, Siemieniec in view of Leomant discloses the transistor device of claim 1. Siemieniec fails to disclose wherein at least some of the plurality of trenches are filled with a dielectric between the respective trench bottom and the source contact, and wherein a void is included in the dielectric.
However, Leomant discloses wherein at least some of the plurality of trenches are filled with a dielectric between the respective trench bottom and the source contact, and wherein a void is included in the dielectric (trenches 13 comprising cavity 17 within insulating material 18 disposed between base 14 of trench 13 and silicide field plate 16 tied to source potential from n-type source region 34 as shown in Fig. 2; paragraphs [0020], [0034], [0037]).
Siemieniec and Leomant are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec to incorporate the teaching of Leomant in order to potentially at least provide higher transistor cell density and vertical current flow which allows for reduced on-resistance and faster switching speeds in power applications.
Claims 4 and 10-15 are rejected under 35 U.S.C. 103 as being unpatentable over Siemieniec in further view of Leomant and US 2020/0194544 A1 to Aichinger et al. (hereinafter “Aichinger” – previously cited reference).
Regarding claim 4, Siemieniec in view of Leomant discloses the transistor device of claim 3. Siemieniec fails to disclose wherein the trenches extend through the first semiconductor layer into the second semiconductor layer.
However, Aichinger discloses wherein the trenches extend through the first semiconductor layer into the second semiconductor layer (gate trenches 104 extending through source region 114 and into body region 120 as shown in Fig. 2; paragraphs [0040], [0043]).
Siemieniec and Aichinger are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec to incorporate the teaching of Aichinger in order to potentially provide increased channel density, enhanced voltage blocking capability, improved charge compensation, reduced parasitic capacitance, and better thermal management.
Regarding claim 10, Siemieniec in view of Leomant discloses the method of claim 9. Siemieniec further discloses wherein forming each transistor cell comprises: forming the source region adjoining the source contact (source area 110 electrically connected to source terminal S; Fig. 6; paragraphs [0047]-[0048]); and forming a body region adjoining the source region (body area 120 adjoining source area 110 as shown in Fig. 6; paragraph [0047]), wherein forming the source region comprises forming a first implanted region by implanting dopant atoms via the first surface into the first semiconductor layer (source region 110 having n+ doping that is disposed at the top surface of the drift zone 131 as shown in Fig. 6; paragraph [0047]), wherein forming the body region comprises forming a second implanted region by implanting dopant atoms via the first surface into the first semiconductor layer (body region 120 having in part n+ doping that is disposed at the top surface of the drift zone 131 as shown in Fig. 6; paragraph [0047]).
Siemieniec fails to disclose wherein forming the source region and the body region further comprises an annealing process.
However, Aichinger discloses wherein forming the source region and the body region further comprises an annealing process (SiC substrate 102 comprising source and body regions 120 is annealed to activate all implanted dopants; Fig. 2; paragraph [0072]).
Siemieniec and Aichinger are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec to incorporate the teaching of Aichinger in order to potentially provide precise dopant activation, controlled diffusion and junction formation, and repair to lattice damage.
Regarding claim 11, Siemieniec in view of Leomant and Aichinger discloses the method of claim 10. Siemieniec further discloses wherein forming each transistor cell further comprises forming a JFET region, and wherein forming the JFET comprises forming a third implanted region by implanting dopant atoms into the first semiconductor layer (p-type shielding region 162 formed by doping drift zone 131; Fig. 6; paragraph [0053]).
Regarding claim 12, Siemieniec in view of Leomant and Aichinger discloses the method of claim 11. Siemieniec further discloses wherein implanting the dopant atoms to form the third implanted region comprises implanting the dopant atoms via a sidewall of a respective one of the trenches into the first semiconductor layer (region 162 formed by doping drift zone 131 along sidewall of trench containing trench contact 316; Fig. 6).
Regarding claim 13, Siemieniec in view of Leomant and Aichinger discloses the method of claim 12. Siemieniec further discloses wherein implanting the dopant atoms via the sidewall comprises partially covering the sidewall by a protection layer (implantation masks are applied to SiC body 100 including walls of trenches; paragraphs [0114]-[0117], [0120]-[0121]).
Regarding claim 14, Siemieniec in view of Leomant and Aichinger discloses the method of claim 10. Siemieniec further discloses wherein forming each transistor cell further comprises forming a compensation region, and wherein forming the compensation region comprises forming a fourth implanted region by implanting dopant atoms via a sidewall of a respective one of the trenches into the first semiconductor layer (current distribution area 137 having n-type doping and only accessible via sidewall of trench as shown in Fig. 4B).
Regarding claim 15, Siemieniec in view of Leomant and Aichinger discloses the method of claim 10. Siemieniec further discloses wherein each transistor cell further comprises a drift region, and wherein forming the drift region comprises forming a fifth implanted region by implanting dopant atoms via a sidewall of a respective one of the trenches into the first semiconductor layer (drift structure 130 having additional doped regions only accessible via sidewalls of trenches as shown in Fig. 4B).
Response to Arguments
Applicant's arguments filed February 10, 2026 have been fully considered. Applicant presented substantive amendments to claims 1 and 9 and corresponding arguments. Applicant first asserts that Siemieniec does not suggest that trench contacts 316 could be disposed at a position other than at the bottom of the trench, and cites paragraphs [0085]-[0086] which state that the sublayers 311, 312 may directly adjoin the first surface 101. Examiner asserts that surface 101 is altered upon formation of trenches within the SIC body 100 which suggests that the surface 101 extends into trenches after their formation. Therefore, Applicant’s citation supports Examiner’s assertion. Applicant’s assertion regarding Peake is moot in light of the new ground of rejection. Applicant next asserts that silicide field plate 16 of Leomant would not qualify as a source contact because plate 16 does not directly adjoin source region 34. However, in the context of MOSFETs, a source metal that is not in contact with the source region can still function as a source contact if it is tied to the potential from the source region, given the source region is typically connected to the lowest possible voltage in the circuit. In the case of Leomant, the silicide field plate 16 of Fig. 2 is tied to the potential from the source region 34 and so functions as a source contact. Further, if silicide field plate 16 were simply rearranged at the top of the trench 15, it would form a very good ohmic connection with the n-type source region 34 which provides additional support that plate 16 can function as a source contact in the MOSFET of Leomant. Applicant next asserts that Leomant could not be combined with Siemieniec because Leomant discloses the field plate 16 being disposed in a separate trench from gate trench 37 which would destroy the functionality of Siemieniec because the plate 16 of Leomant would not be able to contact source region 110 if it weren’t in the gate structure 150 of Siemieniec. However, Fig. 6 of Siemieniec directly contradicts Applicant’s assertion given that source regions 110 are disposed in direct contact with the upper region of source contact 316 trenches which means the plate 16 of Leomant could contact source regions 110 of Siemieniec if disposed therein. Finally, Applicant’s amended claims 1 and 9 and corresponding arguments regarding the narrow definition of a source contact are disclosed by Siemieniec, but necessitated a new ground of rejection using Bhalla to provide an optimal 35 USC 103 rejection of the amended claim language given that Peake did not disclose, teach, or suggest the source contact directly adjoining the source region, whereas Bhalla does disclose this and Leomant suggests this.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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