DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on December 31, 2025 has been entered. Claim(s) 22, 26, 35-38, 40-41, 58, 63-71, 73-74 has/have been canceled and claim(s) 75-84 has/have been added. Therefore, claim(s) 19, 25, 27-28, 30, 42-44, 61-62, 72, and 75-84 are pending in the application.
Claim Objections
Claim(s) 75, 77-78 and 81 is/are objected to because of the following informalities:
With respect to claim 75, “wherein one of the first and second transistors comprising” recited in line 2 of the claim should read “wherein one of the first and second transistors comprises”.
With respect to claim 77, “a isolation region” recited in line 3 of the claim should read “an isolation region”. Claim 78 which directly depends from claim 88 and which inherits issue of claim 77 is objected to for similar reason.
With respect to claim 78, “wherein the first interconnect contacting” recited in lines 1-2 of the claim should read “wherein the first interconnect contacts”.
With respect to claim 81, “a fourth transistor gates” recited in line 2 of the claim should read “a fourth transistor that gates”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 19, 25, 27-28, 42-44, 61-62, 72, 75-79, and 80-84 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claim 19, as currently amended the claim requires “a first interconnect contacting the source/drain region to a capacitor”. To begin with, the meaning of the phrase “contacting the source/drain region to a capacitor” is unclear. Namely, it is not clear how the first interconnect that contacts source/drain region is contacting it to a capacitor. Moreover, there is insufficient antecedent basis for the limitation “the source/drain region” recited in lines 5-6 of the claim. Additionally, it is not clear what is “a second interconnect” recited in line 12 of the claim, providing. While it appears that the second interconnect is electrically coupling the first gate to the second gate, it is not clear what such interconnect is providing. For purpose of compact prosecution, it will be assumed that “a first interconnect connects the first source/drain region to a capacitor and that the second interconnect is electrically coupling first gate of a first transistor to a second gate of a second transistor. Claims 42-44, 61-62, 75-79, which either directly or indirectly depend from claim 19 and which inherit issues of claim 19 are rejected for similar reasons.
With respect to claim 25, as currently amended the claim recites “a gate” twice (in line 11 and 16). It is unclear whether the second recited “a gate” was intended to relate back to “a gate” (line 11) or to set forth an additional gate. For purpose of compact prosecution, it will be assumed that the second recited gate was intended to set forth an additional gate. Claims 27-28 and 80-82, which either directly or indirectly depend from claim 25 and which inherit issues of claim 25 are rejected for similar reasons.
With respect to claim 62, the claim recites “a first source/drain region” twice (in line 3 of claim 1 and line 2 of claim 62). For purpose of compact prosecution, it will be assumed that “a first source/drain region” is referring back to “a first source/drain region” introduced in line 3 of claim 1.
With respect to claim 72, there is insufficient antecedent basis for the limitation “the two source/drain regions” recited in line 2 of the claim. For purpose of compact prosecution, “the two source/drain regions” will be treated as if it were “two source/drain regions”.
With respect to claim 77, there is insufficient antecedent basis for the limitation “the third interconnect” recited in lines 2-3 of the claim. Moreover, as currently presented the claim requires “the third interconnect contacting a side of the first source/drain region … against a isolation region”. It is unclear from the claim language to what element the term “side” is referring to. Namely, it is not clear if the third interconnect is contacting a side of first source/drain region that is formed in a substrate or is contacting first source/drain region that is on a side of an isolation region wherein the source/drain region is against the isolation region. For purpose of compact prosecution, “the third interconnect” will be treated as if it were “a third interconnect” and it will be assumed that the third interconnect contacts a source/drain region that is in a substrate against an isolation region.
With respect to claim 78, as currently amended the claim recites “wherein the first interconnect contacting an opposite side … against the isolation region”. It is unclear, however, what the first interconnect is contacting (an opposite side of what) and/or what is “against the isolation region” (the first source/drain or the first interconnect). For purpose of compact prosecution, it will be assumed that the first interconnect contacts a side of the isolation region that is opposite to the side that the first source/drain region is against.
With respect to claim 79, as currently presented the claim requires that each interconnect extends “between a storage device and the substrate” and that “a first interconnect contac[s] … to a capacitor”. It is unclear if the “capacitor” recited in line 6 of claim 19 and the “storage device” recited in line 2 of the claim are intended to refer to the same element or two different elements. Review of the specification, and in particular, paragraph [0019] of the specification as published suggests that the capacitor, to which first interconnect is connected, and the storage to which the interconnect extends are referring to the same element. For purpose of compact prosecution, it will be assumed that the capacitor and the storage device are referring to the same elements.
With respect to claim 82, as currently presented the claim requires “wherein at least one transistor comprises a horizontal transistor between another horizontal transistor and an interconnect”. It is unclear from the claim language if the recited, at least one transistor, was intended to refer back to the first, second and third transistors recited in claim 25 or a set forth a different, at least another transistor, and if the recited interconnect was intended to refer back to the first or second interconnects recited in claim 25 or set forth an additional interconnect. For purpose of compact prosecution, it will be assumed that at least one transistor is referring to at least one transistor from among the first, second and third transistors.
With respect to claim 83, there is insufficient antecedent basis for the limitation “each mux driver” recited in lines 2-3 of the claim. For purpose of compact prosecution, “each mux drive” will be treated as if it were “the mux driver”.
With respect to claim 84, there is insufficient antecedent basis for the limitation “the at least four transistors” recited in line 2 of the claim. For purpose of compact prosecution, “the at least four transistors” will be treated as if it were “at least four transistors”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 30 and 83-84 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2019/0206463, hereinafter “Kim”).
Regarding claim 30, Kim teaches in Figs. 3 and 6A-6C (Figs. 3 and 6A shown below) and related text an integrated assembly, comprising:
a first vertical transistor adjacent a second vertical transistor (i.e. transistors 302, Fig. 3 and ¶¶[0046]-[0047] and [0085]-[0091]), each transistor comprising a gate (306, Fig. 3 and ¶[0046]);
first and second interconnects (610, 605, 612 and 614, Fig. 6A and ¶¶[0083]-[0086]) extending from a substrate (Fig. 6A) and the first vertical transistor surrounding the first interconnect and the second vertical transistor surrounding the second interconnect (Fig. 6A);
a mux driver (326, Fig. 3 and ¶[0052]) electrically coupled to each gate (306, Fig. 3 and ¶[0046]) of the first and second vertical transistors
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Regarding claim 83 (30), Kim teaches wherein each mux driver is electrically coupled to at least four transistors (e.g. mux 326 coupled to at least four transistors 302, Fig. 3).
Regarding claim 84 (83), Kim teaches wherein each of the at least four transistors comprises a vertical transistor (Figs. 3, 6A and ¶¶[0046]-[0047] and [0085]-[0091]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 19, 42-44,61-62, and 75-78 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pillarisetty et al. (WO 2018/118096, hereinafter “Pillarisetty”, previously cited) in view of Leslie (US 2005/0164454, hereinafter “Leslie”, previously cited) and Furukawa et al. (US 2006/0169972 A1, hereinafter “Furukawa”, previously cited).
Regarding claim 19, Pillarisetty teaches in Fig. 8 (shown below) and related text an integrated assembly, comprising:
a first transistor (110, Fig. 8 and ¶[0063]) comprising a first gate (116, Fig. 8 and ¶[0065]) and a first source/drain region (118, Fig. 8 and ¶[0026]);
a first interconnect (156, 163, 102-104, Figs. 18-20 and ¶¶[0023]-[0026]) contacting the source/drain region (118, Fig. 8) to a charge-storage device (Fig. 8 and ¶[0041]); and
a second transistor (100, Fig. 8 and ¶[0022]) comprising a second gate (106, Fig. 8 and ¶[0022]) that is a different structure from the first gate (Fig. 8), the second gate gates a portion of a length of the first interconnect, the first interconnect electrically coupling the second gate to the first gate (i.e. through the first source/drain region).
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Pillarisetty, however, does not explicitly teach the charge-storage device is a capacitor comprising a lower conductive node configured as an upwardly-opening container and that a second interconnect provides a second electrically coupling of first gate to the second gate.
Leslie, in a similar field of endeavor, teaches in Fig. 25 and related text that in a memory device, similar to that disclosed by Pillarisetty, a charge-storage device can include a capacitive memory cell (i.e. capacitor) comprising a lower conductive node (122, Fig. 25 and ¶[0047]) configured as an upwardly-opening container (Fig. 25 and ¶[0047]) in order to implement data storage capabilities of the storage device (¶[0025]).
Thus, since the prior art teaches all of the claimed elements, using such element would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the capacitor comprising a lower conductive node configured as an upwardly-opening container, as disclosed by Leslie, as a storage element disclosed by Pillarisetty in order to implement data storage capabilities of the storage device.
Moreover, Furukawa, in a similar field of endeavor, teaches in Fig. 3 (shown below) and related text that a vertical transistor (26, Fig. 3 and ¶¶[0020] and [0051]) connected to a source/drain of a horizontal transistor (24, Fig. 3 and ¶¶[0020] and [0051]), similar to those disclosed by Pillarisetty, may include a second interconnect (e.g. 36, 40 extending from gate 28 of transistor 24, Fig. 3 and ¶[0051]) that electrically couples the first gate to the second (20, 36, Fig. 3 and ¶¶[0041]-[0045]) and the second gate in order to meet specific design requirements (e.g. form desired circuit configuration, ¶[0041]).
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Thus, since the prior art teaches all of the claimed elements, using such element would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to electrically couple the second gate to the first gate of Pillarisetty and Leslie via a connection directly contacting the first and the second gate, as disclosed by Furukawa, in order to meet specific design requirements.
Regarding claim 42 (19), the combined teaching of Pillarisetty, Leslie and Furukawa discloses wherein at least one of the first and second transistors is a horizontal transistor (Pillarisetyy, e.g. 100, Fig. 8).
Regarding claim 43 (19), the combined teaching of Pillarisetty, Leslie and Furukawa discloses wherein the source/drain region (118, Fig. 8) is located in a substrate (152, Fig. 8).
Regarding claim 44 (19), the combined teaching of Pillarisetty, Leslie and Furukawa discloses wherein:
the first transistor (Pillarisetty, 110, Fig. 8) comprises a first channel (Pillarisetty, 120, Fig. 8 and ¶[0065]); and
the second transistor (Pillarisetty, 100, Fig. 8) comprises a second channel (Pillarisetty, 103, Fig. 8) perpendicular to the first channel (Pillarisetty, 120, Fig. 8).
Regarding claim 61 (19), the combined teaching of Pillarisetty, Leslie and Furukawa discloses wherein, in the vertical cross section (Pillarisetty, Fig. 8), a bitline (163, Fig. 8 and ¶[0024])] extends horizontally below the second transistor (PIllarisetty, 100, Fig. 8) and above the first transistor (Pillarisetty, 110, Fig. 8).
Regarding claim 62 (19), the combined teaching of Pillarisetty, Leslie and Furukawa discloses wherein the source/drain region comprises a first source/drain/region in a substrate against one side of an isolation region (Pilarisetty, 122, Fig. 8), and further comprising a second source/drain region in the substrate against an opposite side of the isolation region (i.e. when integrated assembly disclosed by Pillarisetty includes a plurality of electronic device 150 of Fig. 8 in order to form a fully functional memory device (see annotated Fig. 8 below), the first and the second source/drain regions of the two adjacent electronic devices 150 will be on opposite sides of the isolation regions 122).
[AltContent: textbox ((Annotated Figure))]
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Regarding claim 75 (19), the combined teaching of Pillarisetty, Leslie and Furukawa discloses wherein one of the first and second transistors comprises a vertical transistor (Pillarisetty, 100, Fig. 8) on a substrate (Pillarisetty, 152, Fig. 8).
Regarding claim 76 (19), the combined teaching of Pillarisetty, Leslie and Furukawa discloses further comprising a third transistor comprising a third gate gating a portion of a third interconnect (i.e. Pillarisetty teaches that the disclosed integrated assembly includes plurality of adjacent transistors 110 that are isolated from each other by a shallow trench isolation (¶[0065]) and plurality of vertical transistors 100 as shown in Fig. 9A, which would include a third transistor comprising a third gate gating a portion of a third interconnect, annotated Fig. 8).
Regarding claim 77 (19), the combined teaching of Pillarisetty, Leslie and Furukawa discloses a third interconnect contacting a side of the first source/drain region in a substate against an isolation region (i.e. Pillarisetty teaches that the disclosed integrated assembly includes plurality of adjacent transistors 110 that are isolated from each other by a shallow trench isolation (¶[0065]) and plurality of vertical transistors 100 as shown in Fig. 9A, which would include a third interconnect that contacts a source/drain region that is in a substrate and is against an isolation region, annotated Fig. 8).
Regarding claim 78 (77), the combined teaching of Pillarisetty, Leslie and Furukawa discloses wherein the first interconnect contacts an opposite side to the side of the first source/drain region against the isolation region (Pillarisety, annotated Fig. 8).
Regarding claim 79 (19), the combined teaching of Pillarisetty, Leslie and Furukawa discloses wherein each interconnect (i.e. the first and second interconnects) is a single structure (i.e. the interconnects disclosed by Pillarisetty are single structures in a similar manner to that disclosed by the applicant where different portions of the interconnects comprise different materials) extending between a charge-storage device (i.e. capacitor) and a substrate (Pillarisetty, Fig. 8).
Response to Arguments
Applicant’s arguments with respect to claim(s) 19, 25 and 30 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANETA B CIESLEWICZ whose telephone number is 303-297-4232. The examiner can normally be reached M-F 8:30 AM - 2:30 PM.
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/A.B.C/
Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893