DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-3,9-10,12-17, 19-20,26 and 28-33 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11451217. Although the claims at issue are not identical, they are not patentably distinct from each other because the patent claims and application claims recite similar limitations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3,9-10,12-17, 19-20,26 and 28-33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Aida (JP 09139467) and/or Shindo (JP 03-277010) in view of Ito et al. (US 4417158), Nojiri (JP 2007208401 A).
As to claim 1, Aida’s figures and/or Shindo’s figure 3 shows a circuit comprising: a master latch (Aida’s M-LAT or Shido’s 11) configured to latch an input data signal and to output a data latch signal based on a master clock signal (K1 or Shindo’s F1A or /F1A which equivalent to Aida’s K2); a slave latch (Aida’s S-LAT or Shindo’s F2A or /F2A which equivalent to Aida’s K1) coupled to the master latch and configured to generate an output data signal based on a slave latch clock signal (K2) and the data latch signal. The figure fails to show the internal structure of the master and slave latches. However, Nojiri’s figure 13 shows a master and slave flip flop circuit (35 that comprises master latch 33 and slave latch 34). It would have been obvious to one having ordinary skill in the art to use Nojiri’s mater and slave flip flop (35) for Aida or Shindo’s master and slave flip flop for the purpose of providing more precise output signals. Therefore, the modified Aida or Shindo’s figure further shows that the master latch operated based on the master clock signal at a first clock input thereof (Nojiri’s CLK1) and an inverted version of the master clock at a second clock input thereof (Nojiri’s /CLK1); the slave latch operated based on the slave clock signal at a third clock input thereof (Nojiri’s CLK2), an inverted version of the slave clock signal at a fourth clock input thereof (Nojiri’s /CLK2); slave latch (Nojiri’s 34 includes a first transmission gate (in Nojiri’s transmission gate that receives CLK2, hereinafter “TG4”); a first inverter (Nojiri’s inverter that its output coupled to TG4); and a second inverter (Nojiri’s inverter that its input coupled to the output of TG3) connected in parallel to a series connection of the transmission gate and the first inverter, wherein the output of the first inverter is coupled to an input of the transmission gate; and the output data signal is taken from a junction of an output of the second inverter and an input of the first inverter to a location external to the circuit, and the data output signal is subsequently fed back from the external location into the circuit; and a skewed clock circuit (Aida’s figure 4 or Shindo’s 2B) coupled to the master latch and the slave latch. The figures fail to show the detail structure of the skewed clock circuit as claimed. However, Ito et al.’s figure 5 shows a skewed clock circuit having equivalent function with Aida or Shindo’s skewed clock circuit (Wada, US 7315196, figure 3 shows a skewed clock circuit having the same structure as Aida’s skewed clock circuit figure 4 which is similar to Shindo’s 2B, Wada’s figure 4 shows a timing diagram that is similar to Ito et al.’s timing diagram figure 6). Therefore, it would have been obvious to one having ordinary skill in the art to use Ito et al.’s skewed clock circuit for Aida or Shindo’s skewed clock circuit due to the doctrine of equivalent function, MPEP 2144.06, and for the purpose of saving space. As noted above, Aida uses K1 as its master clock. In contrast, Shindo uses K2 or /F1A as its master clock. Therefore, from selecting K1 or K2 as a master clock signal is seen as an obvious design preference to ensure optimum performance. Thus, selecting Ito’s F1 or F2 as the master clock signal for the modified circuit is seen as an obvious design preference to achieve optimum performance. Therefore, the modified Aida’s figures show that the skewed clock circuit comprises both of a NOR gate (Ito et al.’s 52) and a NAND gate (Ito et al.’s 51), the skewed clock circuit configured to receive a clock signal and generate a plurality of clock signals based on the clock signal, wherein the plurality of clock signals have overlapping high levels (as understood, not all of the plurality of clock signals have overlapping high levels, i.e. Applicant’s slave_CLKi and Master_CLKb do not have overlapping high levels. Ito’s figure 6 shows timing diagrams similar to Applicant’s timing diagrams figure 6), the plurality of clock signals have overlapping high levels and include the master clock signal at a first clock output thereof coupled to the first clock input of the master latch, an inverted version of the master clock signal at a second clock output thereof coupled to the second clock input of the master latch, the slave clock signal at a third clock output thereof coupled to the third clock input of the slave latch, and an inverted version of the slave clock signal at a fourth clock output thereof coupled to the fourth clock input of the slave latch based on the clock signal; and wherein: the master latch and the NAND gate (Ito’s 51) are configured to receive an inverted version of the master clock signal (/1 or 1. When F1 is used as the master clock); the slave latch and the NOR gate (Ito’s 52) are configured to receive an inverted version of the slave clock signal (2. /2 is equivalent to Aida’s K2 which is the slave clock signal); the master clock signal is directly taken from the output of the NOR gate to the mater latch (since Ito’s F1 and /F1 are the master clocks).
As to claim 2, the modified Aida’s figures show that each of master latch and the slave latch comprises the first transmission gate (Nojiri’s TG2 or TG4); the first inverter (that its output coupled to TG2 or TG4); the second inverter (that its input coupled to TG1 or TG3) connected in parallel to a series connection of the first transmission gate and the first inverter; wherein an output of the first inverter is coupled to an input of the first transmission gate; a second transmission gate (TG1 or TG3) connected to the second inverter and configured to receive the data latch signal from the master latch.
As to claim 3, the modified Aida or Shindo’s figure further shows that the NOR gate is configured to compare the clock signal with the inverted version of the slave clock signal and generate the master clock signal; the third inverter is coupled between the NOR gate and the master latch; the third inverter is configured to invert the master clock signal; the NAND gate is configured to compare the clock signal and the inverted version of the master clock signal and generate a slave clock signal; and the fourth inverter is coupled between the NAND gate and the slave latch; and the fourth inverter is configured to invert the slave clock signal.
Claims 9, 10, 12-17 recite similar limitations of claims above. Therefore, they are rejected for the same reasons.
As to further regarding claims 16, 19 and 20, the modified Aida’s or Shindo’s figure further shows that a setup/hold timing window for data latch operation of the data latch signal at a junction of an output of the master latch and an input of the slave latch reflects an amount of time that the data latch signal remains stable before a rising edge of the inverted slave clock signal and after a falling edge of the inverted slave clock signal (MPEP 2144.09).
As to claim 26, the modified Aida and/or Shindo’s figure shows that the skewed clock circuit further comprises: a third inverter (Ito’s 54) having an input connected to an output of the NOR gate and an output connected to an input of the NAND gate; and a fourth inverter (Ito’s 53) having an input connected to an output of the NAND gate and an output connected to an input of the NOR gate.
As to claim 28, the modified Aida and/or Shindo’s figure shows that the circuit is a flip-flop and the output data signal is configured to be read out of the flip-flop.
As to claim 29, the modified Aida and/or Shindo’s figures shows that the junction of the output of the second inverter and the input of the first inverter is free of connection to additional one or more logic gates.
As to claim 30, the modified Aida and/or Shindo’s figure shows that the slave latch consists of the first transmission gate, the first inverter, the second inverter and a second transmission gate coupled to the first transmission gate and the second inverter, and the output data signal serves as an external output of the slave latch.
As to claim 31, the modified Aida and/or Shindo’s figures shows that the circuit is a flip-flop, and the output data signal is configured to be read out from an output pin of the flip-flop.
Claims 32-33 recite similar limitations in claims above. Therefore, they are rejected for the same reasons.
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive.
Shindo’s figure 3 shows a two-phase clock supply method that is adopted for controlling master and slave latches. Shindo’s clock generator is similar to Aido’s clock generator. Therefore, it would have been obvious to one having ordinary skill in the art to use a two-phase clock supply method for controlling Aida’s master and slave latches when Nojiri’s flip flop is used for Aida and Shindo’s flip flop in order for providing more precise operation. Ito’s figure 5 shows an improvement of clock generator figure 3 which is similar to Aido and Shindo’s clock generators. It would have been obvious to one having ordinary skill in the art to use Ito’s clock generator circuit for Aida and/or Shindo’s clock generator circuit due to the doctrine of equivalent function and reducing error, see Ito’s col. 1, lines 39-44.
Conclusion
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/QUAN TRA/
Primary Examiner
Art Unit 2842