DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 7 and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by TSUJIMURA (US 20180240906).
Regarding claim 1, TSUJIMURA discloses a semiconductor device comprising a transistor (the FET transistor comprising gate 26, source 30, channel 32 and drain 34, see fig 1-3, para 44), the transistor comprising:
a gate electrode (gate electrode 26, see fig 1-3, para 33) arranged in gate trenches (the trenches in which 24 and 26 are formed, see fig 1-3, para 33) formed in a first portion of a silicon carbide substrate (the portion of the device shown in fig 3, see figure I below) and extending lengthwise in a first horizontal direction (the gate and trench extend lengthwise in the y-direction, see fig 1-3), the gate trenches patterning the first portion of the silicon carbide substrate into ridges (the semiconductor between the trenches comprising 33, 38, 32, 30 and 31, see fig 1-3, para 44);
a source region of a first conductivity type (n-type region 30, see fig 1-3, para 40), a channel region of a second conductivity type (p-type region 32 which will contain the channel, see fig 1-3, para 42), and a drift region of the first conductivity type (drift region 33, see fig 1-3, para 44), the source region, the channel region and a part of the drift region being arranged in the ridges (at least portions of 33, 32 and 30 are present in the ridges, see fig 1-3), a current path from the source region to the drift region extending in a depth direction of the silicon carbide substrate (the channel in 32 will run in the z-direction, see fig 1-3); and
a body contact portion of the second conductivity type (p-type region 36 and 38 that is in contact with source electrode 70 and body region 32, see fig 2, para 39 and 43) that is arranged in a second portion of the silicon carbide substrate (the portion of the device shown in fig 2, see figure I below), the second portion being adjacent to the first portion in the first horizontal direction (cross-sections II and III are adjacent in the y-direction, see fig 1), the second portion extending in a second horizontal direction intersecting the first horizontal direction (cross-section II extends in the x-direction, see fig 1 and 2), the body contact portion being electrically connected to the channel region (32 and 38 are directly connected, see fig 1-3), the body contact portion extending in the depth direction of the silicon carbide substrate to a portion below a bottom side of the gate trenches and being directly adjacent to the drift region (p-type region 36 and 38 extend in the z-direction to below the trench and in direct contact with 33, see fig 2-3 and figure I below),
wherein in the first portion of the silicon carbide substrate, the ridges are devoid of the body contact portion (in the region of the device in fig 3, 38 does not extend into the ridge between the gate electrodes, see fig 3, para 39) such that the body contact portion is not in direct contact with the source region in the first portion of the silicon carbide substrate (38 and 30 are not in direct contact in the region shown in fig 3).
Regarding claim 2, TSUJIMURA discloses the semiconductor device of claim 1, wherein the body contact portion is connected to a source terminal (upper electrode 70, see fig 2, para 35) via contact elements arranged in the second portion (36 and 38 are connected to 70 by means of portions of 38 in the 2nd region in figure 2, see figure I below).
Regarding claim 7, TSUJIMURA discloses the semiconductor device of claim 1, wherein the ridges extend through the second portion (the ridges extend into the region shown in fig 2, see fig 1-3).
Regarding claim 21, TSUJIMURA discloses a semiconductor device comprising a transistor (the FET transistor comprising gate 26, source 30, channel 32 and drain 34, see fig 1-3, para 44), the transistor comprising:
a gate electrode (gate electrode 26, see fig 1-3, para 33) arranged in gate trenches (the trenches in which 24 and 26 are formed, see fig 1-3, para 33) formed in a silicon carbide substrate (the portion of the device shown in fig 3, see figure I below) and running lengthwise in a first horizontal direction (the gate and trench extend lengthwise in the y-direction, see fig 1-3), the gate trenches patterning the silicon carbide substrate into ridges (the semiconductor between the trenches comprising 33, 38, 32, 30 and 31, see fig 1-3, para 44);
a source region of a first conductivity type (n-type region 30, see fig 1-3, para 40), a channel region of a second conductivity type (p-type region 32 which will contain the channel, see fig 1-3, para 42), a drift region of the first conductivity type (drift region 33, see fig 1-3,, and a drain region of the first conductivity type (fig 1-3, 34, para 45), the source region being arranged at a first main surface of the ridges (source 30 is formed at a top surface of the ridges, see fig 1-3, para 45), the drain region being arranged at a second main surface of the silicon carbide substrate (34 is on a bottom surface of the substrate, see fig 1-3, para 45); and
a body contact portion of the second conductivity type (p-type region 36 and 38 that is in contact with source electrode 70 and body region 32, see fig 2, para 39 and 43) that is arranged in a portion of the silicon carbide substrate (the portion of the device shown in fig 2, see figure I below) extending in a second horizontal direction intersecting the first horizontal direction (cross-section II extends in the x-direction, see fig 1 and 2), the body contact portion being electrically connected to the channel region (32 and 38 are directly connected, see fig 1-3), the body contact portion extending in a depth direction of the silicon carbide substrate to a portion below a bottom side of the gate trenches and being directly adjacent to the drift region (p-type region 36 and 38 extend in the z-direction to below the trench and in contact with 33, see fig 2-3 and figure I below),
wherein the gate trenches run lengthwise in the first horizontal direction through the portion of the silicon carbide substrate in which the body contact portion is arranged (the gate trenches run in the y-direction, see fig 1-3, para 33),
wherein the body contact portion directly adjoins at least some of the gate trenches in the portion of the silicon carbide substrate in which the body contact portion is arranged (36 and 38 are in direct contact with 24 in the trench, see fig 1-3).
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Figure I: TSUJIMURA figure 2-3 with added annotations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-4, 6, 11, 15 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over TSUJMURA (US 20180240806) in view of NAKANO (US 20130313576).
Regarding claim 3, TSUJIMURA discloses the semiconductor device of claim 2.
TSUJIMURA fails to explicitly disclose a device, wherein a lateral extension of each of the contact elements in the second horizontal direction is larger than a width of each of the ridges in the second horizontal direction.
NAKANO teaches a device, wherein a lateral extension of each of the contact elements in the second horizontal direction is larger than a width of each of the ridges in the second horizontal direction (the lateral extension of 147 and 148 is larger than that of a ridge between 112, see fig 15).
TSUJUMURA and NAKANO are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of TSUJIMURA with the element geometry of NAKANO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of TSUJIMURA with the element geometry of NAKANO in order to improve the breakdown voltage (see NAKANO para 19).
Regarding claim 4, TSUJIMURA discloses the semiconductor device of claim 2.
TSUJIMURA fails to explicitly disclose a device, wherein the ridges extend to an edge region of the second portion and are absent from a contact region in the second portion, the contact elements being arranged in the contact region.
NAKANO teaches a device, wherein the ridges extend to an edge region of the second portion and are absent from a contact region in the second portion (the ridges are formed around the edge of 114 but do not extend into the middle of 114, see fig 14-15, para 245), the contact elements being arranged in the contact region (147 and 148 are formed in the region 114, see fig 14-15).
TSUJUMURA and NAKANO are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of TSUJIMURA with the element geometry of NAKANO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of TSUJIMURA with the element geometry of NAKANO in order to improve the breakdown voltage (see NAKANO para 19).
Regarding claim 6, TSUJIMURA discloses the semiconductor device of claim 2.
TSUJIMURA fails to explicitly disclose a device, wherein a conductive material of one of the contact elements is different from a conductive material of a source contact electrically coupling the source region to the source terminal.
NAKANO teaches a device, wherein a conductive material of one of the contact elements is different from a conductive material of a source contact electrically coupling the source region to the source terminal (147 and 148 can be different materials, see para 274).
TSUJUMURA and NAKANO are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of TSUJIMURA with the material of NAKANO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of TSUJIMURA with the material of NAKANO in order to improve the breakdown voltage (see NAKANO para 19).
Regarding claim 11, TSUJIMURA discloses the semiconductor device of claim 1.
TSUJIMURA fails to explicitly disclose a device, further comprising shielding structures of the second conductivity type arranged below the gate trenches in the first portion of the silicon carbide substrate, a doping concentration of the shielding structures being smaller than the doping concentration of the body contact portion, the shielding structures being electrically connected to the body contact portion.
NAKANO teaches a device, further comprising shielding structures of the second conductivity type arranged below the gate trenches in the first portion of the silicon carbide substrate (fig 15, 140, para 261), a doping concentration of the shielding structures being smaller than the doping concentration of the body contact portion (140 can have a doping concentration of 1E17-1E19, and 138 can be doped to 1E21, see fig 15, para 257, and 261), the shielding structures being electrically connected to the body contact portion (140 is connected to 134 and 138 by 118, see fig 15).
TSUJUMURA and NAKANO are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of TSUJIMURA with the doping concentration of NAKANO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of TSUJIMURA with the doping concentration of NAKANO in order to improve the breakdown voltage (see NAKANO para 19).
Regarding claim 15, TSUJIMURA discloses the semiconductor device of claim 1.
TSUJIMURA fails to explicitly disclose a device, further comprising a body contact trench formed in the second portion of the silicon carbide substrate, the body contact trench extending in the second horizontal direction, wherein a sidewall of the body contact trench is doped with dopants of the second conductivity type.
NAKANO teaches a device, further comprising a body contact trench formed in the second portion of the silicon carbide substrate (the source trench 133, see fig 15, para 255), the body contact trench extending in the second horizontal direction (133 extends in the horizontal direction in G-G, see fig 15), wherein a sidewall of the body contact trench is doped with dopants of the second conductivity type (the sidewall of 133 includes p-region 134, see fig 15, para 256).
TSUJUMURA and NAKANO are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of TSUJIMURA with the doping concentration of NAKANO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of TSUJIMURA with the doping concentration of NAKANO in order to improve the breakdown voltage (see NAKANO para 19).
Regarding claim 23, TSUJIMURA discloses the semiconductor device of claim 21.
TSUJIMURA fails to explicitly disclose a device, wherein the source region is formed in a groove formed in the ridges, a doped portion of the second conductivity type being adjacent to sidewalls and a bottom side of the groove, the channel region and the body contact portion being arranged in the doped portions.
NAKANO teaches a device, wherein the source region is formed in a groove formed in the ridges (source region 117 is formed adjacent to the grooves 115 and 114 in the ridges, see fig 15), a doped portion of the second conductivity type being adjacent to sidewalls and a bottom side of the groove (p-type region 134 is formed on the bottom and sides of the groove 115, see fig 15, para 256), the channel region and the body contact portion being arranged in the doped portions (body contact 138 and the channel 118 are part of a contiguous p-doped region on the bottom and sides of 115, see fig 15).
TSUJUMURA and NAKANO are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of TSUJIMURA with the element geometry of NAKANO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of TSUJIMURA with the element geometry of NAKANO in order to improve the breakdown voltage (see NAKANO para 19).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over TSUJMURA (US 20180240806) in view of NAKANO (US 20130313576) and further in view of HIYOSHI (US 20160225855).
Regarding claim 5, TSUJIMURA and NAKANO disclose the semiconductor device of claim 4.
TSUJIMURA fails to explicitly disclose a device, wherein the ridges are interrupted in an interruption portion between adjacent second portions, further comprising a gate contact in the interruption portion.
HIYOSHI teaches a device, wherein the ridges are interrupted in an interruption portion between adjacent second portions (the portion of the device including the outermost gat trench 30a below 66, see fig 14, para 71), further comprising a gate contact (fig 14, 66, para 51) in the interruption portion.
TSUJIMURA and HIYOSHI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of TSUJIMURA with the ridge geometry of HIYOSHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of TSUJIMURA with the ridge geometry of HIYOSHI in order to increase the breakdown voltage (see HIYOSHI para 105).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over TSUJMURA (US 20180240806) in view of SIEMIENIEC (US 20180172910).
Regarding claim 8, TSUJIMURA discloses the semiconductor device of claim 1.
TSUJIMURA fails to explicitly disclose a device, wherein a width of each of the ridges is less than 100 nm.
SIEMIENIEC teaches a device, wherein a width of each of the ridges is less than 100 nm (the mesa width w3 can be less than 400 nm, see fig 1, para 63).
TSUJIMURA and SIEMIENIEC are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of TSUJIMURA with the element size of SIEMIENIEC because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of TSUJIMURA with the element size of SIEMIENIEC in order to provide short channels (see SIEMIENIEC para 67).
Additionally, parameters such as the size of various elements in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust the thickness, spacing or separation of layers in the device of NAKANO in order to improve short circuit resistance (see NAKANO para 66).
Claim(s) 9 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over TSUJMURA (US 20180240806) in view of CALAFIT (US 20140374824).
Regarding claim 9, TSUJIMURA discloses the semiconductor device of claim 1.
TSUJIMURA fails to explicitly disclose a device, wherein a width of each of the ridges is less than 4 x L, and wherein L denotes a length of a depletion zone at an interface between the channel region and an adjacent gate dielectric.
CALAFIT teaches a device, wherein a width of each of the ridges is less than 4 x L, and wherein L denotes a length of a depletion zone at an interface between the channel region and an adjacent gate dielectric (the width of the mesa M is chosen such that the depletion regions from the trenches 113A and B on either side of the mesa merge, meaning it must be less than 2 x L, see fig 1B, para 26).
TSUJIMURA and CALAFIT are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of TSUJIMURA with the element size of CALAFIT because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of TSUJIMURA with the element size of CALAFIT in order to allow suitable control over of the reverse blocking state leakage (see BALAFUT para 26.
Additionally, parameters such as the size of various elements in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust the thickness, spacing or separation of layers in the device of NAKANO in order to improve short circuit resistance (see NAKANO para 66).
Regarding claim 22, TSUJIMURA discloses the semiconductor device of claim 21.
TSUJIMURA fails to explicitly disclose a device, wherein the drift region is arranged adjacent to the first main surface of the ridges.
CALAFIT teaches a device, wherein the drift region is arranged adjacent to the first main surface of the ridges (the drift region 306 extends to the top surface of the ridges between 313, see fig 3B, para 32 and 31).
TSUJIMURA and CALAFIT are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of TSUJIMURA with the drift geometry of CALAFIT because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of TSUJIMURA with the drift geometry of CALAFIT in order to allow suitable control over of the reverse blocking state leakage (see BALAFUT para 26.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over TSUJMURA (US 20180240806) in view of BALIGA (US 6191447).
Regarding claim 10, TSUJIMURA discloses the semiconductor device of claim 1.
TSUJIMURA fails to explicitly disclose a device, wherein an aspect ratio of height to width of the ridges is larger than 7:1.
BALIGA teaches a device , wherein an aspect ratio of height to width of the ridges is larger than 7:1 (the width of the mesa can be 0.4 microns, and its height can be 3 microns, which yields an aspect ratio of 7.5, see fig 14, para 36).
TSUJIMURA and BALIGA are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of TSUJIMURA with the ridge sizes of BALIGA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of TSUJIMURA with the ridge sizes of BALIGA in order to increase the breakdown voltage (see BALIGA para 36).
Additionally, parameters such as the size of various elements in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust the thickness, spacing or separation of layers in the device of NAKANO in order to improve short circuit resistance (see NAKANO para 66).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over TSUJMURA (US 20180240806) in view of NAKANO ‘364 (US 20130306983).
Regarding claim 12, TSUJIMURA discloses the semiconductor device of claim 1.
TSUJIMURA fails to explicitly disclose a device, further comprising buried tuning structures of the first conductivity type arranged below the gate trenches in the second portion of the silicon carbide substrate, the buried tuning structures being electrically connected to the drift region.
NAKANO ‘364 teaches a device, further comprising buried tuning structures of the first conductivity type arranged below the gate trenches in the second portion of the silicon carbide substrate (n-type regions 74 below the gate trenches 15, see fig 7, para 141), the buried tuning structures being electrically connected to the drift region (74 are directly electrically connected to drift region 73, see fig 7).
TSUJIMURA and NAKANO ‘364 are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of TSUJIMURA with the tuning structure of NAKANO ‘364 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of TSUJIMURA with the tuning structure of NAKANO ‘364 in order to improve the breakdown voltage (see NAKANO '364 para 141).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over TSUJMURA (US 20180240806) in view of NAKAGAWA (US 20200243641).
Regarding claim 13, TSUJIMURA discloses the semiconductor device of claim 1.
TSUJIMURA fails to explicitly disclose a device, wherein a distance between a bottom portion of the body contact portion and a first main surface of the silicon carbide substrate is larger than 2 um.
NAKAGAWA teaches a device, wherein a distance between a bottom portion of the body contact portion and a first main surface of the silicon carbide substrate is larger than 2 um (since the depth of the source trench 11 can be 2.5 microns, see para 320, the distance from the bottom of body contact region 32, see fig 6, para 303, to the topmost surface of 31 will be at least 2 microns).
TSUJIMURA and NAKAGAWA are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of TSUJIMURA with the element sizes of NAKAGAWA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of TSUJIMURA with the element sizes of NAKAGAWA in order to improve withstand (see NAKAGAWA para 319).
Additionally, parameters such as the size of various elements in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust the thickness, spacing or separation of layers in the device of NAKANO in order to improve short circuit resistance (see NAKANO para 66).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over TSUJMURA (US 20180240806) in view of YAMAUCHI (US 20070072397).
Regarding claim 14, TSUJIMURA discloses the semiconductor device of claim 1.
TSUJIMURA fails to explicitly disclose a device, wherein the body contact portion extends to a drain region of the transistor.
YAMAUCHI teaches a device, wherein the body contact portion extends to a drain region of the transistor (the p-doped region 14 and 5 in contact with the body 7 extends to the drain 1, see fig 2, para 45 and 46).
TSUJIMURA and YAMAUCHI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of TSUJIMURA with the body contact shape of YAMAUCHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of TSUJIMURA with the body contact shape of YAMAUCHI in order to construct a super junction structure (see YAMAUCHI para 45).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over TSUJMURA (US 20180240806) in view of NUMABE (US 20160351702).
Regarding claim 16, TSUJIMURA discloses the semiconductor device of claim 1.
TSUJIMURA fails to explicitly disclose a device, wherein the gate electrode comprises a first sublayer of a first conductive material in a lower portion of the gate trenches and a second sublayer of a second conductive material formed over the first sublayer, the second conductive material having a smaller resistivity than the first conductive material.
NUMABE teaches a device, wherein the gate electrode comprises a first sublayer of a first conductive material in a lower portion of the gate trenches (polysilicon GE1, see fig 36, para 172) and a second sublayer of a second conductive material (Al layer M forming M1C, see fig 37, para 188) formed over the first sublayer, the second conductive material having a smaller resistivity than the first conductive material.
TSUJIMURA and NUMABE are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of TSUJIMURA with the gate electrode structure of NUMABE because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of TSUJIMURA with the gate electrode structure of NUMABE in order to increase the transistor formation area (see NUMABE para 329).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811