DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification/Drawings
In view of Applicant’s amendments to the specification and drawing, the prior objections for new matter are withdrawn.
Drawings
In view of Applicant’s amendments, the prior drawing objections are withdrawn.
Claim Objections
In view of Applicant’s amendments, the prior objections are withdrawn.
Claims 15-20 are objected to because of the following informalities: “a second end a second end” should likely read --a second end--. Appropriate correction is required.
Claims 16-20 inherit this objection for minor informalities.
Claim Rejections - 35 USC § 112
In view of Applicant’s amendments, the prior 112(b) rejections are withdrawn.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-21 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1, 9, and 15 describe the semiconductor fins as “having the semiconductor composition of the bulk semiconductor throughout the fin”. Though the semiconductor fins were originally described as “composed of material of the bulk semiconductor region”, they were never described as having that composition throughout the fin. Therefore, reciting “…having the semiconductor composition of the bulk semiconductor throughout the fin” introduces new matter.
Claims 2-8, 10-14, and 16-21 inherit this rejection for new matter.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(Re Claims 1, 9, and 21) As the following limitation was not originally described, it is unclear what is required by reciting “having the semiconductor composition of the bulk semiconductor throughout the fin”. Does the semiconductor composition only need to be present in some form from one end of the fin to another; must the fin consist of the semiconductor composition; or may the fin need only to comprise the semiconductor composition in some continuous region?
During examination, “having the semiconductor composition of the bulk semiconductor throughout the fin” was read as “comprising the semiconductor composition of the bulk semiconductor”.
Claims 2-8, 10-14, and 16-21 inherit this rejection for indefiniteness.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 15, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Radosavljevic et al. (US 2007/0001219) of record.
(Re Claim 1) Radosavljevic teaches a fin field-effect transistor comprising: a bulk semiconductor region (302+304; “In other embodiments of the present invention, the substrate 302 can be a "bulk" semiconductor substrate”; Fig. 3G, ¶36) having a recessed region (the space between 318 and 319; Fig. 3H markup), the recessed region have a first end (the left end of the recessed region, where left to right is in a diagonal direction from the bottom left corner to the top right corner of Fig. 3H; see Fig. 3H markup) and a second end (the right end of the recessed region; Fig. 3H markup), the second end opposite the first end (Fig. 3H), the bulk semiconductor having a semiconductor composition (¶36);
a source region (from the topmost part of 318 down to half of its thickness; “If source and drain landing pads 318 and 319 are utilized, they may be doped at this time also”; ¶48) on and extending vertically from the bulk semiconductor region (“In an embodiment of the invention where a "bulk" substrate is used, semiconductor layer 304 is merely an upper region of the semiconductor substrate”; ¶36), the source region being a planar source region (Fig. 3H) having an end of the source region (the end closest to the recess region) aligned with the first end of the recess region, the source region doped relative to the bulk semiconductor region (¶48); a drain region (from the topmost part of 319 down to half of its thickness; “If source and drain landing pads 318 and 319 are utilized, they may be doped at this time also”; ¶48) on and extending vertically from the bulk semiconductor region (“In an embodiment of the invention where a "bulk" substrate is used, semiconductor layer 304 is merely an upper region of the semiconductor substrate”; ¶36), the drain region being a planar drain region (Fig. 3H) having an end of the drain region aligned with the second end of the recessed region, the drain region doped relative to the bulk semiconductor region (¶48); one or more semiconductor fins (each 305; Fig. 3H, ¶48) contained within the recessed region, each semiconductor fin of the one or more semiconductor fins having the semiconductor composition of the bulk semiconductor throughout the fin (each 305 is formed from layer 304; Fig. 3G and 3H, ¶45); each semiconductor fin of the one or more semiconductor fins structured such that each semiconductor fin has a first end contacting and ending at the end of the source region (Fig. 3H) aligned with the first end of the recessed region within the recessed region and second end contacting and ending at the end of drain region aligned with the second end of the recessed region within the recessed region (Fig. 3H), the second end of each semiconductor fin being opposite from the first end of each semiconductor fin (Fig. 3H), the source region and the drain region being continuous and uniform with respect to each semiconductor fin (Fig. 3H); and a gate (313; Fig. 3I) wrapped around the one or more semiconductor fins, the gate at least partially in the recessed region (Fig. 3I).
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(Re Claim 2) Radosavljevic teaches the fin field-effect transistor of claim 1, wherein the one or more semiconductor fins and the bulk semiconductor region are composed of silicon (e.g., silicon; Fig. 3G-3H, ¶45).
(Re Claim 3) Radosavljevic teaches a fin field-effect transistor of claim 1, wherein the gate is separated from each of the one or more semiconductor fins by a gate dielectric (312; Fig. 3I), the gate dielectric including a dielectric having a dielectric constant greater than 3.9 (hafnium oxide; ¶46; see also the instant’s description of high-k gate dielectrics in ¶37).
(Re Claim 4) Radosavljevic teaches a fin field-effect transistor of claim 3, wherein the bulk semiconductor region and the one or more semiconductor fins include silicon (¶¶37, 45), the gate includes a metal structure, and the gate dielectric includes hafnium oxide (hafnium oxide; ¶46).
(Re Claim 15) Radosavljevic teaches a method comprising: providing a bulk semiconductor region (302+304; “In other embodiments of the present invention, the substrate 302 can be a "bulk" semiconductor substrate”; Fig. 3G, ¶36) having a recessed region (the space between 318 and 319; Fig. 3H markup), the recessed region having a first end (the left end of the recessed region, where left to right is in a diagonal direction from the bottom left corner to the top right corner of Fig. 3H; see Fig. 3H markup) and a second end (the right end of the recessed region; Fig. 3H markup), the second end opposite the first end (Fig. 3H), the bulk semiconductor having a semiconductor composition (¶36);
forming a source region (from the topmost part of 318 down to half of its thickness; “If source and drain landing pads 318 and 319 are utilized, they may be doped at this time also”; ¶48) on and extending vertically from the bulk semiconductor region (“In an embodiment of the invention where a "bulk" substrate is used, semiconductor layer 304 is merely an upper region of the semiconductor substrate”; ¶36), the source region being a planar source region (Fig. 3H) having an end of the source region (the end closest to the recess region) aligned with the first end of the recessed region, the source region doped relative to the bulk semiconductor region (¶48);
forming a drain region (from the topmost part of 319 down to half of its thickness; “If source and drain landing pads 318 and 319 are utilized, they may be doped at this time also”; ¶48) on and extending vertically from the bulk semiconductor region (“In an embodiment of the invention where a "bulk" substrate is used, semiconductor layer 304 is merely an upper region of the semiconductor substrate”; ¶36), the drain region being a planar drain region having an end of the drain region aligned with the second end of the recessed region, the drain region doped relative to the bulk semiconductor substrate (¶48); forming one or more semiconductor fins (each 305; Fig. 3H, ¶48) contained within the recessed region with each semiconductor fin of the one or more semiconductor fins having the semiconductor composition of the bulk semiconductor throughout the fin (each 305 is formed from layer 304; Fig. 3G and 3H, ¶45), including forming each semiconductor fin of the one or more semiconductor fins structured such that each semiconductor fin has a first end contacting and ending at the end of the source region aligned with the first end of the recessed region within the recessed region (Fig. 3H) and a second end contacting and ending at the end of the drain region aligned with the second end of the recessed region within the recessed region (Fig. 3H), the second end of each semiconductor fin being opposite from the first end of each semiconductor fin (Fig. 3H), the source region and the drain region being continuous and uniform with respect to each semiconductor fin (Fig. 3); forming a gate (313; Fig. 3I) wrapped around the one or more semiconductor fins such that the gate at least partially is located in the recessed region (Fig. 3I).
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(Re Claim 21) Radosavljevic teaches the fin field-effect transistor of claim 1, wherein the source region has a top surface (the topmost part of 318; Fig. 3H) and each semiconductor fin extends from a level in the recessed region below the source region and the drain region to a level at the top surface of the source region (Fig. 3H).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Radosavljevic et al. (US 2007/0001219) of record as applied to claim 4 above, and further in view of Kim (US 2013/0299914) of record.
(Re Claim 5) Radosavljevic teaches the fin field-effect transistor of claim 4, but has not been shown to teach the dielectric is located on a silicon oxide between the source region and the drain region.
Kim teaches forming a dielectric (131; Fig. 13) on a silicon oxide (125; Fig. 13-14) that is both on a semiconductor fin (F1; Fig. 14) and between a source (261 on the left; Fig. 15) region and a drain (261 on the right; Fig. 15) region.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form a silicon oxide taught by Kim, on the semiconductor fins and between the source region and a drain region of Radosavljevic, before forming the dielectric of Radosavljevic, to prevent a defect interface between the bulk semiconductor region and the dielectric (Kim: ¶37).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Radosavljevic et al. (US 2007/0001219) of record as applied to claim 1 above, and further in view of Maszara et al. (US 2011/0081764) and Wu et al. (US 8,633,516), both of record.
(Re Claim 6) Radosavljevic teaches the fin field-effect transistor of claim 1, wherein the fin field-effect transistor is a p-channel fin field-effect transistor (PMOS, i.e., a p-channel fin field-effect transistor; ¶¶37, 48).
Radosavljevic has not been shown to teach the source region and the drain region including epitaxial silicon germanium.
Radosavljevic does state that layer 304 may be silicon germanium (¶37).
Maszara teaches epitaxially growing silicon germanium (204; Fig. 2, ¶19) on a bulk semiconductor layer (202; Fig. 2).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the layer 304 of Radosavljevic, and so therefore the source and drain regions, from silicon germanium, as this is an alternative material for forming the fin field-effect transistor of Radosavljevic (Radosavljevic: ¶37).
A PHOSITA would also find it obvious to form the layer 304 using epitaxy, and so causing the source region and drain region to include epitaxial silicon germanium, as epitaxial growth allows for control over the ratio between silicon and germanium (Wu: col. 4 ln. 12-20).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Radosavljevic et al. (US 2007/0001219) of record as applied to claim 1 above, and further in view of Hareland et al. (US 2006/0172497) and Chung (US 2013/0148409) both of record.
(Re Claim 7) Radosavljevic teaches the fin field-effect transistor of claim 1, wherein the fin field-effect transistor is a p-channel fin field-effect transistor (PMOS, i.e., a p-channel fin field-effect transistor; ¶¶37, 48).
Radosavljevic has not been shown to explicitly teach the source region and the drain region including p+ implants.
Hareland teaches forming a source region (622; Fig. 8A) and a drain region (624; Fig. 8A) using ion implantation.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to implant the source and drain regions of Radosavljevic using ion implantation, as taught by Hareland, in order to form the PMOS tri-gate transistor (i.e., a p-channel fin field-effect transistor) embodiment of Radosavljevic (Radosavljevic: ¶48), as ion implantation provides good control over the implant concentration and location.
Chung teaches p+ implants can be used to create source or drains of PMOS devices (¶15).
A PHOSITA would find it obvious to utilize p+ implants when forming the source and drain region of modified Radosavljevic using the ion implantation of Hareland, as this is a known implant type that predictably forms a source or drain region for PMOS devices. See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
(Re Claim 8) Radosavljevic teaches the fin field-effect transistor of claim 1, wherein the fin field-effect transistor is a n-channel fin field-effect transistor (NMOS, i.e., an n-channel fin field-effect transistor; ¶¶37, 48).
Radosavljevic has not been shown to explicitly teach the source region and the drain region including n+ implants.
Hareland teaches forming a source region (622; Fig. 8A) and a drain region (624; Fig. 8A) using ion implantation.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to implant the source and drain regions of Radosavljevic using ion implantation, as taught by Hareland, in order to form the NMOS tri-gate transistor (i.e., an n-channel fin field-effect transistor) embodiment of Radosavljevic (Radosavljevic: ¶48), as ion implantation provides good control over the implant concentration and location.
Chung teaches n+ implants can be used to create source or drains of NMOS devices (¶15).
A PHOSITA would find it obvious to utilize n+ implants when forming the source and drain region of modified Radosavljevic using the ion implantation of Hareland, as this is a known implant type that predictably forms a source or drain region for NMOS devices. See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US 2011/0182098) of record and Radosavljevic et al. (US 2007/0001219) of record.
(Re Claim 9) Liaw teaches a memory device comprising: an array (101; Fig. 1) of memory cells (101a; ¶¶18-19); and circuits (105; Fig. 1, ¶25) for controlling operation of the array (¶25), the circuits including a fin field-effect transistor (¶3)
Liaw has not been shown to teach the fin field-effect transistor including:
a bulk semiconductor region having a recessed region, the recessed region having a first end and a second end, the second end opposite to the first end, the bulk semiconductor having a semiconductor composition;
a source region on and extending vertically from the bulk semiconductor region, the source region being a planar source region having an end of the source region aligned with the first end of the recessed region, the source region doped relative to the bulk semiconductor region;
a drain region on and extending vertically from the bulk semiconductor region, the drain region being a planar drain region having an end of the drain region aligned with the second end of the recessed region, the drain region doped relative to the bulk semiconductor region; one or more semiconductor fins contained within the recessed region, each semiconductor fin of the one or more semiconductor fins having the semiconductor composition of the bulk semiconductor throughout the fin, each semiconductor fin of the one or more semiconductor fins structured such that each semiconductor fin has a first end contacting and ending at the end of the source region aligned with the first end of the recessed region within the recessed region and second end contacting and ending at the end of the drain region aligned with the second end of the recessed region within the recessed region, the second end of each semiconductor fin being opposite from the first end of each semiconductor fin, the source region and the drain region being continuous and uniform with respect to each semiconductor fin; and a gate wrapped around the one or more semiconductor fins, the gate at least partially in the recessed region.
Radosavljevic teaches a fin field-effect transistor including: a bulk semiconductor region (302+304; “In other embodiments of the present invention, the substrate 302 can be a "bulk" semiconductor substrate”; Fig. 3G, ¶36) having a recessed region (the space between 318 and 319; Fig. 3H markup), the recessed region have a first end (the left end of the recessed region, where left to right is in a diagonal direction from the bottom left corner to the top right corner of Fig. 3H; see Fig. 3H markup) and a second end (the right end of the recessed region; Fig. 3H markup), the second end opposite the first end (Fig. 3H), the bulk semiconductor having a semiconductor composition (¶36);
a source region (from the topmost part of 318 down to half of its thickness; “If source and drain landing pads 318 and 319 are utilized, they may be doped at this time also”; ¶48) on and extending vertically from the bulk semiconductor region (“In an embodiment of the invention where a "bulk" substrate is used, semiconductor layer 304 is merely an upper region of the semiconductor substrate”; ¶36), the source region being a planar source region (Fig. 3H) having an end of the source region (the end closest to the recess region) aligned with the first end of the recess region, the source region doped relative to the bulk semiconductor region (¶48); a drain region (from the topmost part of 319 down to half of its thickness; “If source and drain landing pads 318 and 319 are utilized, they may be doped at this time also”; ¶48) on and extending vertically from the bulk semiconductor region (“In an embodiment of the invention where a "bulk" substrate is used, semiconductor layer 304 is merely an upper region of the semiconductor substrate”; ¶36), the drain region being a planar drain region (Fig. 3H) having an end of the drain region aligned with the second end of the recessed region, the drain region doped relative to the bulk semiconductor region (¶48); one or more semiconductor fins (each 305; Fig. 3H, ¶48) contained within the recessed region, each semiconductor fin of the one or more semiconductor fins having the semiconductor composition of the bulk semiconductor throughout the fin (each 305 is formed from layer 304; Fig. 3G and 3H, ¶45); each semiconductor fin of the one or more semiconductor fins structured such that each semiconductor fin has a first end contacting and ending at the end of the source region (Fig. 3H) aligned with the first end of the recessed region within the recessed region and second end contacting and ending at the end of drain region aligned with the second end of the recessed region within the recessed region (Fig. 3H), the second end of each semiconductor fin being opposite from the first end of each semiconductor fin (Fig. 3H), the source region and the drain region being continuous and uniform with respect to each semiconductor fin (Fig. 3H); and a gate (313; Fig. 3I) wrapped around the one or more semiconductor fins, the gate at least partially in the recessed region (Fig. 3I).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the fin field-effect transistors of Liaw using the configuration taught by Radosavljevic, as Radosavljevic’s transistors have improved switching speed compared to alternatives (Radosavljevic: ¶15).
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(Re Claim 10) Modified Liaw teaches the memory device of claim 9, wherein the circuits are located in a periphery region (region to the left of the memory array; Fig. 1) adjacent the memory array.
(Re Claim 11) Modified Liaw teaches the memory device of claim 9, wherein the circuits are located in a region under the memory array (from the view after turning Fig. 1 counterclockwise 90°; the orientation of a device does not impart patentability).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US 2011/0182098) of record and Radosavljevic et al. (US 2007/0001219) of record, as applied to claim 9 above, and further in view of Maszara et al. (US 2011/0081764) and Wu et al. (US 8,633,516), both of record.
(Re Claim 12) Modified Liaw teaches the memory device of claim 9, wherein the fin field-effect transistor is a p-channel fin field-effect transistor (PMOS, i.e., a p-channel fin field-effect transistor; ¶¶37, 48).
Modified Liaw has not been explicitly shown to teach the source region and the drain region including epitaxial silicon germanium.
Maszara teaches epitaxially growing silicon germanium (204; Fig. 2, ¶19) on a bulk semiconductor layer (202; Fig. 2).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the layer 304 of Radosavljevic, and so therefore the source and drain regions, from silicon germanium, as this is an alternative material for forming the fin field-effect transistor of Radosavljevic (Radosavljevic: ¶37).
A PHOSITA would also find it obvious to form the layer 304 using epitaxy, and so causing the source region and drain region to include epitaxial silicon germanium, as epitaxial growth allows for control over the ratio between silicon and germanium (Wu: col. 4 ln. 12-20).
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US 2011/0182098) and Radosavljevic et al. (US 2007/0001219) as applied to claim 9 above, and further in view of Hareland et al. (US 2006/0172497) and Chung (US 2013/0148409), all of record.
(Re Claim 13) Modified Liaw teaches the memory device of claim 9, wherein the fin field-effect transistor is a p- channel fin field-effect transistor (PMOS, i.e., a p-channel fin field-effect transistor; ¶¶37, 48).
Modified Liaw has not been explicitly shown to teach the source region and the drain region including p+ implants.
Hareland teaches forming a source region (622; Fig. 8A) and a drain region (624; Fig. 8A) using ion implantation.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to implant the source and drain regions of Radosavljevic using ion implantation, as taught by Hareland, in order to form the PMOS tri-gate transistor (i.e., a p-channel fin field-effect transistor) embodiment of Radosavljevic (Radosavljevic: ¶48), as ion implantation provides good control over the implant concentration and location.
Chung teaches p+ implants can be used to create source or drains of PMOS devices (¶15).
A PHOSITA would find it obvious to utilize p+ implants when forming the source and drain region of modified Radosavljevic using the ion implantation of Hareland, as this is a known implant type that predictably forms a source or drain region for PMOS devices. See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
(Re Claim 14) Modified Liaw teaches the memory device of claim 9, wherein the fin field-effect transistor is a n-channel fin field-effect transistor (NMOS, i.e., an n-channel fin field-effect transistor; ¶¶37, 48).
Modified Liaw has not been explicitly shown to teach the source region and the drain region including n+ implants.
Hareland teaches forming a source region (622; Fig. 8A) and a drain region (624; Fig. 8A) using ion implantation.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to implant the source and drain regions of Radosavljevic using ion implantation, as taught by Hareland, in order to form the NMOS tri-gate transistor (i.e., an n-channel fin field-effect transistor) embodiment of Radosavljevic (Radosavljevic: ¶48), as ion implantation provides good control over the implant concentration and location.
Chung teaches n+ implants can be used to create source or drains of NMOS devices (¶15).
A PHOSITA would find it obvious to utilize n+ implants when forming the source and drain region of modified Radosavljevic using the ion implantation of Hareland, as this is a known implant type that predictably forms a source or drain region for NMOS devices. See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Radosavljevic et al. (US 2007/0001219) of record as applied to claim 15 above, and further in view of Maszara et al. (US 2011/0081764) and Wu et al. (US 8,633,516), both of record.
(Re Claim 16) Radosavljevic teaches the method of claim 15, but has not been explicitly shown to teach forming the source region and the drain region includes epitaxially forming p+ silicon germanium.
Radosavljevic does state that layer 304 may be silicon germanium (¶37).
Maszara teaches epitaxially growing silicon germanium (204; Fig. 2, ¶19) on a bulk semiconductor layer (202; Fig. 2).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the layer 304 of Radosavljevic, and so therefore the source and drain regions, from silicon germanium, as this is an alternative material for forming the fin field-effect transistor of Radosavljevic (Radosavljevic: ¶37).
A PHOSITA would also find it obvious to form the layer 304 using epitaxy, and so causing the source region and drain region to include epitaxial silicon germanium, as epitaxial growth allows for control over the ratio between silicon and germanium (Wu: col. 4 ln. 12-20).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Radosavljevic et al. (US 2007/0001219) of record as applied to claim 15 above, and further in view of Hareland et al. (US 2006/0172497) and Chung (US 2013/0148409) both of record.
(Re Claim 17) Radosavljevic teaches the method of claim 15, but has not been explicitly shown to teach forming the source region and the drain region includes forming the source region and the drain region with p+ implants.
Hareland teaches forming a source region (622; Fig. 8A) and a drain region (624; Fig. 8A) using ion implantation.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to implant the source and drain regions of Radosavljevic using ion implantation, as taught by Hareland, in order to form the PMOS tri-gate transistor (i.e., a p-channel fin field-effect transistor) embodiment of Radosavljevic (Radosavljevic: ¶48), as ion implantation provides good control over the implant concentration and location.
Chung teaches p+ implants can be used to create source or drains of PMOS devices (¶15).
A PHOSITA would find it obvious to utilize p+ implants when forming the source and drain region of modified Radosavljevic using the ion implantation of Hareland, as this is a known implant type that predictably forms a source or drain region for PMOS devices. See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Radosavljevic et al. (US 2007/0001219) of record as applied to claim 15 above, and further in view of Chou et al. (US 2023/0261069) of record, and Huang et al. (US 2014/0145242) and Chien et al. (US 2012/0115284) both of record.
(Re Claim 18) Radosavljevic teaches the method of claim 15, wherein the method includes forming the gate as a high-k metal gate in a replacement gate process.
Radosavljevic has not been shown to explicitly teach the method includes forming the gate as a high-k metal gate in a replacement gate process.
Radosavljevic does describe forming the gate using “replacement gate” methods (¶47).
Chou teaches forming a gate as a polysilicon gate (64; Fig. 4, ¶30) on a gate nitride (62; Fig. 4, ¶30);
replacing the polysilicon gate and the gate nitride with a metal gate (114; Fig. 11A, ¶¶44-45) on a gate dielectric (112; Fig. 11A, ¶¶44-45) including a dielectric having a dielectric constant greater than 3.9 (hafnium oxide; ¶46); and
forming a gate contact (162; Fig. 25C) to the metal gate, a drain contact (right 164; Fig. 25C) to a drain region (88+136; right Fig. 25C), and a source contact (left 164; Fig. 25C) to a source region (left 88+136; Fig. 25C).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious form the gate of Radosavljevic by forming a polysilicon gate on a gate nitride that are both then replaced with a metal gate on a gate dielectric as taught by Chou (Chou: “replacement gate structures”; ¶45), thus forming the gate as a high-k metal gate in a replacement gate process as claimed, as utilizing metal gates with high-k dielectrics decreases device leakage (Huang: ¶1), and forming the high-k dielectric after performing high temperature operations to repair damage associated with implanting the source and drain regions (Radosavljevic: ¶48) of Radosavljevic protects the high-k dielectric material from deterioration (Chien: ¶6). A PHOSITA would also find it obvious to form the gate contact to the metal gate, a drain contact to the drain region, and a source contact to the source region of modified Radosavljevic, in order to interact with the fin field-effect transistor of modified Radosavljevic so that it may be utilized as a circuit component. See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Furthermore, forming a gate contact to a metal gate, a drain contact to a drain region, and a source contact to a source region are understood to be conventional features in the art (remarks 2/26/2026, p. 1).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Radosavljevic et al. (US 2007/0001219) of record as applied to claim 15 above, and further in view of Chou et al. (US 2023/0261069) of record, and Huang et al. (US 2014/0145242) and Chien et al. (US 2012/0115284) both of record as applied to claim 18 above, and further in view of Kelly et al. (US 2013/0249019) of record.
(Re Claim 19) Modified Radosavljevic teaches the method of claim 18, but has not been shown to explicitly teach the metal gate includes a work function metal and a primary metal.
Kelly teaches forming a metal gate includes forming a work function metal (56; Fig. 11a) between a gate dielectric (42; Fig. 11a) and a metal gate (58; Fig. 11a), such that the work function metal is an outer boundary of the gate metal and the metal gate fills a region defined by the outer boundary with a primary metal for the metal gate (Fig. 11a and 11b; ¶34).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the metal gate of modified Radosavljevic as taught by Kelly in order to improve the work function or alter the threshold voltage of the fin field-effect transistor (Kelly: ¶33). This results in the metal gate including a work function metal (Kelly: 56) and a primary metal (Kelly: 58).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Radosavljevic et al. (US 2007/0001219) of record, and Chou et al. (US 2023/0261069) of record, and Huang et al. (US 2014/0145242) and Chien et al. (US 2012/0115284) both of record, and Kelly et al. (US 2013/0249019) of record, as applied to claim 19 above, and further in view of Kim (US 2013/0299914) of record.
(Re Claim 20) Modified Radosavljevic teaches the method of claim 19, wherein the work function metal includes titanium nitride or tantalum nitride (Kelly: ¶33), and the gate dielectric includes hafnium oxide (Chou: ¶46).
Modified Radosavljevic has not been shown to teach the method wherein the primary metal includes tungsten and gate dielectric includes hafnium oxide on silicon oxide.
Chou teaches that the primary metal of a metal gate (114) may be aluminum or tungsten (¶47).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to use tungsten instead of aluminum as the primary metal of the metal gate of modified Radosavljevic as these are art recognized alternatives suitable for forming the gates of fin field-effect transistors. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Kim teaches forming a dielectric (131; Fig. 13) on a silicon oxide (125; Fig. 13-14) that is both on a semiconductor fin (F1; Fig. 14) and between a source (261 on the left; Fig. 15) region and a drain (261 on the right; Fig. 15) region.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form a silicon oxide taught by Kim, before forming the gate dielectric of Radosavljevic, to prevent a defect interface between the bulk semiconductor region and the gate dielectric (Kim: ¶37).
This results in the gate dielectric of modified Radosavljevic including both hafnium oxide from Chou and the silicon oxide layer from Kim.
Response to Arguments
Applicant's arguments filed 6/26/2026 have been fully considered but they are not persuasive.
The Applicant appears to argue that the fins must have uniform properties throughout the fin (remarks, p. 14), but this is not required by the claim language. Claims 1, 9, and 15 recite “semiconductor fins having the semiconductor composition of the bulk semiconductor throughout the fin”; a doped region may possess the semiconductor composition of a different, bulk semiconductor even if that bulk semiconductor is not itself doped – such as when both semiconductor compositions are silicon or GaN; there is no apparent requirement here that the material properties of the fins and bulk semiconductor are the same throughout. Furthermore, such an interpretation of the claim language as argued by the Applicant is not originally supported. See the 112(a) rejection for new matter above.
Applicant also argues that claim 1 teaches a transistor structure with fins connecting source/drains without the fins including source/drains (remarks, p. 14), but the claim language is not so limiting. The language of claim 1 does not preclude the presence of regions that may function as source/drains from existing within fins as nothing is present in the claim to require a particular doping of the fins or that otherwise constrains where dopants may exist that renders the rejection defective. Applicant claims source/drain regions without more language that would require absorbing any doped parts of the fin into the mapping for the source/drain regions. Furthermore, a fin may be doped and still be a fin (Radosavljevic: ¶48). Also, generally in the art it is understood that a fin’s channel region lies underneath a gate, and the regions of the fin outside of this channel region are understood to be source/drains. Applicant’s Fig. 7 appears then to demonstrate that the fins have source/drain regions, as the fins extend outside of the gate 710. Compare Applicant’s Fig. 7 to Radosavljevic’s Fig. 3I.
The remainder of Applicant’s arguments are moot.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHRISTOPHER A. SCHODDE/Examiner, Art Unit 2898
/ERIK T. K. PETERSON/Primary Examiner, Art Unit 2898
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