DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification/Drawings
The amendment filed 9/25/2025 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows: ¶56 and new Fig. 15 now constrain the formation of contacts to be after forming a metal gate. Furthermore, new Fig. 5B now shows a gate dielectric 512B having multiple dielectric regions 512B-1 and 512B-2. The location and extent of these multiple dielectric regions is now shown with a specificity incommensurate with the original disclosure. Notably too, it is unclear if Fig. 5B demonstrates either partially or completely an embodiment where a bulk semiconductor has a recessed region with one or more semiconductor fins in the recessed region as required by claim 1 (see the drawing objection related to claim 3 here and in the Non-Final mailed 6/26/2025).
Applicant is required to cancel the new matter in the reply to this Office Action.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore,
the step of forming the gate as a polysilicon gate on a silicon nitride and then replacing the polysilicon gate and the gate nitride with a metal gate on a gate dielectric as found in claim 17; and
a gate dielectric having multiple dielectric regions as found in claim 3, where the bulk semiconductor region has a recessed region; and
a source, gate, and drain contact for a method involving fins in a recessed region as found in claim 18.
must be shown or the feature(s) canceled from the claim(s). For the step of forming objected to here as found in claim 17, though new Fig. 15 now echoes the written specification, this is not equivalent to showing the structure of the step. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Goto et al. (US 2014/0070328) and Schloesser et al. (US 2006/0056228), both of record.
(Re Claim 1) Goto teaches a fin field-effect transistor comprising: a bulk semiconductor region (702; Fig. 7B markup) having a recessed region (gap in 718 and 708 where the gate is formed; Fig. 7B-7D); a source region (left part of 718; Fig. 7A and 7D) and structured as a first top portion of the bulk semiconductor region (Fig. 7B), the source region located adjacent to a first side of the recessed region (Fig. 7B); a drain region (right part of 718; Fig. 7A and 7D) structured as a second top portion of the bulk semiconductor region (Fig. 7B), the drain region located adjacent to a second side of the recessed region (Fig. 7B), the first side being opposite the second side (Fig. 7B and 7D); one or more semiconductor fins (704+706; Fig. 7B); and
a gate (724; Fig. 7C) at least partially in the recessed region.
Goto does not explicitly teach a fin field-effect transistor wherein one or more semiconductor fins are in the recessed region; the one or more semiconductor fins contacting and ending at the source region contacting and ending at the drain region; and
The gate wrapped around the one or more semiconductor fins.
However, Goto does show that the current passes through a channel region above layer 716 and in the recessed region (Fig. 7D).
Additionally, Schloesser shows that current in a FinFET passes through a region of a fin (11; Fig. 1B) that is surrounded by a gate (85; Fig. 1A and 1B).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious that, as the on current of Goto’s fin field-effect transistor passes through the recess, the fins 704+706 must also pass through the recess along this current path, as this is how fin field-effect transistors operate (Goto: ¶¶2-3; Schloesser: Fig. 1A-1B, ¶15). See also Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Therefore, Goto in view of Schloesser teaches that a fin field-effect transistor wherein one or more semiconductor fins (704+706; Fig. 7B) are in the recessed region (as they cross from the source to the drain region; Fig. 7D);
the one or more semiconductor fins contacting and ending at the source region and contacting and ending at the drain region (the top face of the semiconductor fins contact, and end at, the source and drain regions; “ending at” does not require a particular part of the semiconductor fins to end at the source and drain region; Fig. 7B and 7D); and
a gate (724; Fig. 7C, ¶64) wrapped around the one or more semiconductor fins (Goto: Fig. 7C and 7D, ¶¶2-3).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Goto et al. (US 2014/0070328), Schloesser et al. (US 2006/0056228) as applied to claim 1 above, and further in view of Yang et al. (US 2020/0105938) and Kelly et al. (US 2013/0249019), all of record.
(Re Claim 2) Modified Goto teaches the fin field-effect transistor of claim 1, but does not explicitly teach wherein the one or more semiconductor fins are composed of material of the bulk semiconductor region.
However, though Goto does not explicitly teach the material of the bulk substrate as shown in Fig. 7A-7D, Goto does teach forming a bulk semiconductor substrate (102; Fig. 1A, ¶24) using silicon.
Yang teaches forming fins (218; Fig. 5A) by etching a bulk semiconductor substrate (202; Fig. 5A, ¶26).
Kelly teaches fins may be formed using silicon (¶16).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the bulk semiconductor substrate using silicon as silicon is suitable for forming bulk semiconductor substrates. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Furthermore, a PHOSITA would find it obvious to form the fins of modified Goto by etching the bulk semiconductor as taught by Yang, as silicon has suitable electronic properties for forming fins of a fin field-effect transistor device (Kelly: ¶16). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
As the fins are formed by etching into the bulk semiconductor substrate, the fins and bulk semiconductor region are composed of the same material.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Goto et al. (US 2014/0070328) and Schloesser et al. (US 2006/0056228) as applied to claim 1 above, and further in view of Chou et al. (US 2023/0261069), all of record.
(Re Claim 3) Modified Goto fin field-effect transistor of claim 1, but does not explicitly teach wherein the gate is separated from each of the one or more semiconductor fins by a gate dielectric having multiple dielectric regions.
Chou teaches separating a gate (114; Fig. 12A) from one or more semiconductor fins (58; Fig. 12A) by a gate dielectric (112) having multiple dielectric regions (left, right, and center portions of the gate dielectric; Fig. 12A).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the gate of modified Goto such that it is separated from each of the one or more semiconductor fins by a gate dielectric having multiple dielectric regions, as taught by Chou, to prevent shorting.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Goto et al. (US 2014/0070328), Schloesser et al. (US 2006/0056228), and Chou et al. (US 2023/0261069) as applied to claim 3 above, and further in view of Yang et al. (US 2020/0105938) and Kelly et al. (US 2013/0249019), all of record.
(Re Claim 4) Modified Goto teaches the fin field-effect transistor of claim 3, wherein the gate includes a metal structure (¶64).
Modified Goto does not explicitly teach the bulk semiconductor region and the one or more semiconductor fins include silicon, and the gate dielectric includes a dielectric having a dielectric constant greater than 3.9.
However, though Goto does not explicitly teach the material of the bulk substrate as shown in Fig. 7A-7D, Goto does teach forming a bulk semiconductor substrate (102; Fig. 1A, ¶24) using silicon.
Yang teaches forming fins (218; Fig. 5A) by etching a bulk semiconductor substrate (202; Fig. 5A, ¶26).
Kelly teaches fins may be formed using silicon (¶16).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the bulk semiconductor substrate using silicon as silicon is suitable for forming bulk semiconductor substrates. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Furthermore, a PHOSITA would find it obvious to form the fins of modified Goto by etching the bulk semiconductor as taught by Yang, as silicon has suitable electronic properties for forming fins of a fin field-effect transistor device (Kelly: ¶16). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
As the fins are formed by etching into the bulk semiconductor substrate, the fins and bulk semiconductor region are composed of silicon.
Chou additionally teaches forming the gate dielectric using materials having a dielectric constant greater than about 7, including a hafnium metal oxide (¶64).
A PHOSITA would find it obvious to form the gate dielectric of modified Goto with a dielectric constant greater than 3.9, as suitable materials include materials having dielectric constants greater than 7 including hafnium oxide. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
(Re Claim 5) Modified Goto teaches the fin field-effect transistor of claim 4, wherein the dielectric is located on a silicon oxide (714; Fig. 7D, ¶63) between the source region and the drain region (Fig. 7D).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Goto et al. (US 2014/0070328) and Schloesser et al. (US 2006/0056228) as applied to claim 1 above, and further in view of Lee et al. (US 2004/0256647), Chen et al. (US 2023/0282751), Yang et al. (US 2020/0105938) and Kelly et al. (US 2013/0249019), all of record.
(Re Claim 6) Modified Goto teaches the fin field-effect transistor of claim 1, but does not explicitly teach wherein the fin field-effect transistor is a p-channel fin field-effect transistor with the source region and the drain region including epitaxial silicon germanium.
Goto teaches forming a bulk semiconductor substrate (102; Fig. 1A, ¶24) using silicon.
Yang teaches forming fins (218; Fig. 5A) by etching a bulk semiconductor substrate (202; Fig. 5A, ¶26).
Kelly teaches fins may be formed using silicon (¶16).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the bulk semiconductor substrate using silicon as silicon is suitable for forming bulk semiconductor substrates. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Furthermore, a PHOSITA would find it obvious to form the fins of modified Goto by etching the bulk semiconductor as taught by Yang, as silicon has suitable electronic properties for forming fins of a fin field-effect transistor device (Kelly: ¶16). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Chen teaches that the channel type of a fin field-effect transistor is determined by local dopant concentrations in the bulk semiconductor in which the fins are formed (¶26).
A PHOSITA would find it obvious to form the fin field-effect transistor of Goto (700; Fig. 7D) in a region of the bulk semiconductor having n-type dopants, as taught by Chen, when the different device characteristics of a p-channel fin field-effect transistor are required, such as improved hole mobility, compared to that of an n-channel fin field-effect transistor. See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Lee teaches epitaxially grown source and drain regions comprising silicon germanium (¶46).
A PHOSITA would find it obvious to use silicon germanium for the epitaxial layer of the source and drain regions of modified Goto, as taught by Lee, in order to increase hole mobility (Lee: ¶46).
Claims 7-8 rejected under 35 U.S.C. 103 as being unpatentable over Goto et al. (US 2014/0070328) and Schloesser et al. (US 2006/0056228) as applied to claim 1 above, and further in view of Chou et al. (US 2023/0261069), Chen et al. (US 2023/0282751), Yang et al. (US 2020/0105938) and Kelly et al. (US 2013/0249019), all of record.
(Re Claim 7) Modified Goto teaches the fin field-effect transistor of claim 1, but does not explicitly teach wherein the fin field-effect transistor is a p-channel fin field-effect transistor with the source region and the drain region including p+ implants.
Goto teaches forming a bulk semiconductor substrate (102; Fig. 1A, ¶24) using silicon.
Yang teaches forming fins (218; Fig. 5A) by etching a bulk semiconductor substrate (202; Fig. 5A, ¶26).
Kelly teaches fins may be formed using silicon (¶16).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the bulk semiconductor substrate using silicon as silicon is suitable for forming bulk semiconductor substrates. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Furthermore, a PHOSITA would find it obvious to form the fins of modified Goto by etching the bulk semiconductor as taught by Yang, as silicon has suitable electronic properties for forming fins of a fin field-effect transistor device (Kelly: ¶16). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Chen teaches that the channel type of a fin field-effect transistor is determined by local dopant concentrations in the bulk semiconductor in which the fins are formed (¶26).
A PHOSITA would find it obvious to form the fin field-effect transistor of Goto (700; Fig. 7D) in a region of the bulk semiconductor having n-type dopants, as taught by Chen, when the different device characteristics of a p-channel fin field-effect transistor are required, such as improved hole mobility, compared to that of an n-channel fin field-effect transistor. See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Chou teaches implanting p+ dopants into an epitaxially grown source or drain region (88; Fig. 9B, ¶58).
A PHOSITA would find it obvious to form the fin field-effect transistor of modified Goto such that the source and drain regions include p+ implants as taught by Chou, in order to decrease the contact resistance to the source and drain regions (Chou: ¶55).
(Re Claim 8) Modified Goto teaches the fin field-effect transistor of claim 1, but does not explicitly teach wherein the fin field-effect transistor is a n-channel fin field-effect transistor with the source region and the drain region including n+ implants.
Goto teaches forming a bulk semiconductor substrate (102; Fig. 1A, ¶24) using silicon.
Yang teaches forming fins (218; Fig. 5A) by etching a bulk semiconductor substrate (202; Fig. 5A, ¶26).
Kelly teaches fins may be formed using silicon (¶16).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the bulk semiconductor substrate using silicon as silicon is suitable for forming bulk semiconductor substrates. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Furthermore, a PHOSITA would find it obvious to form the fins of modified Goto by etching the bulk semiconductor as taught by Yang, as silicon has suitable electronic properties for forming fins of a fin field-effect transistor device (Kelly: ¶16). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Chen teaches that the channel type of a fin field-effect transistor is determined by local dopant concentrations in the bulk semiconductor in which the fins are formed (¶26).
A PHOSITA would find it obvious to form the fin field-effect transistor of Goto (700; Fig. 7D) in a region of the bulk semiconductor having p-type dopants, as taught by Chen, when the different device characteristics of an n-channel fin field-effect transistor are required, such as improved switching speed, compared to that of a p-channel fin field-effect transistor. See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Chou teaches implanting n+ dopants into an epitaxially grown source or drain region (88; Fig. 9B, ¶58).
A PHOSITA would find it obvious to form the fin field-effect transistor of modified Goto such that the source and drain regions include n+ implants as taught by Chou, in order to decrease the contact resistance to the source and drain regions (Chou: ¶55).
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US 2011/0182098), Goto et al. (US 2014/0070328), and Schloesser et al. (US 2006/0056228), all of record.
(Re Claim 9) Liaw teaches a memory device comprising: an array (101; Fig. 1) of memory cells (101a; ¶¶18-19); and circuits (105; Fig. 1, ¶25) for controlling operation of the array (¶25), the circuits including a fin field-effect transistor (¶3).
Liaw does not teach the fin field-effect transistor including: a source region structured as a first top portion of a bulk semiconductor region, the source region located adjacent to a first side of a recessed region in the bulk semiconductor; a drain region structured as a second top portion of the bulk semiconductor region, the drain region located adjacent to a second side of the recessed region, the first side being opposite the second side; one or more semiconductor fins in the recessed region, the one or more semiconductor fins contacting and ending at the source region and contacting and ending at the drain region; and a gate wrapped around the one or more semiconductor fins, the gate at least partially in the recessed region.
Goto teaches a fin field-effect transistor comprising:
a source region (left part of 718; Fig. 7D) structured as a first top portion of a bulk semiconductor region (702; Fig. 7A), the source region located adjacent to a first side (left side of the recessed region; Fig. 7D) of a recessed region;
a drain region (right part of 718; Fig. 7D) structured as a second top portion of the bulk semiconductor region (Fig. 7A-7D), the drain region located adjacent to a second side (right side of recessed region; Fig. 7D) of the recessed region, the first side being opposite the second side (Fig. 7D); and
a gate (724; Fig. 7C) at least partially in the recessed region.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to use the fin field-effect transistors of Goto in the circuits of Liaw, as Goto’s transistors have reduced off current (¶48).
Goto does not explicitly teach a fin field-effect transistor wherein one or more semiconductor fins are in the recessed region; the one or more semiconductor fins contact the source region and the drain region; and
the gate wrapped around the one or more semiconductor fin.
However, Goto does show that the current passes through a channel region above layer 716 and in the recessed region (Fig. 7D).
Additionally, Schloesser shows that current in a FinFET passes through a region of a fin (11; Fig. 1B) that is surrounded by a gate (85; Fig. 1A and 1B).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious that, as the on current of Goto’s fin field-effect transistor passes through the recess, the fins 704+706 must also pass through the recess along this current path, as this is how fin field-effect transistors operate (Goto: ¶¶2-3; Schloesser: Fig. 1A-1B, ¶15). See also Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Therefore, Goto in view of Schloesser teaches that a fin field-effect transistor wherein one or more semiconductor fins (704+706; Fig. 7B) are in the recessed region (as they cross from the source to the drain region; Fig. 7D);
the one or more semiconductor fins contacting and ending at the source region and contacting and ending at the drain region (the top face of the semiconductor fins contact, and end at, the source and drain regions; “ending at” does not require a particular part of the semiconductor fins to end at the source and drain region; Fig. 7B and 7D); and
a gate (724; Fig. 7C, ¶64) wrapped around the one or more semiconductor fins (Goto: Fig. 7C and 7D, ¶¶2-3).
And so the fin field-effect transistors of Liaw have the structure according to modified Goto.
(Re Claim 10) Modified Liaw teaches the memory device of claim 9, wherein the circuits are located in a periphery region (region to the left of the memory array; Fig. 1) adjacent the memory array.
(Re Claim 11) Modified Liaw teaches the memory device of claim 9, wherein the circuits are located in a region under the memory array (from the view after turning Fig. 1 counterclockwise 90°; the orientation of a device does not impart patentability).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US 2011/0182098), Goto et al. (US 2014/0070328), and Schloesser et al. (US 2006/0056228), as applied to claim 9 above, and further in view of Lee et al. (US 2004/0256647) and Chen et al. (US 2023/0282751), all of record.
(Re Claim 12) Modified Liaw teaches the memory device of claim 9, but does not explicitly teach wherein the fin field-effect transistor is a p-channel fin field-effect transistor with the source region and the drain region including epitaxial silicon germanium.
Goto teaches forming a bulk semiconductor substrate (102; Fig. 1A, ¶24) using silicon.
Yang teaches forming fins (218; Fig. 5A) by etching a bulk semiconductor substrate (202; Fig. 5A, ¶26).
Kelly teaches fins may be formed using silicon (¶16).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the bulk semiconductor substrate using silicon as silicon is suitable for forming bulk semiconductor substrates. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Furthermore, a PHOSITA would find it obvious to form the fins of modified Goto by etching the bulk semiconductor as taught by Yang, as silicon has suitable electronic properties for forming fins of a fin field-effect transistor device (Kelly: ¶16). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Chen teaches that the channel type of a fin field-effect transistor is determined by local dopant concentrations in the bulk semiconductor in which the fins are formed (¶26).
A PHOSITA would find it obvious to form the fin field-effect transistor of Goto (700; Fig. 7D) in a region of the bulk semiconductor having n-type dopants, as taught by Chen, when the different device characteristics of a p-channel fin field-effect transistor are required, such as improved hole mobility, compared to that of an n-channel fin field-effect transistor. See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Lee teaches epitaxially grown source and drain regions comprising silicon germanium (¶46).
A PHOSITA would find it obvious to use silicon germanium for the epitaxial layer of the source and drain regions of modified Liaw, as taught by Lee, in order to increase hole mobility (Lee: ¶46).
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US 2011/0182098), Goto et al. (US 2014/0070328), and Schloesser et al. (US 2006/0056228), as applied to claim 9 above, and further in view of Chou et al. (US 2023/0261069) and Chen et al. (US 2023/0282751), all of record.
(Re Claim 13) Modified Liaw memory device of claim 9, but does not explicitly teach wherein the fin field-effect transistor is a p-channel fin field-effect transistor with the source region and the drain region including p+ implants.
Goto teaches forming a bulk semiconductor substrate (102; Fig. 1A, ¶24) using silicon.
Yang teaches forming fins (218; Fig. 5A) by etching a bulk semiconductor substrate (202; Fig. 5A, ¶26).
Kelly teaches fins may be formed using silicon (¶16).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the bulk semiconductor substrate using silicon as silicon is suitable for forming bulk semiconductor substrates. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Furthermore, a PHOSITA would find it obvious to form the fins of modified Goto by etching the bulk semiconductor as taught by Yang, as silicon has suitable electronic properties for forming fins of a fin field-effect transistor device (Kelly: ¶16). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Chen teaches that the channel type of a fin field-effect transistor is determined by local dopant concentrations in the bulk semiconductor in which the fins are formed (¶26).
A PHOSITA would find it obvious to form the fin field-effect transistor of Goto (700; Fig. 7D) in a region of the bulk semiconductor having n-type dopants, as taught by Chen, when the different device characteristics of a p-channel fin field-effect transistor are required, such as improved hole mobility, compared to that of an n-channel fin field-effect transistor. See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Chou teaches implanting p+ dopants into an epitaxially grown source or drain region (88; Fig. 9B, ¶58).
A PHOSITA would find it obvious to form the fin field-effect transistor of modified Liaw such that the source and drain regions include p+ implants as taught by Chou, in order to decrease the contact resistance to the source and drain regions (Chou: ¶55).
(Re Claim 14) Modified Liaw teaches the memory device of claim 9, but does not explicitly teach wherein the fin field-effect transistor is a n-channel fin field-effect transistor with the source region and the drain region including n+ implants.
Goto teaches forming a bulk semiconductor substrate (102; Fig. 1A, ¶24) using silicon.
Yang teaches forming fins (218; Fig. 5A) by etching a bulk semiconductor substrate (202; Fig. 5A, ¶26).
Kelly teaches fins may be formed using silicon (¶16).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the bulk semiconductor substrate using silicon as silicon is suitable for forming bulk semiconductor substrates. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Furthermore, a PHOSITA would find it obvious to form the fins of modified Goto by etching the bulk semiconductor as taught by Yang, as silicon has suitable electronic properties for forming fins of a fin field-effect transistor device (Kelly: ¶16). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Chen teaches that the channel type of a fin field-effect transistor is determined by local dopant concentrations in the bulk semiconductor in which the fins are formed (¶26).
A PHOSITA would find it obvious to form the fin field-effect transistor of Goto (700; Fig. 7D) in a region of the bulk semiconductor having p-type dopants, as taught by Chen, when the different device characteristics of an n-channel fin field-effect transistor are required, such as improved switching speed, compared to that of a p-channel fin field-effect transistor. See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Chou teaches implanting n+ dopants into an epitaxially grown source or drain region (88; Fig. 9B, ¶58).
A PHOSITA would find it obvious to form the fin field-effect transistor of modified Liaw such that the source and drain regions include n+ implants as taught by Chou, in order to decrease the contact resistance to the source and drain regions (Chou: ¶55).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Goto et al. (US 2014/0070328) and Schloesser et al. (US 2006/0056228), all of record.
(Re Claim 15) Goto teaches a method comprising: forming a source region (left part of 718; Fig. 7D) as a first top portion of a bulk semiconductor region and adjacent to a first side (left side; Fig. 7D) of a recessed region (gap in 718 and 708; Fig. 7A-7D) in the bulk semiconductor region; forming a drain region (right part of 718; Fig. 7D) as a second top portion of the bulk semiconductor region and adjacent to a second side (right side; Fig. 7D) of the recessed region, the first side being opposite the second side (Fig. 7D); and
forming a gate at least partially located in the recessed region (Fig. 7C).
Goto does not explicitly teach a method comprising: forming one or more semiconductor fins in the recessed region including forming the one or more semiconductor fins contacting the source region and the drain region; and forming a gate wrapped around the one or more semiconductor fins such that the gate at least partially is located in the recessed region.
However, Goto does show that the current passes through a channel region above layer 716 and in the recessed region (Fig. 7D).
Additionally, Schloesser shows that current in a FinFET passes through a region of a fin (11; Fig. 1B) that is surrounded by a gate (85; Fig. 1A and 1B).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious that, as the on current of Goto’s fin field-effect transistor passes through the recess, the fins 704+706 must also pass through the recess along this current path, as this is how fin field-effect transistors operate (Goto: ¶¶2-3; Schloesser: Fig. 1A-1B, ¶15). See also Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Therefore, Goto in view of Schloesser teaches forming a fin field-effect transistor by forming one or more semiconductor fins (704+706; Fig. 7B) in the recessed region (as they cross from the source to the drain region; Fig. 7D) including forming the one or more semiconductor fins contacting the source region and the drain region (Fig. 7B and 7D); and
and forming a gate (724; Fig. 7C, ¶64) wrapped around the one or more semiconductor fins (Goto: Fig. 7C and 7D, ¶¶2-3).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Goto et al. (US 2014/0070328) and Schloesser et al. (US 2006/0056228) as applied to claim 15 above, and further in view of Lee et al. (US 2004/0256647), all of record.
(Re Claim 16) Modified Goto teaches the method of claim 15, but does not explicitly teach the method wherein forming the source region and the drain region includes epitaxially forming p+ silicon germanium.
Goto teaches forming a bulk semiconductor substrate (102; Fig. 1A, ¶24) using silicon.
Yang teaches forming fins (218; Fig. 5A) by etching a bulk semiconductor substrate (202; Fig. 5A, ¶26).
Kelly teaches fins may be formed using silicon (¶16).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the bulk semiconductor substrate using silicon as silicon is suitable for forming bulk semiconductor substrates. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Furthermore, a PHOSITA would find it obvious to form the fins of modified Goto by etching the bulk semiconductor as taught by Yang, as silicon has suitable electronic properties for forming fins of a fin field-effect transistor device (Kelly: ¶16). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Chen teaches that the channel type of a fin field-effect transistor is determined by local dopant concentrations in the bulk semiconductor in which the fins are formed (¶26).
A PHOSITA would find it obvious to form the fin field-effect transistor of Goto (700; Fig. 7D) in a region of the bulk semiconductor having n-type dopants, as taught by Chen, when the different device characteristics of a p-channel fin field-effect transistor are required, such as improved hole mobility, compared to that of an n-channel fin field-effect transistor. See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Lee teaches epitaxially grown source and drain regions comprising silicon germanium (¶46).
A PHOSITA would find it obvious to use silicon germanium for the epitaxial layer of the source and drain regions of modified Goto, as taught by Lee, in order to increase hole mobility (Lee: ¶46).
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Goto et al. (US 2014/0070328) and Schloesser et al. (US 2006/0056228) as applied to claim 15 above, and further in view of Chou et al. (US 2023/0261069), all of record.
(Re Claim 17) Modified Goto teaches method of claim 15, but does not teach the method wherein forming the source region and the drain region includes forming the source region and the drain region with p+ implants.
Goto teaches forming a bulk semiconductor substrate (102; Fig. 1A, ¶24) using silicon.
Yang teaches forming fins (218; Fig. 5A) by etching a bulk semiconductor substrate (202; Fig. 5A, ¶26).
Kelly teaches fins may be formed using silicon (¶16).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the bulk semiconductor substrate using silicon as silicon is suitable for forming bulk semiconductor substrates. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Furthermore, a PHOSITA would find it obvious to form the fins of modified Goto by etching the bulk semiconductor as taught by Yang, as silicon has suitable electronic properties for forming fins of a fin field-effect transistor device (Kelly: ¶16). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Chen teaches that the channel type of a fin field-effect transistor is determined by local dopant concentrations in the bulk semiconductor in which the fins are formed (¶26).
A PHOSITA would find it obvious to form the fin field-effect transistor of Goto (700; Fig. 7D) in a region of the bulk semiconductor having n-type dopants, as taught by Chen, when the different device characteristics of a p-channel fin field-effect transistor are required, such as improved hole mobility, compared to that of an n-channel fin field-effect transistor. See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Chou teaches implanting p+ dopants into an epitaxially grown source or drain region (88; Fig. 9B, ¶58).
A PHOSITA would find it obvious to form the fin field-effect transistor of modified Goto such that the source and drain regions include p+ implants as taught by Chou, in order to decrease the contact resistance to the source and drain regions (Chou: ¶55).
(Re Claim 18) Modified Goto teaches the method of claim 15, but does not explicitly teach the method wherein the method includes: forming the gate as a polysilicon gate on a gate nitride; replacing the polysilicon gate and the gate nitride with a metal gate on a gate dielectric including a dielectric having a dielectric constant greater than 3.9; and forming a gate contact to the metal gate, a drain contact to the drain region, and a source contact to the source region.
Chou teaches forming a gate as a polysilicon gate (64; Fig. 4, ¶30) on a gate nitride (62; Fig. 4, ¶30);
replacing the polysilicon gate and the gate nitride with a metal gate (114; Fig. 11A, ¶¶44-45) on a gate dielectric (112; Fig. 11A, ¶¶44-45) including a dielectric having a dielectric constant greater than 3.9 (hafnium oxide; ¶46); and
forming a gate contact (162; Fig. 25C) to the metal gate, a drain contact (right 164; Fig. 25C) to a drain region (88+136; right Fig. 25C), and a source contact (left 164; Fig. 25C) to a source region (left 88+136; Fig. 25C).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to fill the recessed region of modified Goto (Fig. 7B) to form the gate 724, according to the sequence of Chou, in order to take advantage of the different etch selectivities of the polysilicon and gate nitride. See also Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Furthermore, a PHOSITA would find it obvious to form gate, drain, and source contacts respectively connected to the metal gate, drain region, and source region of modified Goto as taught by Chou, in order to interact with the fin field-effect transistor of modified Goto so that it may be utilized as a circuit component (Chou: ¶88). See also Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Goto et al. (US 2014/0070328), Schloesser et al. (US 2006/0056228), and Chou et al. (US 2023/0261069) as applied to claim 18 above, and further in view of Kelly et al. (US 2013/0249019), all of record.
(Re Claim 19) Modified Goto teaches the method of claim 18, but does not explicitly teach the method wherein forming the metal gate includes forming a work function metal as an outer boundary of the gate metal and filling a region defined by the outer boundary with a primary metal for the metal gate.
Kelly teaches forming a metal gate includes forming a work function metal (56; Fig. 11a) between a gate dielectric (42; Fig. 11A) and a metal gate (58; Fig. 11A), such that the work function metal is an outer boundary of the gate metal and the metal gate fills a region defined by the outer boundary with a primary metal for the metal gate (Fig. 11a and 11b; ¶34).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the metal gate of modified Goto as taught by Kelly in order to improve the work function or alter the threshold voltage of the fin field-effect transistor (Kelly: ¶33).
(Re Claim 20) Modified Goto teaches the method of claim 19, wherein the work function metal incudes titanium nitride or tantalum nitride (Kelly: ¶33) and the gate dielectric includes hafnium oxide (Chou: ¶46) on silicon oxide (Goto: 714).
Modified Goto does not explicitly teach the method wherein the primary metal includes tungsten.
Chou teaches that the primary metal of metal gate (114) may be aluminum or tungsten (¶47).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to use tungsten instead of aluminum as the primary metal of