DETAILED ACTION/EXAMINER’S COMMENT
This Office action responds to the amendments filed on 02/03/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
Applicant’s response filed on 02/03/2026 in reply to the final rejection mailed on 12/03/2025, has been entered. The present Office action is made with all previously suggested amendments being fully considered. Claim 28 is added. Claims 1-17 & 28 will be examined in this Office action.
Claims Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-15 are rejected under 35 U.S.C. 103 as being unpatentable over Alsmeier (US 20120001247) in view of Zhang (US 20150357413).
Regarding Claim 1, Alsmeier (see, e.g., fig. 42, annotated figure 42) shows a memory device comprising:
isolation layers 143 (143a & 143b) and gate structures, alternately stacked on a lower structure;
a tunnel isolation layer 11 (see, e.g., para.0047) penetrating the isolation layers and the gate structures;
a channel layer 1 (see, e.g., para.0070) formed along an inner wall of the tunnel isolation layer;
and a core plug 2 (see, e.g., para.0039) formed along an inner wall of the channel layer,
wherein each of the gate structures includes:
a floating gate 9 (9a & 9b, see, e.g., para.0046) surrounding an outer wall of the tunnel isolation layer;
a first dielectric layer 7 (see, e.g., para.0048) surrounding an outer wall of the floating gate;
and a gate line 3 (see, e.g., para.0122) formed between the isolation layers,
wherein each of the gate structures is spaced apart in a stacking direction of the isolation layers and the gate structures,
and the floating gate positioned adjacent to the first dielectric layer is disposed between the isolation layers (see, e.g., annotated figure 42),
Alsmeier, however, fails to show,
a second dielectric layer surrounding an outer wall of the first dielectric layer;
a third dielectric layer surrounding an outer wall of the second dielectric layer;
the gate line filling a region surrounded at least in part by the third dielectric layer,
wherein the third dielectric layer includes
a first portion;
a second portion
and a third portion,
wherein the second portion is disposed at one end of the first portion and the third portion is disposed at another end of the first portion,
wherein the first portion contacts a sidewall of the second dielectric layer,
wherein the second portion and the third portion extend in a direction away from the floating gate,
and wherein the gate line is disposed between the second portion and the third portion.
Zhang (see, e.g., fig. 1b, para.0027) in a similar device to Alsmeier teaches the dielectric layer 7 can be comprised of multiple dielectric layers. The duplication of the first dielectric layer of Alsmeier to teach a second and a third dielectric layer, and their subsequent missing limitations (see next paragraph and annotated figure 42), would be an obvious design choice. Unless a new and unexpected result is produced from the duplication of parts, it would have been obvious to one of ordinary skill in the art to duplicate the first dielectric layer of the device of Alsmeier, in view of the device of Zhang, as an obvious design choice, In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Alsmeier (see, e.g., annotated figure 42), in view of Zhang, shows
a second dielectric layer 7 (duplication in view of Zhang) surrounding an outer wall of the first dielectric layer;
a third dielectric layer 7 (duplication in view of Zhang) surrounding an outer wall of the second dielectric layer;
the gate line 3 filling a region surrounded at least in part by the third dielectric layer,
wherein the third dielectric layer includes
a first portion (middle portion);
a second portion (top portion)
and a third portion (bottom portion),
wherein the second portion is disposed at one end of the first portion and the third portion is disposed at another end of the first portion,
wherein the first portion contacts a sidewall of the second dielectric layer,
wherein the second portion and the third portion extend in a direction away from the floating gate,
and wherein the gate line 3 is disposed between the second portion and the third portion (also shown in limitation “gate line filling a region surrounded at least in part…”).
Regarding Claim 2, Alsmeier (see, e.g., figs. 36a-b), in view of Zhang, shows the memory device of claim 1,
wherein the core plug is formed in a cylindrical shape,
the channel layer is formed in a tubular shape surrounding a side surface of the core plug (top view shows tubular shape, see, e.g., figs. 36a-b),
and the tunnel isolation layer is formed in a tubular shape surrounding a side surface of the channel layer.
Regarding Claim 3, Alsmeier (see, e.g., para.0042, para.0048, para.0071), in view of Zhang, shows the memory device of claim 1,
wherein: the core plug is formed of an isolation material (see, e.g., para.0042),
the channel layer is formed of poly-silicon (see, e.g., para.0071),
and the tunnel isolation layer is formed of silicon oxide (see, e.g., para.0048).
Regarding Claim 4, Alsmeier (see, e.g., fig. 36a-b), in view of Zhang, shows the memory device of claim 1,
wherein the floating gate is formed in a tubular shape surrounding the tunnel isolation layer (top view shows tubular shape, see, e.g., figs. 36a-b).
Regarding Claim 5, Alsmeier (see, e.g., para.0049), in view of Zhang, shows the memory device of claim 1,
wherein the floating gate comprises a material capable of storing electrons.
Regarding Claim 6, Alsmeier (see, e.g., para.0049), in view of Zhang, shows the memory device of claim 1,
wherein the floating gate comprises at least one of titanium nitride (TiN) and tantalum nitride (TaN).
Regarding Claim 7, Alsmeier (see, e.g., para.0048), in view of Zhang (see, e.g., para.0037). shows the memory device of claim 1,
wherein the first dielectric layer comprises a material having a permittivity lower than a permittivity of each of the second and third dielectric layers.
Zhang (see, e.g., para.0037) teaches the first, second, and third dielectric layers can comprise a variety of materials, such as silicon oxide, silicon nitride, and aluminum oxide respectively. Thus Alsmeier, in view of Zhang, would satisfy the limitation and render the claim obvious.
Regarding Claim 8, Alsmeier, in view of Zhang (see, e.g., para.0037), shows the memory device of claim 1,
wherein the first dielectric layer comprises a material having an energy band gap higher than an energy band gap of the second dielectric layer.
Zhang (see, e.g., para.0037) teaches the first and second dielectric layers can comprise a variety of materials, such as silicon oxide and silicon nitride respectively. Thus Alsmeier, in view of Zhang, would satisfy the limitation and render the claim obvious.
Regarding Claim 9, Alsmeier (see, e.g., para.0048), in view of Zhang, shows the memory device of claim 1,
wherein the first dielectric layer comprises a silicon oxide.
Regarding Claim 10, Alsmeier, in view of Zhang (see, e.g., para.0037). shows the memory device of claim 1,
wherein: the second dielectric layer has a permittivity higher than a permittivity of the first dielectric layer and a permittivity of the third dielectric layers,
and the second dielectric layer has an energy band gap lower than an energy band gap of the first dielectric layer and lower than an energy band gap of the third dielectric layer.
Zhang (see, e.g., para.0037) teaches the first, second, and third dielectric layers can comprise a variety of materials, such as silicon oxide, hafnium oxide, and aluminum oxide respectively. Thus Alsmeier, in view of Zhang, would satisfy the limitation and render the claim obvious.
Regarding Claim 11, Alsmeier, in view of Zhang (see, e.g., para.0037), shows the memory device of claim 1,
wherein the second dielectric layer comprises at least one of silicon nitride, hafnium oxide, zirconium oxide, zirconium silicate, and hafnium silicate.
Regarding Claim 12, Alsmeier, in view of Zhang (see, e.g., para.0037), shows the memory device of claim 1,
wherein the third dielectric layer comprises an aluminum oxide.
Regarding Claim 13, Alsmeier (see, e.g., fig. 22a, para.0043, para.0093), in view of Zhang, shows the memory device of claim 1,
wherein the gate line is a select line or a word line, which is connected to a memory block.
Regarding Claim 14, Alsmeier (see, e.g., para.0122), in view of Zhang, shows the memory device of claim 1,
wherein the gate line comprises a conductive layer or a semiconductor layer.
Regarding Claim 15, Alsmeier (see, e.g., para.0122), in view of Zhang, shows the memory device of claim 1,
wherein the gate line comprises at least one of tungsten (W), tungsten nitride (WN), titanium nitride, molybdenum (Mo), cobalt (Co), nickel (Ni), silicon (Si), and poly-silicon (Poly-Si).
Regarding Claim 28, Alsmeier (see, e.g., fig. 42, annotated figure 42) shows a memory device comprising:
isolation layers and gate structures 143 (143a & 143b), alternately stacked on a lower structure;
a tunnel isolation layer 11 (see, e.g., para.0047) penetrating the isolation layers and the gate structures;
a channel layer 1 (see, e.g., para.0070) formed along an inner wall of the tunnel isolation layer;
and a core plug 2 (see, e.g., para.0039) formed along an inner wall of the channel layer,
wherein each of the gate structures includes:
a floating gate 9 (9a & 9b, see, e.g., para.0046) surrounding an outer wall of the tunnel isolation layer;
a first dielectric layer 7 (see, e.g., para.0048) surrounding an outer wall of the floating gate;
and a gate line 3 (see, e.g., para.0122) formed between the isolation layers,
wherein each of the gate structures is spaced apart in a stacking direction of the isolation layers and the gate structures,
and the floating gate positioned adjacent to the first dielectric layer is disposed between the isolation layers,
wherein the floating gate of each of the gate structures contacts to one of the isolation layers (top and bottom surface of each floating gate contacts isolation layers 143a & 143b, see, e.g., fig. 42).
Alsmeier, however, fails to show
a second dielectric layer surrounding an outer wall of the first dielectric layer;
a third dielectric layer surrounding an outer wall of the second dielectric layer;
the gate line filling a region surrounded at least in part by the third dielectric layer,
Zhang (see, e.g., fig. 1b, para.0027) in a similar device to Alsmeier teaches the dielectric layer 7 can be comprised of multiple dielectric layers. The duplication of the first dielectric layer of Alsmeier to teach a second and a third dielectric layer, and their subsequent missing limitations (see next paragraph and annotated figure 42), would be an obvious design choice. Unless a new and unexpected result is produced from the duplication of parts, it would have been obvious to one of ordinary skill in the art to duplicate the first dielectric layer of the device of Alsmeier, in view of the device of Zhang, as an obvious design choice, In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Alsmeier (see, e.g., annotated figure 42), in view of Zhang, shows
a second dielectric layer 7 (duplication in view of Zhang) surrounding an outer wall of the first dielectric layer;
a third dielectric layer 7 (duplication in view of Zhang) surrounding an outer wall of the second dielectric layer;
the gate line 3 filling a region surrounded at least in part by the third dielectric layer (between second and third portion of the third dielectric layer),
Claims 16 & 17 are rejected under 35 U.S.C. 103 as being unpatentable over Alsmeier (US 20120001247) in view of Zhang (US 20150357413) and further in view of Baraskar (US 20200388688).
Regarding Claim 16, Alsmeier, in view of Zhang, shows the memory device of claim 1, further comprising
Alsmeier, in view of Zhang, however, fails to show
a barrier layer 46a formed between the gate line and the third dielectric layer.
Baraskar (see, e.g., fig. 14c, para.0201) in a similar device to Alsmeier, in view of Zhang, that a barrier layer formed between the gate line and the third dielectric layer would promote adhesion between the gate line and the third dielectric layer.
It would have been obvious to one of ordinary skill in the art to use the barrier layer of Baraskar, in the device of Alsmeier, in view of Zhang, to promote adhesion between the gate line and the third dielectric layer.
Regarding Claim 17, Alsmeier, in view of Zhang and further in view of Baraskar (see, e.g., para.00201), shows the memory device of claim 16,
wherein the barrier layer comprises tungsten nitride (WN) or titanium nitride (TiN).
Response to Arguments
Applicant’s arguments with respect to claims 1-17, filed on 02/03/2026, have been fully considered but they are not persuasive. The prior art of record overcomes the amendments, see paragraphs 3-35 above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/F.R.D./ Examiner, Art Unit 2814
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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