DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Office acknowledges receipt on 23 October 2025 of Applicant’s amendments in which claims 1, 10, 12, 16, 18, an 20 are amended and claims 7 and 21 are cancelled. The Office withdraws the drawing objection and the section 112(a) rejections identified in the Office Communication dated 14 August 2025 in view of the amendments.
Response to Arguments
Applicant’s arguments dated 23 October 2025 with respect to claim(s) 1, 10, and 16 have been considered but are moot because the new grounds of rejection do not rely on any reference applied in the prior rejections of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claim 16 is objected to because of the following informalities:
Claim 16, line 4, recites “a upper buffer layer,” which should read “an upper buffer layer” for proper grammar.
Claim 16, line 24, recites “a upper intermediate insulating layer,” which should read “an upper intermediate insulating layer” for proper grammar.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10, lines 5 and 6, recites “the opening of the intermediate insulating layer such that the intermediate insulating layer,” which is indefinite because “the opening” and each instance of “the intermediate insulating layer” lacks a proper antecedent basis. For the purpose of compact prosecution and to better comport with the remainder of the claim, the claim will be interpreted as reciting “the first opening of the first intermediate insulating layer such that the first intermediate insulating layer.” Claims 11-15 are rejected due to their dependencies from base claim 10.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 6, 10, and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US20230005998A1) in view of Luo (US20230098341A1 ) and Huang et al. (US20200411619A1).
Regarding claim 1, Oh teaches in Fig. 10 a display apparatus comprising:
a first light-blocking pattern (BMLa) on a pixel area (A2) of a device substrate (110) {¶0207, 0229, 0230};
an upper buffer layer (BF2) on the device substrate (110), the upper buffer layer (BF2) covering the first light-blocking pattern (BMLa) {¶0225};
a driving thin film transistor (S-TFT) on the pixel area (A2) of the device substrate (110), the driving thin film transistor (S-TFT) including a driving semiconductor pattern (AC1) overlapping with the first light-blocking pattern (BMLa) {¶0237};
a first intermediate insulating layer (BR/BR2) between the device substrate (110) and the upper buffer layer (BF2) {¶0225}, and
a second intermediate insulating layer (BF1) between the first intermediate insulating layer (BR/BR2) and the upper buffer layer (BF2) {¶0226},
wherein the first intermediate insulating layer (BR/BR2) includes a first opening (opening in BR housing BMLa) overlapping with the first light-blocking pattern (BMLa) and the driving semiconductor pattern (AC1) {¶0230, 0232}.
Oh does not necessarily teach:
wherein the first opening penetrates the first intermediate insulating layer, and the first light-blocking pattern is disposed within the first opening such that the first intermediate insulating layer is non-overlapping with an upper surface of the first light-blocking pattern, and
wherein the second intermediate insulating layer includes a second opening overlapping with and wider than the first opening, and the second intermediate insulating layer is non-overlapping with the upper surface of the first light-blocking pattern.
In an analogous art, Luo teaches in Fig. 5 and paragraphs [0065, 0067]:
a first opening (portion of V1 in 221) penetrates a first intermediate insulating layer (221), and a first light-blocking pattern (211) is disposed within the first opening (portion of V1 in 221) such that the first intermediate insulating layer (221) is non-overlapping with an upper surface of the first light-blocking pattern (211), and
a second intermediate insulating layer (222) includes a second opening (portion of V1 in 222) overlapping with and wider than the first opening (portion of V1 in 221), and the second intermediate insulating layer (222) is non-overlapping with the upper surface of the first light-blocking pattern (211).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Oh’s display apparatus based on the teachings of Luo, to achieve the above-identified features, so an overall thickness of the array substrate … may not be increased. Huang ¶0077. Moreover, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Luo) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 2, Oh as modified by Luo and Huang teaches the display apparatus according to claim 1, and Oh further teaches wherein the first opening (opening in BR housing BMLa) has a size larger than the first light-blocking pattern (BMLa) and the driving semiconductor pattern (AC1) {Fig. 10}.
Regarding claim 3, Oh as modified by Luo and Huang teaches the display apparatus according to claim 1, and Oh further teaches further comprising a switching thin film transistor (O-TFT) on the upper buffer layer (BF2) of the pixel area (A2) {Fig. 10; ¶0230},
wherein the switching thin film transistor (O-TFT) includes a switching semiconductor pattern (AC2) being spaced away from the driving semiconductor pattern (AC1) {¶0244}, and
wherein the first intermediate insulating layer (BR/BR2) includes a portion overlapping with the switching semiconductor pattern (AC2) {Fig. 10}.
Regarding claim 6, Oh as modified by Luo and Huang teaches the display apparatus according to claim 5, and Oh further teaches further comprising a separation insulating layer (BR1) between the device substrate (110) and the second light-blocking pattern (BMLb) {Fig. 10; ¶0210},
wherein the separation insulating layer (BR1) extends to be disposed between the device substrate (110) and the first light-blocking pattern (BMLa) {Fig. 10; ¶0210}.
Regarding claim 10, as interpreted in view of the indefiniteness rejection, Oh teaches in Fig. 10 a display apparatus comprising:
a first intermediate insulating layer (BR/BR2) on a device substrate (110) {Fig. 10; ¶0209, 0210};
a first light-blocking pattern (BMLa) {Fig. 10; ¶0230};
a second intermediate insulating layer (BF1) on the first intermediate insulating layer (BR/BR2) {¶0226};
an upper buffer layer (BF2) on the first intermediate insulating layer (BR/BR2) and the second intermediate insulating layer (BF1) and the first light-blocking pattern (BMLa) {Fig. 10; ¶0226};
a driving thin film transistor (S-TFT) on the upper buffer layer (BF2), the driving thin film transistor (S-TFT) including a driving semiconductor pattern (AC1) overlapping with the first light-blocking pattern (BMLa) {Fig. 10; ¶0230, 0237};
a first switching thin film transistor (O-TFT) on the upper buffer layer (BF2), the first switching thin film transistor (O-TFT) including a first switching semiconductor pattern (AC2) being spaced away from the opening (opening in BR housing BMLa) {Fig. 10; ¶0230, 0244};
an over-coat layer (80) on the first switching thin film transistor (O-TFT) and the driving thin film transistor (S-TFT) {Fig. 10; ¶0254}; and
a light-emitting device (LD2) on the over-coat layer (80), the light-emitting device (LD2) being electrically connected to the driving thin film transistor (S-TFT) {Fig. 10; ¶0265}.
Oh does not necessarily teach:
the first intermediate insulating layer including a first opening penetrating the first intermediate insulating layer;
the first light-blocking pattern disposed within the first opening of the first intermediate insulating layer such that the first intermediate insulating layer is non-overlapping with an upper surface of the first light-blocking pattern;
the second intermediate insulating layer including a second opening overlapping with and wider than the first opening, the second intermediate insulating layer being non-overlapping with the upper surface of the first light-blocking pattern.
Luo teaches in Fig. 5 and paragraphs [0065, 0067]:
a first intermediate insulating layer (221) including a first opening (portion of V1 in 221) penetrating the first intermediate insulating layer (221);
a first light-blocking pattern (211) disposed within the first opening (portion of V1 in 221) of the first intermediate insulating layer (221) such that the first intermediate insulating layer (221) is non-overlapping with an upper surface of the first light-blocking pattern (211),
a second intermediate insulating layer (222) including a second opening (portion of V1 in 222) overlapping with and wider than the first opening (portion of V1 in 221), the second intermediate insulating layer (222) being non-overlapping with the upper surface of the first light-blocking pattern (211).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Oh’s display apparatus based on the teachings of Luo, to achieve the above-identified features, so an overall thickness of the array substrate … may not be increased. Huang ¶0077. Moreover, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Luo) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 27, Oh as modified by Luo and Huang teaches the display apparatus according to claim 1, but Oh does not teach wherein the first opening penetrates an entire thickness of the first intermediate insulating layer.
Luo teaches in Fig. 5 and paragraph [0065] a first opening (V1) penetrates an entire thickness of a first intermediate insulating layer (221). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Oh’s display apparatus as modified by Luo and Huang based on the teachings of Luo – such that the first opening penetrates an entire thickness of the first intermediate insulating layer – so an overall thickness of the array substrate … may not be increased. Huang ¶0077.
Claim(s) 4 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh in view of Luo and Huang as applied to claim 3 (for claim 4) and 10 (for claim 11) above, and further in view of Lee et al. (US20220406860A1).
Regarding claim 4, Oh as modified by Luo and Huang teaches the display apparatus according to claim 3, but Oh does not teach wherein the switching semiconductor pattern includes a same material as the driving semiconductor pattern.
In an analogous art, Lee ‘860 teaches in Fig. 4 and paragraph [0081] the switching semiconductor pattern includes a same material (e.g., oxide semiconductor) as the driving semiconductor pattern. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Oh’s display apparatus as modified by Luo and Huang based on the teachings of Lee ‘860 – such that Oh’s switching semiconductor pattern includes a same material as the driving semiconductor pattern, as taught by Lee – because [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 11, Oh as modified by Luo and Huang teaches the display apparatus according to claim 10, but Oh does not teach wherein the driving semiconductor pattern and the first switching semiconductor pattern include an oxide semiconductor.
Lee ‘860 teaches in Fig. 4 and paragraph [0081] the driving semiconductor pattern and the first switching semiconductor pattern includes an oxide semiconductor. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Oh’s display apparatus as modified by Luo and Huang based on the teachings of Lee ‘860 – such that Oh’s the driving semiconductor pattern and Oh’s first switching semiconductor pattern include an oxide semiconductor, as taught by Lee – because [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh in view of Luo and Huang as applied to claim 3 above, and further in view of Wang et al. (US20200083309A1).
Regarding claim 5, Oh as modified by Luo and Huang teaches the display apparatus according to claim 3, but Oh does not teach further comprising a second light-blocking pattern between the device substrate and the first intermediate insulating layer, the second light-blocking pattern overlapping with the switching semiconductor pattern.
Wang teaches in Fig. 2A and paragraph [0071] a second light-blocking pattern (130a) between the device substrate (110) and the first intermediate insulating layer (11), the second light-blocking pattern (130a) overlapping with the switching semiconductor pattern (31). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Oh’s display apparatus as modified by Luo and Huang based on the teachings of Wang – such that a second light-blocking pattern is disposed between the device substrate and the first intermediate insulating layer, the second light-blocking pattern overlapping with the switching semiconductor pattern – so the first and second light-blocking patterns, which reduce voltage variations of the respective TFTs by reducing the outside light that impinges on the TFTs {Wang ¶0067}, may be formed at the same time of the same material and thereby reduce manufacturing operations. Wang ¶0071.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh in view of Luo and Huang as applied to claim 1 above, and further in view of Bae et al. (US20200111855A1).
Regarding claim 8, Oh as modified by Luo and Huang teaches the display apparatus according to claim 1, but Oh does not teach wherein a driving source electrode of the driving thin film transistor is electrically connected to the first light-blocking pattern.
In an analogous art, Bae teaches in Fig. 6 and paragraph [0068] a driving source electrode (133b) of the driving thin film transistor (133b, 134b, 135b, 155b) is electrically connected to the first light-blocking pattern (160). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Oh’s display apparatus as modified by Luo and Huang based on the teachings of Bae – such that a driving source electrode of the driving thin film transistor is electrically connected to the first light-blocking pattern – so the first light-blocking pattern is not floated … [and] thereby preventing deterioration of the display quality due to the unnecessary parasitic capacitance. Bae ¶0068.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh in view of Luo and Huang as applied to claim 1 above, and further in view of Kwon et al. (US20140183476A1), Murashige et al. (US20190081081A1), and Jeon et al. (US20210320162A1).
Regarding claim 9, Oh as modified by Luo and Huang teaches the display apparatus according to claim 1, but Oh does not teach wherein a capacitance of a first parasitic capacitor between the first light-blocking pattern and the driving semiconductor pattern is larger than a capacitance of a second parasitic capacitor between the driving semiconductor pattern and a driving gate electrode of the driving thin film transistor.
Oh teaches the first light-blocking pattern and the driving semiconductor pattern defined by the claim, but does not expressly teach the existence of the parasitic capacitance existing with the claimed arrangement of these components. In an analogous art, Kwon teaches in paragraph [0006] the existence of high parasitic capacitance between a semiconductor pattern and a gate electrode of a thin film transistor and teaches in paragraph [0009] the problems such high parasitic capacitance causes with a TFT. Murashige teaches in Fig. 9 and paragraph [0084] the existence of a parasitic capacitance between a light-shielding layer (201) and a semiconductor body of a thin film transistor (300) that are spaced apart as with the claimed arrangement of these components. Moreover, the use of the word “parasitic” to describe the recited capacitances indicates these capacitances are implicit to the arrangement both claimed in the instant application and taught by Oh. Regardless of whether the parasitic capacitances are deemed implicit to Oh’s disclosed arrangement or taught by Kwon and Murashige, Jeon teaches in paragraph [0093] that capacitance is proportional to a dielectric constant of a material between conductors forming the conductance and inversely proportional to the distance between the conductors. Accordingly, before the effective filing date of the claimed invention a person of ordinary skill in the art would be motivated to discover the optimum or workable ranges of capacitance by routine experimentation such that a capacitance of a first parasitic capacitor between the first light-blocking pattern and the driving semiconductor pattern is larger than a capacitance of a second parasitic capacitor between the driving semiconductor pattern and a driving gate electrode of the driving thin film transistor. [W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. MPEP ¶2144.05(II).
Claim(s) 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh in view of Luo and Huang as applied to claim 10 above, and further in view of Kim et al. (US20220140059A1).
Regarding claim 12, Oh as modified by Luo and Huang teaches the display apparatus according to claim 10, but Oh does not teach further comprising:
a second switching thin film transistor between the device substrate and the over-coat layer, the second switching thin film transistor including a second switching semiconductor pattern and a gate electrode overlapping with a portion of the second switching semiconductor pattern; and
a gate insulating layer extending between the second switching semiconductor pattern and the gate electrode.
In an analogous art, Kim teaches in Fig. 15 a second switching thin film transistor (STR2 in STRR2) between the device substrate (110) and the over-coat layer (165), the second switching thin film transistor (STR2 in STRR2) including a second switching semiconductor pattern (151) and a gate electrode (132) overlapping with a portion of the second switching semiconductor pattern (151) {¶0131}; and a gate insulating layer (162) extending between the second switching semiconductor pattern (151) and the gate electrode (132) {¶0130}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Oh’s display apparatus as modified by Luo and Huang based on the teachings of Kim – such that a second switching thin film transistor is disposed between the device substrate and the over-coat layer, the second switching thin film transistor including a second switching semiconductor pattern and a gate electrode overlapping with a portion of the second switching semiconductor pattern; and a gate insulating layer is extending between the second switching semiconductor pattern and the gate electrode – to electrically connect a reference voltage line … to the source electrode of the driving transistor. Kim ¶0105.
Regarding claim 13, Oh as modified by Luo, Huang, and Kim teaches the display apparatus according to claim 12, but Oh does not teach wherein the second switching semiconductor pattern includes a material different from the driving semiconductor pattern and the first switching semiconductor pattern.
Kim teaches in paragraph [0108] the second switching semiconductor pattern (151) includes a material different from the driving semiconductor pattern (153) and the first switching semiconductor pattern (STR1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Oh’s display apparatus as modified by Luo, Huang, and Kim based on the further teachings of Kim – such that the second switching semiconductor pattern includes a material different from the driving semiconductor pattern and the first switching semiconductor pattern – because all the claimed elements (e.g., first and second switching semiconductor patterns) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Kim), with no change in their respective functions (e.g., of operating as a transistor), to yield nothing more than predictable results. MPEP ¶2143(I)(A).
Claim(s) 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh in view of Luo, Huang, and Kim as applied to claim 12 above, and further in view of Wang.
Regarding claim 14, Oh as modified by Luo, Huang, and Kim teaches the display apparatus according to claim 12, and Oh further teaches further comprising a second light-blocking pattern (BMLb) being spaced away from the first light-blocking pattern (BMLa), the second light-blocking pattern (BMLb) overlapping with the first switching semiconductor pattern (AC2) {Fig. 10; ¶0230}.
Oh does not teach wherein the second light-blocking pattern is disposed on a same layer as the gate electrode of the second switching thin film transistor.
Wang teaches in Fig. 2C and paragraph [0080] a second light-blocking pattern (130c) is disposed on a same layer (12) as a gate electrode (22) of a thin film transistor. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Oh’s display apparatus as modified by Luo, Huang, and Kim based on the teachings of Wang – such that the second light-blocking pattern is disposed on a same layer as the gate electrode of the second switching thin film transistor – so the second light-blocking pattern and the gate electrode of the second switching thin film transistor may be formed together of the same material on the same layer and thereby reduce manufacturing operations. Wang ¶0080, 0081.
Regarding claim 15, Oh as modified by Luo, Huang, Kim, and Wang teaches the display apparatus according to claim 14, but Oh does not teach wherein the second light-blocking pattern includes a same material as the gate electrode of the second switching thin film transistor.
Wang teaches in Fig. 2C and paragraph [0080] a second light-blocking pattern (130c) includes a same material as a gate electrode (22) of a thin film transistor. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Oh’s display apparatus as modified by Luo, Huang, Kim, and Wang based on the further teachings of Wang – such that the second light-blocking pattern includes a same material as the gate electrode of the second switching thin film transistor – so the second light-blocking pattern and the gate electrode of the second switching thin film transistor may be formed together of the same material and thereby reduce manufacturing operations. Wang ¶0080, 0081.
Claim(s) 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Lee et al. (US20170338252A1), Chung et al. (US20130175534A1), Luo, and Huang.
Regarding claim 16, Wang teaches in Fig. 2A, 2B, or 2C a display apparatus comprising:
a first light-blocking pattern (120) and a second light-blocking pattern (130a/130b/130c) disposed on a device substrate (110) {¶0066};
a first thin-film transistor (M1), the first thin-film transistor (M1) including a first semiconductor pattern (21) overlapping with the first light-blocking pattern (120), the first semiconductor pattern (21) electrically connected to a light-emitting device (not shown) {¶0065, 0077};
a second thin-film transistor (M2), the second thin-film transistor (M2) including a second semiconductor pattern (31) overlapping with the second light-blocking pattern (130a/130b/130c) {¶0065}; and
wherein a distance between the first light-blocking pattern (120) and the first semiconductor pattern (21) is shorter than a distance between the second light-blocking pattern (130a/130b/130c) and the second semiconductor pattern (31) {Figs. 2A-2C}.
Wang does not teach:
a[n] upper buffer layer disposed on the first light-blocking pattern and the second light-blocking pattern;
the first thin-film transistor on the upper buffer layer; and
the second thin-film transistor on the upper buffer layer;
Lee teaches in Fig. 10 and paragraphs [0049] and [0066] a[n] upper buffer layer (12) disposed on a first light-blocking pattern (113) and a second light-blocking pattern (111), and first and second thin-film transistors (transistors of 193-195; 13a} disposed on the upper buffer layer (12). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wang’s display apparatus based on the teachings of Lee – such that a[n] upper buffer layer is disposed on the first light-blocking pattern and the second light-blocking pattern, the first thin-film transistor is disposed on the upper buffer layer, and the second thin-film transistor is disposed on the upper buffer layer – to prevent the introduction of impurity ions (such as alkali metal ions) … to the active layer [of a transistor]. Chung ¶0054.
Wang as modified by Lee above does not teach the first semiconductor pattern of the first thin-film transistor includes oxide semiconductor.
However, Lee further teaches in Fig. 4 and paragraph [0066] the first semiconductor pattern (193-195) of the first thin-film transistor (transistor of 193-195) includes oxide semiconductor. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wang’s display apparatus as modified by Lee and Chung based on the further teachings of Lee – such that Wang’s first semiconductor pattern of the first thin-film transistor includes oxide semiconductor, as taught by Lee – because [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Wang as modified by Lee above does not teach:
two intermediate insulating layers between the second light-blocking pattern and the second thin-film transistor, the two intermediate insulating layers not between the first light-blocking pattern and the first thin-film transistor;
wherein each of the two intermediate insulating layers has an opening penetrating a corresponding intermediate insulating layer, and the first light-blocking pattern disposed within the opening of a lower intermediate insulating layer among the two intermediate insulating layers,
wherein the opening of a upper intermediate insulating layer among the two intermediate insulating layers is overlapping with and wider than the opening of the lower intermediate insulating layer, and
wherein the two intermediate insulating layers are not overlapping with an upper surface of the first light-blocking pattern.
Luo teaches in Fig. 5 and paragraphs [0053, 0065]:
two intermediate insulating layers (221, 222) between a second light-blocking pattern (212) and a second thin-film transistor (24), the two intermediate insulating layers (221, 222) not between a first light-blocking pattern (211) and a first thin-film transistor (23),
wherein each of the two intermediate insulating layers (221, 222) has an opening (V1) penetrating a corresponding intermediate insulating layer (221, 222), and the first light-blocking pattern (211) is disposed within the opening (portion of V1 in 221) of a lower intermediate insulating layer (221) among the two intermediate insulating layers (221, 222),
wherein the opening (portion of V1 in 222) of a[n] upper intermediate insulating layer (222) among the two intermediate insulating layers (221, 222) is overlapping with and wider than the opening (portion of V1 in 221) of the lower intermediate insulating layer (221), and wherein the two intermediate insulating layers (221, 222) are not overlapping with an upper surface of the first light-blocking pattern (211).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Oh’s display apparatus as modified by Lee and Chung based on the teachings of Luo, as identified above, so an overall thickness of the array substrate … may not be increased. Huang ¶0077. Moreover, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Luo) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 17, Wang as modified by Lee, Chung, Luo, and Huang teaches the display apparatus of claim 16, and Wang further teaches wherein the first thin-film transistor (M1) is a driving transistor for driving the light-emitting device and the second thin-film transistor (M2) is a switching transistor {¶0023, 0024, 0063}.
Regarding claim 18, Wang as modified by Lee, Chung, Luo, and Huang teaches the display apparatus of claim 16, and Wang further teaches the second semiconductor pattern (31) includes oxide semiconductor {¶0074}.
Wang does not teach the first semiconductor pattern and the second semiconductor pattern are disposed on the upper buffer layer.
As discussed above with respect to base claim 16, Lee teaches in Fig. 10 and paragraphs [0049] and [0066] a first semiconductor pattern (193-195) and the second semiconductor pattern (131-133) are disposed on an upper buffer layer (12). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wang’s display apparatus as modified by Lee, Chung, Luo, and Huang based on the further teachings of Lee – such that the first semiconductor pattern and the second semiconductor pattern are disposed on the upper buffer layer – to prevent the introduction of impurity ions (such as alkali metal ions) … to the active layer [of a transistor]. Chung ¶0054.
Regarding claim 19, Wang as modified by Lee, Chung, Luo, and Huang teaches the display apparatus of claim 16, and Wang further teaches wherein the first semiconductor pattern (21) is overlapped with the opening (opening below mesa portion of 12) {e.g., Fig. 2A}.
Regarding claim 20, Wang as modified by Lee, Chung, Luo, and Huang teaches the display apparatus of claim 16, and Wang further teaches in Figs. 2A-2C wherein a side surface (e.g., side surface that directly interfaces with 120/130 or upper surface) of the two intermediate insulating layers (modified 11) is located between the first light-blocking pattern (120) and the second light-blocking pattern (130c).
Claim(s) 22-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Lee, Chung, Luo, and Huang as applied to claim 16 above, and further in view of Kim and Kwon.
Regarding claim 22, Wang as modified by Lee, Chung, Luo, and Huang teaches the display apparatus of claim 16, but Wang does not teach further comprising a third thin-film transistor on the device substrate, the third thin-film transistor including a third semiconductor pattern including poly-Si.
Kim teaches in Fig. 15 a third thin-film transistor (STR2 in STRR2) on the device substrate (110), the third thin-film transistor (STR2 in STRR2) including a third semiconductor pattern (151). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wang’s display apparatus as modified by Lee, Chung, Luo, and Huang based on the teachings of Kim – such that a third thin-film transistor is disposed on the device substrate, the third thin-film transistor including a third semiconductor pattern – to electrically connect a reference voltage line … to the source electrode of the driving transistor. Kim ¶0105.
Kim teaches in paragraph [0108] the third semiconductor pattern may be an oxide semiconductor. In an analogous art, Kwon teaches in paragraph [0007] that oxide semiconductor and polysilicon are alternative materials for a thin film transistor. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wang’s display apparatus as modified by Lee, Chung, Luo, Huang, and Kim based on the teachings of Kwon – such that the third semiconductor pattern of the third thin-film transistor includes poly-Si – because [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 23, Wang as modified by Lee, Chung, Luo, Huang, Kim, and Kwon teaches the display apparatus of claim 22, and Wang further teaches further comprising a separation insulating layer on the third thin-film transistor, and wherein the first light-blocking pattern (120) and the second light-blocking pattern (130a/130b/130c) are disposed on the separation insulating layer (10).
But Wang does not teach a separation insulating layer on the third thin-film transistor.
Kim teaches in Fig. 5 and paragraph [0156] a separation insulating layer (164) on a third thin-film transistor (STR2 in STRR2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wang’s display apparatus as modified by Lee, Chung, Luo, Huang, Kim, and Kwon based on the further teachings of Kim – such that a separation insulating layer is disposed on the third thin-film transistor – to protect and insulate the underlying material. Kim ¶0156.
Regarding claim 24, Wang as modified by Lee, Chung, Luo, Huang, Kim, and Kwon teaches the display apparatus of claim 22, and Wang further teaches wherein the first light-blocking pattern (120) and the second light-blocking pattern (130a/130b/130c) are disposed on an insulating layer (10) {Figs. 2A-2C; ¶0069, 0138}.
Wang does not teach the third thin-film transistor further includes a gate electrode and at least a portion of a lower gate insulating layer.
Kim teaches in Fig. 5 and paragraph [0131] a third thin-film transistor (STR2 in STRR2) further includes a gate electrode (131) and at least a portion of a lower gate insulating layer (162). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wang’s display apparatus as modified by Lee, Chung, Luo, Huang, Kim, and Kwon based on the further teachings of Kim – such that the third thin-film transistor further includes a gate electrode and at least a portion of a lower gate insulating layer – to provide a capacitance-based control for enabling/disabling a conductive channel in the third thin film transistor using a conductive gate electrode and a dielectric gate insulating layer. Moreover, [t]he selection of a known material [e.g., gate and gate insulating layer] based on its suitability for its intended use [in a thin film transistor is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Lee, Chung, Luo, Huang, Kim, and Kwon as applied to claim 22 above, and further in view of Yeo (US20180182838A1).
Regarding claim 25, Wang as modified by Lee, Chung, Luo, Huang, Kim, and Kwon teaches the display apparatus of claim 22, and Wang further teaches wherein the first thin-film transistor (M1) and the second thin-film transistor (M2) are disposed in a pixel area (area of PX1) {¶0063}.
Wang does not teach the third thin-film transistor is disposed in a bezel area.
Yeo teaches paragraph [0091] a thin-film transistor is disposed in a non-display area and teaches in Fig. 1 and paragraphs [0028] and [0037] the non-display area is located in a bezel area of the display apparatus. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wang’s display apparatus as modified by Lee, Chung, Luo, Huang, Kim, and Kwon based on the teachings of Yeo – such that the third thin-film transistor is disposed in a bezel area – so as to remove a component, producing a signal shared by multiple devices within a display area, to a non-display area and thereby create more space for the components better suited for disposal within the display area.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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