DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/09/2025 has been entered.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “one first reference line” in the first line of the amendment to the claims. There is insufficient antecedent basis for this limitation in the claim. Claims 1 recites the limitation “a first reference line” in the 3rd line of the claim so it is unclear if the “one first reference line” is the is the same as the recited “a first reference line” or some other reference line. For purposes of examination, Examiner has interpreted the limitation of “one first reference line” recited in the first line of the claim amendment as “the first reference line”.
Claim 1 recites the limitation "one power line" in the first line of the amendment to the claims. There is insufficient antecedent basis for this limitation in the claim. It is unclear if the “one power line” is the same as the recited “a power line” or some other power line. For purposes of examination Examiner has interpreted the limitation of “one power line” as “the power line”.
Claim 1 recites the limitation "each subpixel column including subpixels" in the first line of the amendment to the claim. There is insufficient antecedent basis for this limitation in the claim. Claim 1 recites the limitation “a subpixel” in the sixth line of the claim but does not recite a limitation of “a subpixel column” nor does it recite the limitation of more than one subpixel, so it is unclear what the limitation of “each subpixel column including subpixels” references. For purposes of examination Examiner has interpreted “each subpixel column including subpixels” as “a subpixel column including a subpixel””.
Claim 1 recites the limitation "two reference lines" in the second line of the claim amendment. There is insufficient antecedent basis for this limitation in the claim. Claim 1 recites the limitation of “a first reference line” and “a second reference line”. It is unclear, therefore, if the limitation of “two reference lines” refers to two first reference lines, two second reference lines, one of each of a first reference line and second reference line or a different reference line altogether. For purposes of examination, Examiner has interpreted “two reference lines” as “the first reference line and the second reference line”.
Claim 1 recites the limitation "two power lines" in the last line of the amended claims. There is insufficient antecedent basis for this limitation in the claim. Only “a power line” is recited in the 7th line of claim 1 so “two power lines” is unclear. For purposes of examination Examiner has interpreted the limitation of “two power lines” as “the first power line and a second power line”.
Claim 12 recites the limitation “one first reference line” in the first line of the amended to the claim. There is insufficient antecedent basis for this limitation in the claim. Claim 12 recites the limitation “a lower reference line” in the third line of the claim and “an upper reference line” in the 6th line of the claim and ‘an upper reference line” in 6th line of the claim, but claim 12 fails to recite the limitation of “a first reference line” Therefore it is unclear if “one first reference line” refers to “an upper reference line” or “a lower reference line” or a different reference line. For purposes of examination, Examiner has interpreted the limitation “one first reference line” as “the upper reference line”.
Claim 12 recites the limitation "one power line" in the first line of the amendment to the claims. There is insufficient antecedent basis for this limitation in the claim. Claim 12 recites the limitation “a power line” in the ninth line of the claim. It is unclear if the “one power line” is the same as the recited “a power line” or some other power line. For purposes of examination Examiner has interpreted the limitation of “one power line” as “the power line”.
Claim 12 recites the limitation “each subpixel column including subpixels”. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination Examiner interpreted the limitation “each subpixel column including subpixels” as “a subpixel column including a subpixel”.
Claim 12 recites the limitation "two reference lines" in the second line of the claim amendment. There is insufficient antecedent basis for this limitation in the claim. Claim 12 recites the limitation of “a lower reference line” and “an upper reference line”. It is unclear, therefore, if the limitation of “two reference lines” refers to the a lower reference line, the an upper reference line, one of each of a lower reference line and an upper reference line or a different reference line altogether. For purposes of examination, Examiner has interpreted “two reference lines” as “the lower reference line and the upper reference line”.
Claim 12 recite the limitation "two power lines" in the last line of the amended claims. There is insufficient antecedent basis for this limitation in the claim. Only “a power line” is recited in the 9th line of claim 12 so the limitation of “two power lines” is unclear. For purposes of examination Examiner has interpreted the limitation of “two power lines” as “the power line and a second power line”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a) the invention was known or used by others in this country, or patented or described in a printed publication in this or a foreign country, before the invention thereof by the applicant for a patent.
Claims 1-4, 6-7 and 11-13 and 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. (US 2021/0098749 A1, hereinafter Choi ‘749).
With respect to Claim 1 Choi ‘749 discloses a light emitting display apparatus (Fig 1-5) comprising:
a display panel (display apparatus, Fig 1, Para [0056]) including a display area (DA, Fig 1, Para [0057]) and a non-display area (NDA, Fig 1, Para [0057]);
a first reference line (RL, Fig 3, Para [0076]) arranged in a first direction (DR2, Fig 3, Para [0076]) in the display area (DA)(Para [0075] discloses Fig. 3 is part of pixel circuit PC, which is shown to be part of display apparatus via Fig 2 and Fig 1);
a second reference line (URL, Fig 3, Para [0078]) arranged in a second direction (DR1, Fig 3, Para [0079]) transverse the first direction (DR2, orientation of DR1/DR2 shown in Fig 3) in the display area (DA) and electrically connected to the first reference line (RL)(Fig 3 and Para [0090] disclose RL and URL connected via a contact hole);
a transistor (T1, Fig 3, Para [0080]) included in a subpixel (PC, Fig 3, Para [0080]) of the display panel (display apparatus); and
a power line (PL1, Fig 3, Para [0073]) arranged in the first direction (DR2, Fig 3) in the display area (DA),
wherein the second reference line (URL) is disposed on a same layer as a semiconductor layer (A1, Fig 5, Para [0081]) of the transistor (T1)(Fig 5 shows URL disposed on layers 111/112/113 and A1 disposed on layers 111/112, therefore URL is disposed on same layers 111 and 112 as A1), and
wherein one first reference line (RL)(note Examiners’ above interpretation of “one first reference line” as “the first reference line”) or one power line (PL1)(Note Examiner’s above interpretation of “one power line” as “the power line”) is arranged in each subpixel column including subpixels (note Examiner’s above interpretation of the limitation “each subpixel column including subpixels” as “a subpixel column including a subpixel”) (Para [0075] discloses Fig 3 as schematic of pixel circuit PC; each pixel PC contains one subpixel as disclosed in Fig 1 and 4; pixels are arranged in a column as disclosed in Fig 1) at a same position (Fig 4 discloses RL on layer 115 and Fig 5 discloses PL1 on layer 115) in the second direction (DR2), and two reference lines (RL and URL)(Note Examiner’s above interpretation of “two reference lines” as “the first reference line and the second reference line”) are arranged between two power lines (PL1 ) and (PL2, Fig 2, Para [0073]))(note Examiner’s above interpretation of “two power lines” as “the power line and a second power line”)(Fig 3 discloses that RL and URL are arranged between power lines PL1 and PL2).
With respect to Claim 2 Choi ‘749 discloses all limitations of the light emitting display apparatus of claim 1, and Choi ‘749 further discloses wherein at least one of the first reference line (RL) and the second reference line (URL) is disposed on a layer which differs from the power line (PL1)(Fig 5 discloses URL on a layer below PL1).
With respect to Claim 3 Choi ‘749 discloses all limitations of the light emitting display apparatus of claim 1, and Choi ‘749 further discloses wherein the second reference line (URL) is disposed on a layer (Fig 5 discloses URL on a layer below PL1 and RL) which differs from the first reference line (RL) and the power line (PL1).
With respect to Claim 4 Choi ‘749 discloses all limitations of the light emitting display apparatus of claim 1, and Choi ‘479 further discloses wherein the first reference line (RL) and the power line (PL1) are disposed in a source drain metal layer (metal layer of S1/D1 and S3/D3 as shown in Fig 5, disclosed in Para [0066 and 0068] disclose S1/D1 and S3/D3 as source drain electrodes)(Fig 5 discloses PL1 and RL on the same layer as S1/D1 and S3/D3), the source drain metal layer (metal layer of S1/D1 and S3/D3) being in the transistor (T1)(Fig 5 and Para [0066] disclose S1/D1 as part of transistor T1).
With respect to Claim 6 Choi ‘749 discloses all limitations of the light emitting display apparatus of claim 4, and Choi ‘749 further discloses wherein the first reference line (RL) and the power line (PL1) are disposed between an interlayer insulation layer (115, Fig 5, Para [0149] discloses RL and PL1 on layer 115) and a planarization layer (117, Fig 5, Para [0126]) disposed on a layer (115, Fig 5, Para [0149] discloses RL and Pl1 on layer 115) which is higher than the second reference line (URL)(Fig 5 discloses URL on layer 113 and RL and PL1 on layer 115 which is higher than layer 113).
With respect to Claim 7 Choi ‘749 discloses all limitations of the light emitting display apparatus of claim 1, and Choi ‘749 further discloses wherein the second reference line (URL) is disposed between a buffer layer (115, Fig 5, Para [0091]) and a gate insulation layer (113, Fig 5, Para [0119]) disposed on a layer (112, Fig 5, Para [0092]) which is lower than the first reference line (RL) and the power line (PL1)(Fig 5 discloses URL between 115 and 113 and that 113 is on layer 112 which is lower than RL and PL1).
With respect to Claim 11 Choi ‘749 discloses all limitations of the light emitting display apparatus of claim 1, wherein the power line (PL1) is disposed to have a mesh shape in the display area (DA)(Para [0094] discloses the power lines disposed in a mesh structure).
With respect to Claim 12 Choi ‘579 discloses a light emitting display apparatus (Fig 1-5) comprising:
a buffer layer (111, Fig 5, Para [0092]) disposed on a substrate (100, Fig 1, Para [0097]);
a lower reference line (URL, Fig 3, Para [0078]) disposed on the buffer layer (111)(Fig 5 discloses URL disposed on 111), the lower reference line (URL) being arranged in a horizontal direction (DR1, Fig 3, Para [0075]) in a display area (DA)(Para [0075] discloses Fig. 3 is part of pixel circuit PC, which is shown to be part of display apparatus via Fig 2 and Fig 1) of the substrate (100);
at least one insulation layer (115, Fig 5, Para [0083]) disposed on the lower reference line (URL)(Fig 5 discloses 115 disposed on URL);
an upper reference line (RL, Fig 3, Para [0076]) disposed on the at least one insulation layer (115)(Fig 5 discloses RL disposed on 115), arranged in a vertical direction (DR2, Fig 3, Para [0076]) in the display area (DA) of the substrate (100), and electrically connected (Fig 3 and Para [0090] disclose RL and URL connected via a contact hole) to the lower reference line (URL); and
a power line (PL1, Fig 3, Para [0066]) disposed on the at least one insulation layer (115)(Fig 5 discloses PL1 disposed on 115) and arranged in the vertical direction (DR2, disclosed in Fig 3) in the display area (DA) of the substrate (100),
wherein the lower reference line (URL) is disposed on a same layer (Fig 5 shows URL disposed on layers 111/112/113 and A1 disposed on layers 111/112, therefore URL is disposed on same layers 111 and 112 as A1) as a semiconductor layer (A1, Fig 5, Para [0081]) of a transistor (T1 , Fig 3, Para [0080]) between the buffer layer (111) and at least one insulation layer (115) (Fig 5 shows URL and T1 between layer 111 and layer 115) and
wherein one first reference line (RL) (Note Examiner’s above interpretation of the limitation “one first reference line” as “the upper reference line”) or one power line (PL1)(Note Examiner’s above interpretation of “one power line” as “the power line”) is arranged in each subpixel column including subpixels (note Examiner’s above interpretation of the limitation “each subpixel column including subpixels” as “a subpixel column including a subpixel”) (Para [0075] discloses Fig 3 as schematic of pixel circuit PC; each pixel PC contains one subpixel as disclosed in Fig 1 and 4; pixels are arranged in a column as disclosed in Fig 1) at a same position (Fig 4 discloses RL on layer 115 and Fig 5 discloses PL1 on layer 115) in the second direction (DR2), and two reference lines (RL and URL)(Note Examiner’s above interpretation of “two reference lines” as “the upper reference line and the lower reference line”) are arranged between two power lines (PL1 ) and (PL2, Fig 2, Para [0073])(note Examiner’s above interpretation of “two power lines” as “the power line and a second power line”)(Fig 3 discloses that RL and URL are arranged between power lines PL1 and PL2).
With respect to Claim 13 Choi ‘749 discloses all limitations of the light emitting display apparatus of claim 12, wherein the upper reference line (RL) and the power line (PL1) are disposed apart from each other (Fig 5 discloses RL and PL1 disposed apart from each other) on the at least one insulation layer (115) and each is disposed in a source drain metal layer (metal layer of S1/D1 and S3/D3 as shown in Fig 5, disclosed in Para [0066 and 0068] disclose S1/D1 and S3/D3 as source drain electrodes)(Fig 5 discloses PL1 and RL on the same layer as S1/D1 and S3/D3).
With respect to Claim 15 Choi ‘749 discloses all limitations of the light emitting display apparatus of claim 1, and Choi ‘749 further discloses wherein the second reference line (URL) includes the semiconductor layer (Para [0078] discloses URL disclosed on semiconductor layer, therefore URL would “include” the semiconductor layer).
With respect to Claim 16 Choi ‘749 discloses all limitations of the light emitting display apparatus of claim 1, wherein the second reference line (URL) including the semiconductor layer (Para [0078] discloses URL disclosed on semiconductor layer, therefore URL would “include” the semiconductor layer) is disposed in the display area (DA)(Fig 3 discloses URL in PC and Para [0075] discloses Fig. 3 is part of pixel circuit PC, which is shown to be part of display apparatus via Fig 2 and Fig 1).
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Choi ‘749 in view of Jo et al. (US 2021/0057506 A1, hereinafter Jo ‘506), in view of the following arguments.
With respect to Claim 8 Choi ‘749 discloses all limitations of the light emitting display apparatus of claim 1, and Choi ‘749 further discloses wherein the power line (PL1) comprises a lower level power line (UPL1, Fig 5, Para [0094]), and
But Choi ‘749 fails to explicitly disclose wherein a power level of the lower level power line is lower than a selected power level.
Nevertheless, in a related endeavor (Fig 1-10 of Jo ‘506) Jo ‘506 teaches wherein the power line (PL) comprises a lower level power line (vertical portion of PL in via O3, Fig 4, Para [0098]), and wherein a power level (ELVDD, Fig 2, Para [0060] discloses PL may have a high-level or a low-level low voltage, so there exists an embodiment where the lower level power line (vertical portion of PL in via O3) operates at the low-level low voltage) of the lower level power line (vertical portion of PL in via O3) is lower than a selected power level (high-level voltage of ELVDD as disclosed in Para [0060]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Jo 506’s teaching that a power level of the lower level power line is lower than a selected power level into Choi ‘749’s apparatus. The ordinary artisan would have been motivated to modify Choi ‘749 in the manner set forth above, at least, because, as Jo ‘506 teaches in Para [0026] this voltage difference enables and improvement in data voltage writing efficiency.
As incorporated, the power level of the lower level power line is lower than a selected power level of Jo ‘506 would be used as the power levels for PL1 and UPL1 of Choi ‘749.
With respect to Claim 9 Choi ‘749 as modified by Jo ‘506 discloses all limitations of the light emitting display apparatus of claim 8, and Choi ‘749 further discloses another power line (PL2, Fig 3, Para [0076]).
But Choi ‘749 fails to explicitly disclose whose power level (ELVDD) is higher than the selected power level
Nevertheless Jo ‘506 further discloses further comprising another power line (PL)(Fig 10 and Para [0101] discloses multiple PL), whose power level (ELVDD) is higher than the selected power level (Para [0060] discloses PL may have a high-level or a low-level low voltage, so there exists an embodiment where a line PL is operating at the high-level voltage and a different line PL is operating at the low-level voltage).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Jo 506’s further teaching of another power line, whose power level is higher than the selected power level into Choi ‘749’s apparatus. The ordinary artisan would have been motivated to modify Choi ‘749 in the manner set forth above, at least, because, as Jo ‘506 teaches in Para [0026] this voltage difference enables and improvement in data voltage writing efficiency.
As incorporated, the another power line, whose power level is higher than the selected power level of Jo ‘506 would be used as the power levels for PL1 and PL2 of Choi ‘749.
With respect to Claim 10 Choi ‘749 discloses all limitations of the light emitting display apparatus of claim 1, but Choi ‘749 fails to explicitly disclose wherein the first reference line and the second reference line are arranged as a mesh type.
Nevertheless, in a related endeavor (Fig 1-10 of Jo ‘506) Jo ‘506 teaches wherein the first reference line (VL2) and the second reference line (VL1) are arranged as a mesh type (Para [0049] discloses VL1 and VL2 connected in a mesh formation).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Jo 506’s teaching of the first reference line and the second reference line are arranged as a mesh type into Choi ‘749’s apparatus. The ordinary artisan would have been motivated to modify Choi ‘749 in the manner set forth above, at least, because, a mesh structure for electrical lines, such as the reference lines creates open areas in the display that enable light to pass without interference from the electrical wires.
As incorporated, the mesh structure for the reference lines of Jo ‘506 would be used as the arrangement of RL and URL of Choi ‘749.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898