Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority Korean Patent Application No. 10-2021-013665, filed on October 14, 2021.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed July 24, 2025. Claims 1, 15, and 20 are amended. The Examiner notes that claims 1-20 are examined.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 10, 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Heo (US 2016/0079208 A1) in view of Su (US 2012/0139092), Sung (US 2018/0175011 A1), Huang-066 (US 2002/0034066 A1), Ramanathan (US 2020/00194330 A1), and Reyes (US 6,762,495 B1).
With respect to claim 1, Heo teaches in Figs. 1B and 2B:/
A semiconductor package comprising:
a first semiconductor chip (para. 54 semiconductor chip 300 and para. 55 circuit pattern 310) comprising:
a first surface (top surface of 300);
first surface signal pads (para. 54 connecting pad 331) and first surface dummy pads (para. 54 second thermal pad 341) disposed on the first surface (top),
a second surface (bottom of 300) opposite to the first surface;
second surface signal pads (conductive pad 313) and second surface dummy pads (para. 45, upper thermal pad 245 of Fig. 2B) disposed on the second surface (bottom of 300),
and first through electrodes (second through via 320) that electrically connect the first surface signal pads (331) and the second surface signal pads (313);
a second semiconductor chip (semiconductor chip 400) disposed on the first semiconductor chip (300) and spaced from the first semiconductor device in a vertical direction (see Fig. 1B, chips are vertically stacked),
the second semiconductor chip comprising:
a third surface (top of 400);
third surface signal pads and third surface dummy pads disposed on the third surface (para. 59, “a fourth semiconductor chip (not shown) may be mounted on the third semiconductor chip 400. In this case, the third semiconductor chip 400 may include a third through-via (not shown) and a third heat dissipation part (not shown). The third through-via may penetrate the third semiconductor chip 400, and the third heat dissipation part may be disposed on a top surface of the third semiconductor chip 400. In this case, the heat slug 350 may be formed on the fourth semiconductor chip.” Although not explicitly mentioned, based on the description of the semiconductor chip 400 including a through-via, the examiner takes the position that the claimed second upper signal pads would be inherent to the through-via of said semiconductor chip 400 in the same manner the first semiconductor chip 300 comprises through-vias and signal pads.
Alternatively, before the effective filing date, it would have been obvious to a person having ordinary skill in the art to include connecting bumps and conductive pads between the semiconductor chips thereby arriving at the limitation in question so as to enable electrical/electronic communication to and from the semiconductor chip 400.);
a fourth surface (bottom of 400) opposite to the third surface (top of 400);
fourth surface signal pads (413) and fourth surface dummy pads (245 of Fig. 2B, modified into semiconductor chip 400 of Fig. 1B) disposed on the fourth surface, and
second through electrodes that electrically couple the third surface signal pads and the fourth surface signal pads (para. 59, “a fourth semiconductor chip (not shown) may be mounted on the third semiconductor chip 400. In this case, the third semiconductor chip 400 may include a third through-via (not shown)”),
an interface (third insulating pattern 530 and connecting bumps 333 disposed therein) between the fourth surface (bottom of 400) of the second semiconductor chip (400) and the first surface (top of 300) of the second semiconductor chip (300), wherein the interface comprises:
signal conductive bumps (connecting bumps 333) that connect the first surface (331) signal pads and the fourth surface (413) signal pads;
and dummy conductive bumps (243 of 2B, modified into the embodiment of Fig. 1B) that connect the first surface dummy pads (341) and the fourth surface dummy pads (245 of Fig. 2B modified into embodiment of Fig. 1B);
Heo fails to teach:
wherein at least a first portion of the first surface dummy pads are expanded coverage dummy pads;
wherein each expanded coverage dummy pad covers two or more of the fourth surface dummy pads;
and a plurality of first metal plating layers disposed between the expanded coverage dummy pads and the dummy conductive bumps, wherein each expanded coverage dummy pad is connected to two or more of the dummy conductive bumps, separated from one another by a non-conductive adhesive layer, via two or more of the plurality of first metal plating layers and wherein;
a combined area of two or more of the fourth surface dummy pads connected to a first one of the expanded coverage dummy pads defines a first area;
an area of the first one of the expanded coverage dummy pads defines a second area; and
the second area is at least 1.5 to 2.5 times larger than the first area.
Su teaches in Fig. 3:
wherein at least a first portion of the first surface dummy pads (shielding layer 321) are expanded coverage dummy pads (expanded to connect multiple conductive bumps 302);
wherein each expanded coverage dummy pad (321) is connected to two or more of the dummy conductive bumps (302),
wherein the expanded coverage dummy pads (321) are disposed between the first semiconductor chip (Die-2) and the second semiconductor chip (Die-3) with respect to the vertical direction
Heo discloses the claimed invention except for the expanded coverage dummy pads in contact with multiple dummy conductive bumps separated by adhesive. Su teaches that it is known to use a heat conducting shielding layer connected to dummy bumps. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Heo with the dummy structure as taught by Su since Su states in para. 38 that such a modification would accelerate dissipation of heat generated by the chips. See MPEP 2144.
Sung teaches in Fig. 2:
wherein each expanded coverage dummy pad (179) covers two or more of the dummy conductive bumps (para. 49, third inner connectors 410 which “may be bumps having substantially the same size and shape as the first or second inner connectors 210 or 310”), that are separated from one another by a non-conductive adhesive layer (para. 29, encapsulant 500 which may include an epoxy molding compound or a polymer material)
Heo/Su discloses the claimed invention except for the expanded coverage dummy pads surrounded by an adhesive Sung teaches that it is known to put an adhesive between conductive bumps that are attached to an expanded coverage pad. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Heo/Su with the adhesive taught by Sung for the purpose of improving the protection and mechanical connection of the chip stack. See MPEP 2144.
Huang-066 teaches Figs. 2-3 and para. 26:
wherein each expanded coverage dummy pad (second thermal ball pads 222) covers two or more of the fourth surface dummy pads (contacts 262, although Fig. 2 shows only one of second thermal balls 252 and 254 contacting a contact 262, para 26 teaches another embodiment in which both are connected to contacts 262 “The second thermal balls 252 and 254 can be selectively attached to the contacts 262.”)
Huang-066 does not explicitly teach the area of the pads, however, Fig. 2-3 show that 222 has a larger surface area than two of 262. It has been ruled that changes of dimension are prima facie obvious absent persuasive evidence that the particular dimension is significant (MPEP 2144.04(IV)(A)). The Examiner takes the position that although it is not clear if the device of Huang anticipates the limitation:
“a combined area of two or more of the fourth surface dummy pads connected to a first one of the expanded coverage dummy pads defines a first area;
an area of the first one of the expanded coverage dummy pads defines a second area; and
the second area is at least 1.5 to 2.5 times larger than the first area.”
It would be obvious to one of ordinary skill in the art to arrive at the claimed ratio of areas through routine optimization and experimentation within prior art conditions in order to tune the desired thermal properties and size of the device as the ordinary artisan would be motivated to optimize the heat dissipated through the printed circuit board and the thermal stress on the package as taught in para. 26 of Huang-066. (MPEP 2144.05(II)(A))
Heo/Su/Sung discloses the claimed invention except for the expanded coverage dummy pads that cover non-expanded coverage dummy pads with an area that is 1.5 to 2.5 times larger than the area of the non-expanded coverage dummy pads. Huang-066 teaches that it is known to have the expanded coverage dummy pad with an area larger than the non-expanded dummy pads that it covers. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Heo/Sung with the pads as taught by Huang-066, since Huang-066 states in para. 26 that such a modification would provide heat dissipation routes in the device. See MPEP 2144.
Ramanathan teaches in Fig. 5E:
and a plurality of first metal plating layers (para. 41, Ni or Ni-alloy surface finish 383) disposed between the expanded coverage dummy pads (seed layer 382 which may be copper and/or adhesion layer 381 which may be titanium) and the dummy conductive bumps (para. 24 “thermal solder features 130 are inoperable to convey electrical power”), wherein each expanded coverage dummy pad (382 and/or 381) is connected to two or more of the dummy conductive bumps (Fig. 5E shows two instances of 130 A) via two or more of the plurality of first metal plating layers (each of the two thermal solder features 130A are connected to an instance of 383) and wherein;
Heo/Su/Sung/Huang-066 discloses the claimed invention except for the metal plating layers between the pads and the bumps. Ramanathan teaches that it is known dispose a metal plating layer between a dummy pad and a dummy bump. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Heo/Sung/Huang-066 with the metal plates as taught by Ramanathan, since Ramanathan states in para. 39 that such a modification would improve integration of thermal routing features (traces, pads, planes) to connect thermal solder bumps. See MPEP 2144.
Reyes teaches in Fig. 2:
the first surface of the first semiconductor chip comprises an inner region and an outer region that surrounds the inner region (see annotated Fig. 2 below. Outer region is region within red boxes in corners);
the outer region includes a region adjacent to a corner of the first semiconductor chip (see annotated Fig. 2);
and at least one of the first surface dummy pads (copper ball land pad 250) are disposed in the region adjacent to the corner of the first semiconductor chip (see annotated Fig. 2 below. The first surface expanded coverage dummy pads, copper ball land pad 250, is within the boxes of the corners).
Heo/Su/Sung/Huang-066/Ramanathan discloses the claimed invention except for the location of the merged pads on the chip. Reyes teaches that it is known to put them in an outer region on the corner of the chip. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Heo/Sung/Huang-066/Ramanathan with the layout taught by Reyes, since Reyes states in col. 1, lns. 36-45 that such a modification would improve the strength of the array because areas around the corners are under heavy strange due to mismatched coefficients of thermal expansion. See MPEP 2144.
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With respect to claim 3, Heo/Su/Sung/Huang-066/Ramanathan modified to have the layout of Reyes further teaches:
the first surface signal pads are disposed in the inner region (the white circles in the layout of Reyes above indicate locations of the solder ball connection 205 that carries electrical signal).
With respect to claim 4, Huang-066 and Ramanathan further teach:
one of the expanded coverage dummy pads (222 of Huang) covers two of the fourth surface dummy pads (262 of Huang beneath both 252 and 254 in embodiment where both are connected to lower pads);
and an arrangement of two of the first metal plating layers (383 of Ramanathan) on the one of the expanded coverage dummy pads (381 and/or 382 of Ramanathan, 222 of Huang) corresponds to an arrangement of the two of the fourth surface dummy pads (262 of Huang).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Heo in view of Su, Sung, Huang, Ramanathan, and Reyes as explained above.
With respect to claim 5, Huang-066, Ramanathan, and Reyes further teaches:
one of the expanded coverage dummy pads (222 of Huang, 381 and/or 382 of Ramanathan) covers a square arrangement of four of the fourth surface dummy pads (262 of Huang in embodiment where 252 and 254 all connect to lower bumps in the arrangement of Ramanathan where (at least) four bumps are combined in the corner); and
an arrangement of four of the first metal plating layers (383 of Ramanathan) on the one of the expanded coverage dummy pads (222 of Huang, modified by the teachings of Ramanathan to include the metal plating layer 383 in the arrangement of Fig. 2 of Reyes) corresponds to the square arrangement (Fig. 2 of Reyes).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Heo in view of Su, Sung, Huang, Ramanathan, and Reyes as explained above.
With respect to claim 10, Heo and Ramanathan further teaches:
wherein a second portion of the first surface dummy pads (second thermal pad 341 of Heo) are non-expanded coverage dummy pads that each cover only a respective one (245 of Fig. 2B, modified into the embodiment of Fig. 1B of Heo) of the fourth surface dummy pads.
a second metal plating layer is disposed on each of the non-expanded coverage dummy pads (Fig. 3A of Ramanathan shows that metal plating layer 383 is deposited on all pads, whether they are combined, not combined, thermal, or conductive).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Heo in view of Su, Sung, Huang, Ramanathan, and Reyes as explained above.
With respect to claim 13, Huang-066 further teaches:
wherein all of the first surface dummy pads are expanded coverage dummy pads (see Fig. 3 of Huang, all of the thermal pads 222 are merged).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Heo in view of Su, Sung, Huang, Ramanathan, and Reyes as explained above.
With respect to claim 14, Heo/Su/Sung/Huang-066/Ramanathan/Reyes as combined above does not teach:
a third semiconductor chip disposed on the second semiconductor chip, the third semiconductor chip comprising:
a fifth surface;
fifth surface signal pads and fifth surface dummy pads disposed on the fifth surface, wherein at least a portion of the third surface dummy pads are additional expanded coverage dummy pads and wherein each additional expanded coverage dummy pad covers two or more of the fifth surface dummy pads;
an additional interface disposed between the fifth surface of the third semiconductor chip and the third surface of the second semiconductor chip, wherein the additional interface comprises:
additional signal conductive bumps that connect the third surface signal pads and the fifth surface signal pads; and
additional dummy conductive bumps that connect the third surface dummy pads and the fifth surface dummy pads, and
a plurality of additional metal plating layers disposed between the additional expanded coverage dummy pads,
and the additional dummy conductive bumps, wherein each additional expanded coverage dummy pad is connected to two or more of the additional dummy conductive bumps via two or more of the plurality of additional metal plating layers.
However, Heo further teaches in para. 59:
“Embodiments are not limited to the number of the semiconductor chips. In other embodiments, a fourth semiconductor chip (not shown) may be mounted on the third semiconductor chip 400. In this case, the third semiconductor chip 400 may include a third through-via (not shown) and a third heat dissipation part (not shown). The third through-via may penetrate the third semiconductor chip 400, and the third heat dissipation part may be disposed on a top surface of the third semiconductor chip 400.”
Therefore, Heo/Su/Sung/Huang-066/Ramanathan/Reyes further modified by Heo to include another copy of 300, 315, 530, and bumps 333 within 530 teaches:
a third semiconductor chip (another copy of 300 and 315 of Heo) disposed on the second semiconductor chip (400 of Heo), the third semiconductor chip comprising:
a fifth surface (bottom);
fifth surface signal pads (313 of Heo) and fifth surface dummy pads (245 of Heo) disposed on the fifth surface (bottom),
wherein at least a portion of the third surface dummy pads are additional expanded coverage dummy pads (222 of Sung) and wherein each additional expanded coverage dummy pad covers two or more of the fifth surface dummy pads (262 of Sung);
an additional interface (530) disposed between the fifth surface (bottom) of the third semiconductor chip and the third surface (top) of the second semiconductor chip (400), wherein the additional interface comprises:
additional signal conductive bumps (333) that connect the third surface signal pads (413, added to 400 to accommodate another chip) and the fifth surface signal pads (331 of third chip); and
additional dummy conductive bumps (343 of additional layer added to accommodate third chip) that connect the third surface dummy pads (245) and the fifth surface (bottom) dummy pads (341), and
a plurality of additional metal plating layers disposed between the additional expanded coverage dummy pads (383 of Ramanathan incorporated into the third chip in the same way the first and second chip are modified),
and the additional dummy conductive bumps (130A of Ramanathan), wherein each additional expanded coverage dummy pad (381 and/or 382 of Ramanathan, 222 of Sung) is connected to two or more of the additional dummy conductive bumps (130 of Ramanathan) via two or more of the plurality of additional metal plating layers (383 of Ramanathan).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the further teachings of another embodiment Heo into the device of Heo/Su/Sung/Huang-066/Ramanathan/Reyes to include an additional chip layer. The ordinary artisan would have been motivated to modify Heo/Su/Sung/Huang-066/Ramanathan/Reyes in the manner set forth above for the purpose of developing a “multi-chip semiconductor package” that is “light, small, fast, high-performance, and low-cost.” (para. 2-3 of Heo.)
Claims 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Heo (US 2016/0079208 A1) in view of Su (US 2012/0139092), Sung (US 2018/0175011 A1), Huang-066 (US 2002/0034066 A1), Ramanathan (US 2020/00194330 A1), and Reyes (US 6,762,495 B1) as applied to claim 1 above and further in view of Choi (US 2022/0199430 A1).
With respect to claim 6, Heo/Su/Sung/Huang-066/Ramanathan/Reyes teach all limitations of claim 1 upon which claim 6 depends. Heo/Su/Sung/Huang-066/Ramanathan/Reyes fails to teach:
wherein the non-conductive adhesive layer disposed between the first semiconductor chip and the second semiconductor chip,
the non-conductive adhesive layer surrounding each of the signal conductive bumps and each of the dummy conductive bumps.
Choi teaches in Fig. 4:
wherein the non-conductive adhesive layer (adhesive layer 12) disposed between the first semiconductor chip (semiconductor chip 20) and package substrate 30
the non-conductive adhesive layer surrounding each of the signal conductive bumps (bumps 21)
Although Choi does not disclose the second semiconductor chip, the arrangement of Choi provides for placing the adhesive layer 12 between the chips of Heo/Sung/Huang-066/Ramanathan/Reyes as well. Further, making this modification in the structure of Heo/Sung/Huang-066/Ramanathan/Reyes in which some of the bumps are dummy conductive bumps meets the limitation:
and each of the dummy conductive bumps.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Choi into the device of Heo/Su/Sung/Huang-066/Ramanathan/Reyes to include an adhesive layer surrounding the conductive bumps between the chips. The ordinary artisan would have been motivated to modify Heo/Su/Sung/Huang-066/Ramanathan/Reyes in the manner set forth above for the purpose “simplifying the bonding process and increasing manufacturing efficiency” (para. 2 of Choi.)
With respect to claim 7, Heo further teaches:
wherein a second portion of the first surface dummy pads (second thermal pad 341 of Heo) are non-expanded coverage dummy pads that each cover only a respective one (245 of Fig. 2B, modified into the embodiment of Fig. 1B of Heo) of the fourth surface dummy pads.
With respect to claim 8, Reyes further teaches:
the first surface of the first semiconductor chip comprises an inner region and an outer region that surrounds the inner region (see annotated Fig. 2 of Reyes above. Outer region is region within red boxes in the corners);
the outer region includes a region adjacent to a corner of the first semiconductor chip (see annotated Fig. 2 of Reyes above);
and at least one of the first surface dummy pads are disposed in the region adjacent to the corner of the first semiconductor chip (see annotated Fig. 2 of Reyes above. The first surface expanded coverage dummy pads are within the boxes of the corners).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Heo in view of Su, Sung, Huang-066, Ramanathan, and Reyes as explained above.
With respect to claim 9, Reyes teaches in Fig. 2:
at least some of the non-expanded coverage dummy pads (solder ball pads 208 connected to dummy balls 210 along the diagonal 235) are disposed between the regions adjacent to the corners of the first semiconductor chip (see annotated Fig. 2 above).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Heo in view of Su, Sung, Huang-066, Ramanathan, and Reyes as explained above.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Heo (US 2016/0079208 A1) in view of Su (US 2012/0139092), Sung (US 2018/0175011 A1), Huang-066 (US 2002/0034066 A1), Ramanathan (US 2020/00194330 A1), and Reyes (US 6,762,495 B1) as applied to claim 10 above and further in view of Huang-615 (US 2014/0042615 A1).
With respect to claim 11, Heo/Su/Sung/Huang-066/Ramanathan/Reyes teach all limitations of claim 10 upon which claim 11 depends. Heo/Sung/Huang-066/Ramanathan/Reyes fail to teach:
wherein each of the plurality of first metal plating layers has an area larger than an area of the second metal plating layer.
Huang-615 teaches in Figs. 2, 5, and 6:
wherein each of the plurality of first metal plating layers (bonding pad 206 that is under the UBM 210’) has an area larger than an area of the second metal plating layer (bonding pad 206 that is under UBM 210).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Huang-615 into the device of Heo/Su/Sung/Huang-066/Ramanathan/Reyes to make a device in which the dummy pads are expanded and there is a metal plate between the pads and the bumps. The ordinary artisan would have been motivated to modify Heo/Su/Sung/Huang-066/Ramanathan/Reyes in the manner set forth above for the purpose of “defining a size of the conductive element” (para. 20 of Huang-615).
With respect to claim 12, Huang-615 further teaches
a first portion of conductive bumps (400’) are disposed on the expanded coverage dummy pads (bonding pad 206 of Fig. 5 beneath UBM 210’);
a second portion of conductive bumps (400) are disposed on the non-expanded coverage dummy pad (bonding pads 206 of Fig. 2 beneath 210);
each of the conductive bumps (400 or 400’) of the first portion has a first volume;
each of the dummy conductive bumps of the second portion has a second volume;
and the first volume is larger than the second volume (para 26, “a copper portion 402 ′ and a solder cap portion 404 ′ of the conductive element 400 ′ shown in FIG. 5 also have a feature size greater than that of the copper portion 402 and the solder cap portion 404 of the conductive element 400.”)
Although Huang-615 does not teach that the conductive bumps are dummy, it would be obvious to apply the teachings of Huang into the dummy conductive bumps of Heo/Su/Sung/Huang-066/Ramanathan/Reyes, as it would be known to the ordinary artisan that the size of the dummy conductive bumps affects the thermal properties and bonding stability of the package. The ordinary artisan would be motivated to include dummy conductive bumps of higher volume on expanded coverage pads compared to non-expanded coverage pads for the purpose of tuning the heat dissipation and stress characteristics of the device.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Heo (US 2016/0079208 A1) in view of Su (US 2012/0139092), Sung (US 2018/0175011 A1), Huang-066 (US 2002/0034066 A1), Reyes (US 6,762,495 B1) and Choi (US 2022/0199430 A1).
With respect to claim 15, Heo teaches:
a first semiconductor chip (para. 54 semiconductor chip 300 and para. 55 circuit pattern 310) comprising:
a first surface (top surface of 300);
first surface signal pads (para. 54 connecting pad 331) and first surface dummy pads (para. 54 second thermal pad 341) disposed on the first surface (top),
a second portion of the first surface dummy pads (second thermal pad 341 of Heo) are non-expanded coverage dummy pads
a second surface (bottom of 300) opposite to the first surface;
second surface signal pads (conductive pad 313) and second surface dummy pads (para. 45, upper thermal pad 245 of Fig. 2B) disposed on the second surface (bottom of 300),
and through electrodes (second through via 320) that electrically connect the first surface signal pads (331) and the second surface signal pads (313);
a second semiconductor chip (semiconductor chip 400) disposed on the first semiconductor chip (300) and spaced from the first semiconductor device in a vertical direction (see Fig. 1B),
the second semiconductor chip comprising:
a third surface (top of 400);
a fourth surface (bottom of 400);
fourth surface signal pads (413) and fourth surface dummy pads (245 of Fig. 2B, modified into semiconductor chip 400 of Fig. 1B) disposed on the fourth surface, wherein;
each non-expanded coverage dummy pad covers a respective one (245 of Fig. 2B, modified into the embodiment of Fig. 1B of Heo) of the fourth surface dummy pads.
an interface (third insulating pattern 530 and connecting bumps 333 disposed therein) between the fourth surface (bottom of 400) of the second semiconductor chip (400) and the first surface (top of 300) of the second semiconductor chip (300), wherein the interface comprises:
signal conductive bumps (connecting bumps 333) that connect the first surface (331) signal pads and the fourth surface (413) signal pads;
and dummy conductive bumps (243 of 2B, modified into the embodiment of Fig. 1B) that connect the first surface dummy pads (341) and the fourth surface dummy pads (245 of Fig. 2B modified into embodiment of Fig. 1B);
Heo fails to teach:
a first surface comprising an inner region and an outer region that surrounds the inner region,
wherein the outer region includes regions adjacent to corners of the first semiconductor chip;
at least some of the expanded coverage dummy pads are disposed in the regions adjacent to the corners of the first semiconductor chip;
at least some of the non-expanded coverage dummy pads are disposed between the regions adjacent to the corners of the first semiconductor chip;
each expanded coverage dummy pad covers two or more of the fourth surface dummy pads; and
wherein the expanded coverage dummy pads are disposed between the first semiconductor chip and the second semiconductor chip with respect to the vertical direction
wherein each expanded coverage dummy pad covers two or more of the dummy conductive bumps;
a non-conductive adhesive layer disposed between the first semiconductor chip and the second semiconductor chip, surrounding the signal conductive bumps, the non-conductive adhesive layer separating the two or more of the dummy conductive bumps connected to a respective expanded coverage dummy pad from each other;
wherein;
a combined area of two or more of the fourth surface dummy pads connected to a first one of the expanded coverage dummy pads defines a first area;
an area of the first one of the expanded coverage dummy pads defines a second area; and
the second area is at least 1.5 to 2.5 times larger than the first area
Su teaches in Fig. 3:
a first portion of the first surface dummy pads (shielding layer 321) are expanded coverage dummy pads (expanded to connect multiple conductive bumps 302);
wherein each expanded coverage dummy pad (321) is connected to two or more of the dummy conductive bumps (302),
wherein the expanded coverage dummy pads (321) are disposed between the first semiconductor chip (Die-2) and the second semiconductor chip (Die-3) with respect to the vertical direction
Heo discloses the claimed invention except for the expanded coverage dummy pads in contact with multiple dummy conductive bumps separated by adhesive. Su teaches that it is known to use a heat conducting shielding layer connected to dummy bumps. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Heo with the dummy structure as taught by Su since Su states in para. 38 that such a modification would accelerate dissipation of heat generated by the chips. See MPEP 2144.
Sung teaches in Fig. 2:
wherein each expanded coverage dummy pad (179) is connected to two or more of the dummy conductive bumps (para. 49, third inner connectors 410 which “may be bumps having substantially the same size and shape as the first or second inner connectors 210 or 310”),
non-conductive adhesive layer separating the two or more of the dummy conductive bumps connected to a respective expanded coverage dummy pad from each other (para. 29, encapsulant 500 which may include an epoxy molding compound or a polymer material is disposed between third inner connectors 410 which are connected to 179)
Heo/Su discloses the claimed invention except for the expanded coverage dummy pads surrounded by an adhesive Sung teaches that it is known to put an adhesive between conductive bumps that are attached to an expanded coverage pad. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Heo/Su with the adhesive taught by Sung for the purpose of improving the protection and mechanical connection of the chip stack. See MPEP 2144.
Huang-066 teaches Figs. 2-3 and para. 26:
wherein each expanded coverage dummy pad (second thermal ball pads 222) covers two or more of the fourth surface dummy pads (contacts 262, although Fig. 2 shows only one of second thermal balls 252 and 254 contacting a contact 262, para 26 teaches another embodiment in which both are connected to contacts 262 “The second thermal balls 252 and 254 can be selectively attached to the contacts 262.”)
Huang-066 does not explicitly teach the area of the pads, however, Fig. 2-3 show that 222 has a larger surface area than two of 262. It has been ruled that changes of dimension are prima facie obvious absent persuasive evidence that the particular dimension is significant (MPEP 2144.04(IV)(A)). The Examiner takes the position that although it is not clear if the device of Huang anticipates the limitation:
“a combined area of two or more of the fourth surface dummy pads connected to a first one of the expanded coverage dummy pads defines a first area;
an area of the first one of the expanded coverage dummy pads defines a second area; and
the second area is at least 1.5 to 2.5 times larger than the first area.”
It would be obvious to one of ordinary skill in the art to arrive at the claimed ratio of areas through routine optimization and experimentation within prior art conditions in order to tune the desired thermal properties and size of the device as the ordinary artisan would be motivated to optimize the heat dissipated through the printed circuit board and the thermal stress on the package as taught in para. 26 of Huang-066. (MPEP 2144.05(II)(A)).
Heo/Su/Sung discloses the claimed invention except for the expanded coverage dummy pads that cover non-expanded coverage dummy pads with an area that is 1.5 to 2.5 times larger than the area of the non-expanded coverage dummy pads. Huang-066 teaches that it is known to have the expanded coverage dummy pad with an area larger than the non-expanded dummy pads that it covers. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Heo/Su/Sung with the pads as taught by Huang-066, since Huang-066 states in para. 26 that such a modification would provide heat dissipation routes in the device. See MPEP 2144.
Reyes teaches in Fig. 2:
comprising an inner region and an outer region that surrounds the inner region (see annotated Fig. 2 above. Outer region is region within red boxes in corners);
the outer region includes regions adjacent to corners of the first semiconductor chip (see annotated Fig. 2 above);
at least some of the expanded coverage dummy pads are disposed in the regions adjacent to the corners of the first semiconductor chip (see annotated Fig. 2 above. The first surface expanded coverage dummy pads are within the boxes of the corners
at least some of the non-expanded coverage dummy pads (solder ball pads 208 connected to dummy balls 210 along the diagonal 235) are disposed between the regions adjacent to the corners of the first semiconductor chip (see annotated Fig. 2 above).
Heo/Su/Sung/Huang-066 discloses the claimed invention except for the location of the merged pads on the chip. Reyes teaches that it is known to put them in an outer region on the corner of the chip. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Heo/Su/Sung/Huang-066 with the layout taught by Reyes, since Reyes states in col. 1, lns. 36-45 that such a modification would improve the strength of the array because areas around the corners are under heavy strange due to mismatched coefficients of thermal expansion. See MPEP 2144.
Choi teaches:
a non-conductive adhesive layer (adhesive layer 12) disposed between the first semiconductor chip (semiconductor chip 20) and package substrate 30
surrounding the signal conductive bumps (bumps 21)
Although Choi does not disclose the second semiconductor chip, the arrangement of Choi provides for placing the adhesive layer 12 between the chips of Heo/Sung/Huang-066/Reyes as well. Further, making this modification in the structure of Heo/Sung/Huang-066/Reyes in which some of the bumps are dummy conductive bumps meets the limitation:
the non-conductive adhesive layer surrounding the dummy conductive bumps;
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Choi into the device of Heo/Su/Sung/Huang-066/Reyes to include an adhesive layer surrounding the conductive bumps between the chips. The ordinary artisan would have been motivated to modify Heo/Su/Sung/Huang-066/Reyes in the manner set forth above for the purpose “simplifying the bonding process and increasing manufacturing efficiency” (para. 2 of Choi.).
Claims 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Heo (US 2016/0079208 A1) in view of Su (US 2012/0139092), Sung (US 2018/0175011 A1), Huang-066 (US 2002/0034066 A1), Reyes (US 6,762,495 B1) and Choi (US 2022/0199430 A1) as applied to claim 15 above and further in view of Huang-615 (US 2014/0042615 A1).
With respect to claim 16, Heo/Su/Sung/Huang-066/Reyes/Choi teaches all limitations of claim 15 upon which claim 16 depends. Heo/Su/Sung/Huang-066/Reyes/Choi fails to teaches:
a plurality of first metal plating layers disposed on one of the expanded coverage dummy pads; and
a second metal plating layer disposed on one of the non-expanded coverage dummy pads.
Huang-615 teaches:
a plurality of first metal plating layers (UBM layer 210’) disposed on one of the expanded coverage dummy pads (206 in Fig. 5); and
a second metal plating layer (UBM layer 210) disposed on one of the non-expanded coverage dummy pads (206 in Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Huang-615 into the device of Heo/Su/Sung/Huang-066/Reyes/Choi to make a device in which the dummy pads are expanded and there is a metal plate between the pads and the bumps. The ordinary artisan would have been motivated to modify Heo/Su/Sung/Huang-066/Reyes/Choi in the manner set forth above for the purpose of “defining a size of the conductive element” (para. 20 of Huang).
With respect to claim 17, Huang-615 further teaches:
wherein each first metal plating layer (210’) of the plurality of first metal plating layers has an area larger than an area of the second metal plating layer (210) (para. 26 “the feature size S2 of the UBM layer 210' is different from the feature size S1 of the other UBM layers 210 in the areas 500 as illustrated in FIG. 2. In one embodiment, the feature size S2 is about, for example 150-500% greater than the feature size S1.”)
With respect claim 18, Huang-615 further teaches:
a first portion of the conductive bumps (400’) are disposed on plurality of first metal plating layers (UBM 210’);
a second one of the conductive bumps (400) is disposed on the second metal plating layer (UBM 210);
Although Huang-615 does not teach that the conductive bumps are dummy, it would be obvious to apply the teachings of Huang-615 into the dummy conductive bumps of Heo/Su/Sung/Huang-066/Reyes/Choi, as it would be known to the ordinary artisan that the size of the dummy conductive bumps affects the thermal properties and bonding stability of the package. The ordinary artisan would be motivated to include dummy conductive bumps of higher volume on expanded coverage pads compared to non-expanded coverage pads for the purpose of tuning the heat dissipation and stress characteristics of the device.
With respect claim 19, Heo/Su/Sung/Huang-066/Reyes/Choi/Huang-615 further teaches:
wherein each of the conductive dummy bumps (dummy bumps of Heo/Su/Sung/Huang-066/Reyes/Choi modified to be the bump 400’ of Huang-615) of the first portion has a volume larger than a volume of the second one of the conductive dummy bumps (dummy bumps of Heo/Su/Sung/Huang-066/Reyes/Choi modified to be the bump 400 of Huang-615). (para 26 of Huang-615, “a copper portion 402 ′ and a solder cap portion 404 ′ of the conductive element 400 ′ shown in FIG. 5 also have a feature size greater than that of the copper.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Heo (US 2016/0079208 A1) in view of Su (US 2012/0139092), Sung (US 2018/0175011 A1), Huang-066 (US 2002/0034066 A1) and Ramanathan (US 2020/00194330 A1).
With respect to claim 20, Heo teaches in Figs. 1B and 2B:
First (semiconductor chip 200) and second substrates (semiconductor chip 300) that are vertically stacked in a vertical direction (see Fig. 1B), wherein the first substrate comprises first (top) and second (bottom) surfaces and the second substrate comprises third (top) and fourth (bottom) surfaces;
a semiconductor device layer (circuit pattern layer 310) disposed on the fourth surface (bottom) of the second substrate (300) and facing the first surface (top) of the first substrate (300);
through electrodes (through-via 320) penetrating through the second substrate (300) fourth surface signal pads (conductive pad 313) disposed on the semiconductor device layer (310) and electrically connected to the through electrodes (320);
fourth surface dummy pads (upper thermal pad 245 of Fig. 2B) disposed on the semiconductor device layer (310);
first surface signal pads (connecting pad 231) disposed on the first surface (top) of the first substrate (200), vertically arranged with the fourth surface signal pads (313, see Fig. 1B), and electrically connected to the first surface signal pads;
first surface dummy pads (thermal pad 241) disposed on the first surface (top) of the first substrate (200);
signal conductive bumps (connecting bumps 233) electrically connecting the fourth surface signal pads (313) and the first surface signal pads (231), respectively; and
Heo fails to teach:
wherein the first surface dummy pads are expanded coverage dummy pads, and wherein each expanded coverage dummy pad covers two or more of the fourth surface dummy pads;
a plurality of metal plating layers disposed on the first surface dummy pads;
dummy conductive bumps disposed on the plurality of metal plating layers and electrically connecting the fourth surface dummy pads and the first surface dummy pads;
wherein each expanded coverage dummy pad covers two or more of the dummy conductive bumps that are separated from one another by a non-conductive adhesive layer;
wherein the expanded coverage dummy pads are disposed between the first semiconductor chip and the second semiconductor chip with respect to the vertical direction
wherein:
a combined area of two or more of the fourth surface dummy pads connected to a first one of the expanded coverage dummy pads defines a first area;
an area of the first one of the expanded coverage dummy pads defines a second area; and
the second area is at least 1.5 to 2.5 times larger than the first area
Su teaches in Fig. 3:
wherein at least a first portion of the first surface dummy pads (shielding layer 321) are expanded coverage dummy pads (expanded to connect multiple conductive bumps 302);
wherein each expanded coverage dummy pad (321) is connected to two or more of the dummy conductive bumps (302),
wherein the expanded coverage dummy pads (321) are disposed between the first semiconductor chip (Die-2) and the second semiconductor chip (Die-3) with respect to the vertical direction
Heo discloses the claimed invention except for the expanded coverage dummy pads in contact with multiple dummy conductive bumps separated by adhesive. Su teaches that it is known to use a heat conducting shielding layer connected to dummy bumps. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Heo with the dummy structure as taught by Su since Su states in para. 38 that such a modification would accelerate dissipation of heat generated by the chips. See MPEP 2144.
Sung teaches in Fig. 2:
wherein each expanded coverage dummy pad (179) covers two or more of the dummy conductive bumps (para. 49, third inner connectors 410 which “may be bumps having substantially the same size and shape as the first or second inner connectors 210 or 310”), that are separated from one another by a non-conductive adhesive layer (para. 29, encapsulant 500 which may include an epoxy molding compound or a polymer material)
Heo/Su discloses the claimed invention except for the expanded coverage dummy pads surrounded by an adhesive Sung teaches that it is known to put an adhesive between conductive bumps that are attached to an expanded coverage pad. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Heo/Su with the adhesive taught by Sung for the purpose of improving the protection and mechanical connection of the chip stack. See MPEP 2144.
Huang teaches Figs. 2-3 and para. 26:
wherein each expanded coverage dummy pad (second thermal ball pads 222) covers two or more of the fourth surface dummy pads (contacts 262, although Fig. 2 shows only one of second thermal balls 252 and 254 contacting a contact 262, para 26 teaches another embodiment in which both are connected to contacts 262 “The second thermal balls 252 and 254 can be selectively attached to the contacts 262.”)
Huang does not explicitly teach the area of the pads, however, Fig. 2-3 show that 222 has a larger surface area than two of 262. It has been ruled that changes of dimension are prima facie obvious absent persuasive evidence that the particular dimension is significant (MPEP 2144.04(IV)(A)). The Examiner takes the position that although it is not clear if the device of Huang anticipates the limitation:
“a combined area of two or more of the fourth surface dummy pads connected to a first one of the expanded coverage dummy pads defines a first area;
an area of the first one of the expanded coverage dummy pads defines a second area; and the second area is at least 1.5 to 2.5 times larger than the first area”
It would be obvious to one of ordinary skill in the art to arrive at the claimed ratio of areas through routine optimization and experimentation within prior art conditions in order to tune the desired thermal properties and size of the device as the ordinary artisan would be motivated to optimize the heat dissipated through the printed circuit board and the thermal stress on the package as taught in para. 26 of Huang. (MPEP 2144.05(II)(A))
Heo/Su/Sung discloses the claimed invention except for the expanded coverage dummy pads that cover non-expanded coverage dummy pads with an area that is 1.5 to 2.5 times larger than the area of the non-expanded coverage dummy pads. Huang teaches that it is known to have the expanded coverage dummy pad with an area larger than the non-expanded dummy pads that it covers. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Heo/Su/Sung with the pads as taught by Huang, since Huang states in para. 26 that such a modification would provide heat dissipation routes in the device. See MPEP 2144.
Ramanathan teaches:
a plurality of metal plating layers (para. 41, Ni or Ni-alloy surface finish 383) disposed on the first surface dummy pads (seed layer 382 which may be copper and/or adhesion layer 381 which may be titanium);
dummy conductive bumps (para. 24 “thermal solder features 130 are inoperable to convey electrical power”), disposed on the plurality of metal plating layers (383) and electrically connecting the fourth surface dummy pads (substrate metallization features 369B and the first surface dummy pads (adhesion layer 381 and/or seed layer 382);
Heo/Su/Sung/Huang discloses the claimed invention except for the metal plating layers between the pads and the bumps. Ramanathan teaches that it is known dispose a metal plating layer between a dummy pad and a dummy bump. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Heo/Su/Sung/Huang with the metal plates as taught by Ramanathan, since Ramanathan states in para. 39 that such a modification would improve integration of thermal routing features (traces, pads, planes) to connect thermal solder bumps. See MPEP 2144.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897