DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/16/2026 has been entered.
Claim Status
Previous action: claims 1-4, 6, 8-20, and 22-25 rejected
Present action: claims 1-4, 6, 8-17, 19, 20, and 22-25 rejected
Previously applied 112 2nd paragraph rejection withdrawn, new 112 2nd paragraph rejection applied.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 2, 3, 4, 6, and 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a plurality of logic devices” in line 14. It is unclear whether these are the same or different from “a plurality of logic devices” recites in line 9.
Claim 2 recites the limitation "the plurality of memory devices" in line 2. There is insufficient antecedent basis for this limitation in the claim. Claim 1 recites “a plurality of DRAM devices”.
Claim 4 recites the limitation "the plurality of memory devices" in line 3. There is insufficient antecedent basis for this limitation in the claim. Claim 1 recites “a plurality of DRAM devices”.
Claim 6 recites the limitation "the memory devices" in line 3. There is insufficient antecedent basis for this limitation in the claim. Claim 1 recites “a plurality of DRAM devices”.
Claims 2, 3, 4, 6, and 8 depend from ad incorporate claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 1, 2, 3, 4, and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 2020/0328190) in view of Ooishi (US 6208547)
Regarding claim 1.
Liu teaches:
A method, comprising: forming memory-to-logic circuitry including: forming a plurality of first metal pads (fig 5b:531; [para 0063,0089]) on a first wafer (fig 5b:509; [para 0086]) that includes a plurality of dynamic random access memory (DRAM) devices (fig 5b:513; [para 0086]);
and for each of the plurality of DRAM devices (fig 5b:513; [para 0086]), coupling a plurality of local input/output (LIO) lines (fig 5b:527; [para 0088]) to a respective subset of the plurality of first metal pads (fig 5b:531; [para 0086,0089]);
forming logic-to-memory circuitry including: forming a plurality of second metal pads (fig 5b:535; [para 0063,0089]) on a second wafer (fig 5b:541; [para 0093]) that includes a plurality of logic devices (fig 5b:543,547; [para 0091]);
and coupling a respective [peripheral circuit] (fig 5b:515; [para 0087]) to a respective subset of the plurality of second metal pads (fig 5b:535; [para 0063,0089]);
bonding, via a wafer-on-wafer bonding process ([para 0085]), the subset of the first metal pads (fig 5b:531; [para 0086,0089]) to the subset of the second metal pads (fig 5b:535; [para 0063,0089]) such that each of the plurality of DRAM devices (fig 5b:513; [para 0086]) on the first wafer (fig 5b:509; [para 0086]) is aligned with and coupled to at least a respective one of a plurality of logic devices (fig 5b:543,547; [para 0091]) on the second wafer (fig 5b:541; [para 0093]);
and singulating the bonded first and second wafers (fig 9b:902,904; [para 0108]) into individual wafer-on-wafer bonded memory and logic dies (fig 9c:912; [para 0113]), wherein the respective subset of the first metal pads (fig 5b:531; [para 0086,0089]) and respective subset of second metal pads (fig 5b:535; [para 0063,0089]) are dedicated to communication selectively enabled between the plurality of LIO lines (fig 5b:527; [para 0088]) and the respective one of the plurality of logic devices (fig 5b:543,547; [para 0091]) by the respective [peripheral circuit].
PNG
media_image1.png
600
1194
media_image1.png
Greyscale
Liu does not teach that the [peripheral circuitry] is on the second wafer.
Liu teaches a second embodiment comprising:
Peripheral circuity of DRAM (fig 2A,2B:206; [para 0052]) on the second wafer (fig 2b:200; [para 0052])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the peripheral circuitry to be disposed on the second wafer in order to distribute the circuitry and thereby increase the efficiency of the chip area utilization, thereby reducing the cost (paragraph 38).
Liu does not teach the components of DRAM peripheral control circuitry.
Ooishi teaches:
the memory circuitry (fig 1) comprising coupling a respective transceiver (fig 1:1086; [column 8 lines 20-25])to a respective subset of the plurality of [terminals] (fig 1:DQ; [column 8 lines 20-25])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a transceiver in order to facilitate the transmission of signals from the logic to memory regions.
Regarding claim 2.
Liu in view of Ooishi teaches the method of claim 1, further:
Liu teaches:
prior to bonding the subset of the first metal pads (fig 5b:531; [para 0086])to the subset of the second metal pads (fig 5b:535; [para 0063,0089]), forming the plurality of memory devices (fig 5b:513; [para 0086]),on the first wafer (fig 5b:509; [para 0086]).
Regarding claim 3.
Liu in view of Ooishi teaches the method of claim 1, further:
Liu teaches:
prior to bonding the subset of the first metal pads (fig 5b:531; [para 0086]) to the subset of the second metal pads (fig 5b:535; [para 0063,0089]), forming the plurality of logic devices (fig 5b:543,547; [para 0091])on the second wafer (fig 5b:541; [para 0093]).
Regarding claim 4.
Liu in view of Ooishi teaches the method of claim 1, further:
Liu teaches:
bonding the subset of the first metal pads (fig 5b:531; [para 0086,0089]) to the subset of the second metal pads (fig 5b:535; [para 0063,0089]) comprises coupling a respective LIO line (fig 5b:527; [para 0089]) of each of the plurality of memory devices (fig 5b:513; [para 0086]) to an IO line (fig 5b:537; [para 0089]) of a respective one of the plurality of logic devices fig 5b:543,547; [para 0086]).
PNG
media_image2.png
508
732
media_image2.png
Greyscale
Regarding claim 6.
Liu in view of Ooishi teaches the method of claim 1, further:
Liu teaches:
the memory-to-logic circuitry further comprises coupling the plurality of LIO lines (fig 5b:527; [para 0088]) of the memory devices (fig 5b:513; [para 0086]) to a different subset of the first metal pads (fig 5b:531; [para 0086,0089]), and wherein the different subset of the first metal pads (fig 5b:531; [para 0086,0089]) are dedicated to communication external (fig 5b:551; [para 0093]) to the wafer-on-wafer bonded memory dies (fig 5b:503; [para 0085]) and logic dies (fig 5b:505; [para 0085]).
PNG
media_image3.png
571
586
media_image3.png
Greyscale
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 2020/0328190) in view of Ooishi (US 6208547) as applied to claim 1 and further in view of Han (US 2021/0375681).
Regarding claim 8.
Liu in view of Ooishi teaches elements of the claim 1 above.
Liu teaches:
bonding the subset of the first metal pads (fig 5b:531; [para 0086,0089])to the subset of the second metal pads (fig 5b:535; [para 0063,0089])
Liu in view of Ooishi does not teach bonding four memory devices on a first wafer to one logic device having the same footprint on a second wafer.
Han teaches:
bonding such that four of the plurality of DRAM devices (fig 1c:164,166,168,170; [para 0033]) on the first wafer (fig 1c:160; [para 0033]) are aligned with and coupled to a respective one of the plurality of logic devices (fig 1c:132; [para 0033]) on the second wafer (fig 1c:100; [para 0033]), wherein four of the plurality of DRAM devices (fig 1c:164,166,168,170; [para 0033]) and one of the plurality of logic devices (fig 1c:132; [para 0033]) have a same footprint (fig 1c).
Claim(s) 9, 10, 11, 12, 14, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 2020/0328190) in view of Ooishi (US 6208547) in view of Chatterjee (US 2022/0342595)
Regarding claim 9.
Liu teaches:
A method, comprising: forming a dynamic random access memory (DRAM) array (fig 5b:513; [para 0087]) including a plurality of sense amplifiers ([para 0082]) on a memory die (fig 5b:503; [para 0085])on a first wafer (fig 5b:509; [para 0086]);
forminga logic die (fig 5b:543; [para 0093]) on a second wafer (fig 5b:541; [para 0093]);
forming a wafer-on-wafer bond (fig 5b,9a:506,909; [para 0077,0108]) between the first wafer (fig 5b:509; [para 0086]) and the second wafer (fig 5b:541; [para 0093]) including forming a connection (fig 5b:531,535; [para 0093]) between the logic die (fig 5b:543; [para 0093]) and the memory die (fig 5b:503; [para 0085]) to enable communication of data from the plurality of sense amplifiers ([para 0082]) .
PNG
media_image4.png
571
1152
media_image4.png
Greyscale
Liu does not teach the structure of the control circuitry.
Ooishi teaches
forming a dynamic random access memory (DRAM) array (fig 1:1000; [column 8 lines 9-13])including a plurality of sense amplifiers (fig 18:SA1-SA4; [column 15 lines 55-60])coupled to a common line (annotated fig 18)on a memory die (fig 1:1000; [column 15 lines 30-35]);
wherein the common line (annotated fig 18)is between the plurality of sense amplifiers (fig 18:SA1-SA4; [column 15 lines 55-60])and a local input/output (LIO) line (fig 18:M-I/O; [column 16 lines 15-20])on the memory die (fig 1:1000; [column 15 lines 30-35]);
wherein the common line (annotated fig 18)is between the plurality of sense amplifiers (fig 18:SA1-SA4; [column 15 lines 55-60])and a global input/output line (fig 18:G-I/O; [column 16 lines 30-35]) on the memory die (fig 1:1000; [column 15 lines 30-35]);
and wherein the common line (annotated fig 18), the LIO line (fig 18:M-I/O; [column 16 lines 15-20]), and the global input/output lines (fig 18:G-I/O; [column 16 lines 30-35]) are different lines (annotated fig 18); a transceiver (fig 1:1086; [column 8 lines 25-30]) coupled to an LIO line (fig 13:3006; [column 11 lines 5-15]) on a logic die (fig 13:3000; [column 11 lines 10-15]) on a second wafer; forming a wafer-on-wafer bond (fig 13:1201; [column 11 lines 10-15]) between the first wafer (fig 1:1000; [column 15 lines 30-35]) and the second wafer (fig 13:3000; [column 11 lines 10-15]) including forming a connection between the LIO line (fig 13:3006; [column 11 lines 5-15]) on the logic die (fig 13:3000; [column 11 lines 10-15]) and the common line (annotated fig 18) on the memory die (fig 1:1000; [column 15 lines 30-35]) to enable the transceiver (fig 1:1086; [column 8 lines 25-30]) to control communication of data from the plurality of sense amplifiers (fig 18:SA1-SA4; [column 15 lines 55-60]).
PNG
media_image5.png
520
994
media_image5.png
Greyscale
Liu does not teach that the structure will be used as a deep learning accelerator.
Chatterjee teaches:
forming a DRAM array (fig 1a:115; [para 0024]) and forming a deep learning accelerator ([para 0077]) on a logic die (fig 1a:130; [para 0024]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a deep learning accelerator in order to improve training of artificial intelligence models. Further, the limitation must distinguish from the prior art in terms of structure rather than function, In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); See also In re Swinehart, 439 F.2d210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971). Claims directed to apparatus must be distinguished from the prior art in terms of structure rather than function. In re Danly, 263 F. 2d 844, 847, 120 USPQ 528, 531 (CCPA 1959). “Apparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F. 2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990).
Regarding claim 10.
Liu in view of Ooishi in view of Chatterjee teaches the method of claim 9, further
Liu teaches:
prior to forming the wafer-on- wafer bond (fig 5b,9a:506,909; [para 0077,0108]), positioning the first wafer (fig 9a:902; [para 0097]) and the second wafer (fig 9a:904; [para 0097]) such that the memory die (fig 5b:503; [para 0085]) and the logic die (fig 5b:505; [para 0085])are in a face-to-face arrangement (fig 5b,9a);
and forming the wafer-on-wafer bond (fig 5b,9a:506,909; [para 0077,0108]) such that the memory die (fig 5b:503; [para 0085]) and the logic die (fig 5b:505; [para 0085]) remain in the face-to-face arrangement (fig 5b).
Regarding claim 11.
Liu in view of Ooishi in view of Chatterjee teaches the method of claim 9, further
Liu teaches:
forming the wafer-on-wafer bond (fig 5b,9a:506,909; [para 0077,0108]) comprises forming a metal material (fig 5b:531,535; [para 0089,0062])in contact with the memory die (fig 5b:503; [para 0085]) and the logic die (fig 5b:505; [para 0085]).
Regarding claim 12.
Liu in view of Ooishi in view of Chatterjee teaches the method of claim 11, further
Liu teaches:
forming the wafer-on-wafer bond (fig 5b,9a:506,909; [para 0077,0108]) further comprises annealing (thermal treatment; [para 0109])the metal material (fig 5b:531,535; [para 0089,0062]).
Regarding claim 14.
Liu in view of Ooishi in view of Chatterjee teaches the method of claim 9, further
Liu teaches:
forming the wafer-on-wafer bond (fig 5b,9a:506,909; [para 0077,0108]) comprises bonding a first metal material (fig 5b:535; [para 0089,0062]) of the logic die (fig 5b:505; [para 0085]) to a second metal material (fig 5b:531; [para 0089,0062]) of the memory die (fig 5b:503; [para 0085]).
Regarding claim 15.
Liu in view of Ooishi in view of Chatterjee teaches the method of claim 14, further
Liu teaches:
bonding the first metal material (fig 5b:535; [para 0089,0062]) and the second metal material (fig 5b:531; [para 0089,0062]) comprises merging, via a thermal process, (thermal treatment; [para 0109])the first metal material (fig 5b:535; [para 0089,0062]) and the second metal material (fig 5b:531; [para 0089,0062]) into a third metal material (fig 5b:531,535; [para 0089,0062]) in contact with the memory die (fig 5b:503; [para 0085]) and the logic die (fig 5b:505; [para 0085]).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 2020/0328190) in view of Ooishi (US 6208547) in view of Chatterjee (US 2022/0342595) as applied to claim 11 and further in view of Huang (US 2021/0242166).
Regarding claim 13.
Liu in view of Ooishi in view of Chatterjee teaches the method of claim 11, further
Liu teaches:
forming the wafer-on-wafer bond (fig 5b,9a:506,909; [para 0077,0108]) further comprises bonding the metal material (fig 5b:531,535; [para 0089,0062])to the memory die (fig 5b:503; [para 0085])and the logic die (fig 5b:505; [para 0085]) .
Liu in view of Ooishi in view of Chatterjee does not teach a room temperature bonding process.
Huang teaches:
forming the wafer-on-wafer bond further comprises bonding the metal material to the memory die and the logic die at room temperature ([para 0007]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a room temperature bonding operation in order to weaken copper oxidation during processing (Huang paragraph 7).
Claim(s) 16, 17, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (US 2020/0328180) in view of England (US 2013/0026643)
Regarding claim 16.
Cheng teaches:
A method, comprising: forming, on a substrate (fig 8a,8b:802; [para 0131]), a logic die (fig 8a,8b:808,810; [para 0131]) comprising a deep learning accelerator (DLA) ([para 0003]) thereon, wherein the DLA is distinct from other circuitry (fig 8a,8b:810; [para 0131]) of the logic die (fig 8a,8b:808,810; [para 0131]);
communicatively coupling, in a face-to-face arrangement (fig 11a,11b; [para 0114]), a first memory die (fig 11a,11b:902; [para 0118]) to the DLA;
and communicatively coupling, in the face-to-face arrangement (fig 11a,11b; [para 0114]), a second memory die (fig 11a,11b:1002; [para 0137]) to the other circuitry (fig 11a,11b:810; [para 0137]) of the logic die (fig 8a,8b:808,810; [para 0131])
Cheng does not teach that coupling is in response to a performance metric.
England teaches
A method, comprising: forming, on a substrate, a logic die comprising a deep learning accelerator (DLA) thereon, wherein the DLA is distinct from other circuitry of the logic die;
coupling a first memory die (fig 1c:110b; [para 0030])in response to the first memory die (fig 1b:110b; [para 0030]) having a first value of a performance metric (known good die; [para 0022]);
and coupling a second memory die (fig 1c:110c; [para 0030]) in response to the second memory die (fig 1c:110c; [para 0030]) having a second value of the performance metric (known good die; [para 0022])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to test for known good die in order to form a function packaged structure
Regarding claim 17.
Cheng in view of England teaches the method of claim 16, further
Cheng teaches:
comprising, prior to communicatively coupling the first and second memory dies (fig 11a,11b:902,1002; [para 0137]):
England teaches
determining that the first memory die (fig 1c:110b; [para 0030]) has the first value ([para 0022]);
and determining that the second memory die (fig 1c:110c; [para 0030]) has the second value ([para 0022]).
Regarding claim 19
Cheng in view of England teaches the method of claim 17, further
England teaches:
selecting the first and second memory dies (fig 1c:110b,c; [para 0030]) from a pool of memory dies (0022]).
Claim(s) 20 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 2020/0328190) in view of Ooishi (US 6208547)
Regarding claim 20
Liu teaches:
A method, comprising: forming a plurality of dynamic random access memory (DRAM) devices (fig 7b:704; [para 0104]), each DRAM device including a DRAM array (fig 7b:710; [para 0104]), on a first wafer (fig 7b:702; [para 0103]);
forming a plurality of logic devices (fig 8a:608; [para 0109]) on a second wafer (fig 8a:602; [para 0109]);
and forming a wafer-on-wafer bond (fig 8a,8b:802; [para 0109]) between the first wafer (fig 7b:702; [para 0103]) and the second wafer (fig 8a:602; [para 0109]), wherein forming the wafer-on-wafer bond (fig 8a,8b:802; [para 0109]) comprises: coupling memory-to-logic circuitry (fig 8b:714; [para 0105]) formed on the plurality of DRAM devices (fig 7b:704; [para 0104]) to the plurality of logic devices (fig 8a:608; [para 0109]);
providing a plurality of data paths dedicated for communication of data between the memory-to-logic circuitry (fig 8b:714; [para 0105])to the plurality of logic devices (fig 8a:608; [para 0109]);
aligning a plurality of pads (fig 8a:618; [para 0109]) of the second wafer (fig 8a:602; [para 0109]) coupled to the plurality of logic devices (fig 8a:608; [para 0109]) .
PNG
media_image6.png
480
1013
media_image6.png
Greyscale
Liu does not teach control circuitry on the first wafer in the embodiment.
Ooishi teaches:
a plurality of transceivers (fig 1:1086; [column 8 lines 20-25]) of the first wafer (fig 2:10; [column 8 lines 35-45]) that control whether the data is communicated via the plurality of data paths (fig 1:I/O; [column 8 lines 20-30]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the first wafer with transceiver circuitry in order to detect signals from the DRAM elements and amplify the signals to enable transmission to the logic devices on the second substrate.
Regarding claim 22
Liu in view of Ooishi teaches the method of claim 20, further
Liu teaches:
forming the wafer-on-wafer bond (fig 8b:802; [para 0109]) comprises forming a metal material (fig 8a:618,718; [para 0100,0106]) in contact with the plurality of DRAM devices (fig 7b:704; [para 0104]) and the plurality of logic devices (fig 8a:608; [para 0109]).
Claim(s) 23, 24, and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hedler (US 2009/0321959) in view of Yu (US 2022/0262783)
Regarding claim 23.
Hedler teaches:
A method, comprising: f
;
bonding the stack of memory dies (fig 5a:2000; [para 0068]) to a substrate (fig 5d:4000; [para 0071]), wherein the first memory die is proximal to the substrate (fig 5d:4000; [para 0071]) and the last memory die distal to the substrate (fig 5d:4000; [para 0071]);
and bonding a logic die (fig 5d:10; [para 0070]) to the substrate (fig 5d:4000; [para 0071]) with a plurality of bump contacts (fig 5d:1001; [para 0072]) directly contacting the logic die (fig 5d:10; [para 0070]) and the substrate (fig 5d:4000; [para 0071]) and being in-plane with the stack of memory dies (fig 5a:2000; [para 0068]), wherein the logic die (fig 5d:10; [para 0070]) is in contact with the last memory die.
PNG
media_image7.png
401
888
media_image7.png
Greyscale
Hedler does not teach how the memory stack is made.
Yu teaches:
A method, comprising: forming a wafer-on-wafer bond between a first wafer (fig 2c,2d:56a; [para 0031]) including a first memory die (fig 2c,2d:10a; [para 0031]) and a last wafer (fig 2c,2d:56h; [para 0040]) including a last memory die (fig 2c,2d:10h ; [para 0040]);
singulating ([para 0040]) the bonded first and last wafers (fig 2c,2d:56a,56h; [para 0040]) into individual a wafer-on-wafer bonded stack of memory dies (fig 2d:50; [para 0050]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a stack of memory die by bonding memory die wafers in order that an electrical connection can be formed between each die thereby forming a functional memory cube.
Regarding claim 24.
Hedler in view of Yu teaches the method of claim 23, further
Hedler teaches:
forming the plurality of bump contacts (fig 5d:1001; [para 0072]) as a ball grid array (BGA) on the substrate (fig 5d:4000; [para 0071]).
Regarding claim 25.
Hedler in view of Yu teaches the method of claim 23, further
Hedler teaches:
bonding the stack of memory dies (fig 5a:2000; [para 0068]) and bonding the logic die (fig 5d:10; [para 0070]) comprises: bonding a first surface of the respective last memory die to another memory die of the stack of memory dies (fig 5a:2000; [para 0068]);
and bonding a second surface of the respective last memory die, opposite the first surface, to the logic die (fig 5d:10; [para 0070]).
PNG
media_image7.png
401
888
media_image7.png
Greyscale
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed 3/16/2026 have been fully considered but they are not persuasive.
The applicant argues that the prior art does not couple in response to a metric (page 9).
However, newly applied combination Cheng (US 2020/0328180) in view of England (US 2013/0026643) anticipates the limitation, coupling is performed in response to the metric of good.
The applicant argues that Liu does not teach that transceiver (peripheral circuitry) is on the second wafer (page 10,11). However, Liu teaches an embodiment wherein the peripheral circuitry is on both (first and second) die in order to distribute the circuitry (see above).
The applicant argues that the prior art does not teach separate common line, local line, and global line (page 12).
However, Ooishi teaches this limitation, see annotated figure 18 in the rejection above.
The applicant argues that the prior art does not teach that the DRAM device comprises a DRAM array (page 14).
However, Liu explicitly refers to the DRAM cells as an array (a group of elements forming a unit) (paragraph 104 cited in rejection above).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
Prosecution Insights