Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II, claims 6-11, in the reply filed on 03/13/2025 is acknowledged. Claims 6-11 will be examined on the merits below (noting that claims 7 and 8 have been canceled).
Claim Objections
Claim 6 objected to because of the following informalities: Spelling errors. opitaxial in the second subparagraph, and “type buries layer part A is a..” in the third subparagraph. Appropriate correction is required.
Response to Arguments
Applicant's arguments filed 08/06/2025 have been fully considered but they are not persuasive. Regarding the amendments to the U.S.C. 112 rejection, it is understood that the claim is trying to identify the environment of which it can operate. The specific amendments to define the environment overcome the previous 112(b) rejection, however a new 112(b) rejection is formed due to some of the unclear claim language.
Regarding the applicants’ arguments on page 9, paragraph 1, with regards to Siddiqui being a different device than the Applicant’s disclosure, it is understood that the claim language can read onto the Siddiqui reference since Siddiqui clearly articulates a level-shift-region, isolation region and a high voltage region (paragraphs 0043-0044), where element 208 (the high side region) is understood to be the high-voltage region. The structure may not be exact to the drawings of the applicant, but the claim language reads onto Siddiqui and thus it is adequate for rejection of the claims according one of ordinary skill in the art. Thus, the Applicant’s argument is not persuassive.
Regarding the Applicant’s argument in paragraph 2, page 9 of the office action, the applicant is right that Mallikarjunaswamy does not teach the location of the p-buried layers and neither did the non-final rejection on 05/07/2025 claim it did. It is Siddiqui that teaches such limitations, and thus reading Kim and Mallikarjunaswamy in view of Siddiqui one of ordinary skill in the art would locate the already taught limitations of Mallikarjunaswamy in a new location according to how Siddiqui with the motivation as discussed on page 7 of the office action, that by locating the p-type buried regions in a certain location it creates protection for the other devices as mentioned in Siddiqui. Thus, the examiner finds the Applicant’s arguments not persuasive.
Regarding the applicants’ arguments on page 10, paragraph 1, keep in mind that one can only claim a device or a method. It was disclosed in the office action sent on 05/07/2025 that the limitations of how a layer if formed is a product-by-process claim and thus only the resulting product is examined. One could form the layer with different energies, and claim such formation, but only the resultant product is examined. Thus, the applicant is correct in asserting that Kim forms the structure in a different way than the applicant forms their structure, but nonetheless, the resultant product of Kim matches the claimed limitations of the product. Thus, the examiner finds the applicants arguments not persuasive.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In regard to claim 6, the claim directs to a high-voltage isolation semiconductor device then further claims “the substrate layer comprises” yet the substrate layer is not within the bounds of the high-voltage isolation semiconductor device as later in claim 6 it states, “the high-voltage isolation semiconductor device comprises…” of which there is no mention of “the substrate layer.” Additionally, there are multiple places where a limitation is not introduced but referenced as “the…” and then later introduced with “a.” The examiner encourages the applicant to structure the claims such that, for example, “a substrate layer comprising…” then after the substrate layer limitations are written one can use the phrase “the substrate layer.” Since Applicant is claiming “A high voltage isolation semiconductor device” as the claim then attempts to claim a substrate that is not part of the “high voltage isolation semiconductor device” would those limitations be part of the scope of the ‘high voltage isolation semiconductor device’? Therefore, the scope of what is being claimed is unclear. The examiner recommends the applicant take the following approach:
A semiconductor comprising:
a substrate including a first conductivity type substrate ….;
a high-voltage isolation semiconductor device located in the substrate ….;
Taking this form would overcome the 112(b) rejection of the claim language being unclear.
Claims 7-11 include all the limitations from claim 6, therefore, are also rejected as described above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 8445357 B2) in view of Mallikarjunaswamy (US 20190157257 A1) and in further view of Siddiqui et al (US 20180190816 A1).
Regarding claim 6, Kim et al teaches
[claim 6]
the substrate layer comprising a first conductivity type substrate and a second conductivity type epitaxial layer, the second conductivity type epitaxial layer being formed on the first conductivity type substrate (figure 8, element 110 is the substrate of first conductivity type [p-type] and element 120 is the epitaxial layer formed on the substrate of second conductivity type [n-type]),
the high-voltage isolation semiconductor device comprises a first conductivity type buried layer part A, a first conductivity type buried layer part B, and a first conductivity type well region (figure 8, element 136 is the buried layer part B of first conductivity type [p-type] and element 130 is the buried layer part A of the first conductivity type, well region 146);
the first conductivity typer buried layer part A is formed by performing first conductivity type ion implantation by means of first implantation energy ranging from 1500 Kev to 3000 Kev, the first conductivity type buried layer part B is formed by performing first conductivity type ion implantation by means of a second implantation energy ranging from 50 Kev to 100 Kev (product-by-process limitations, thus only the resultant product is examined, which is stated already in the claim language),
the first conductivity type buried layer part B is located at an adjoining surface of the first conductivity type substrate and the second conductivity type epitaxial layer, a lower portion of the first conductivity type buried layer part B extends into the first conductivity type substrate, and an upper portion of the first conductivity type buried layer part B extends into the second conductivity type epitaxial layer (figure 8, element 136 [buried layer part B] extends down into the substrate and also up into the epitaxial layer and is at a border between the two layers);
and the first conductivity type well region is located in the second conductivity type epitaxial layer, and the first conductivity type well region extends downwards to contact the first conductivity type buried layer part B (figure 8, element 146 is the well region located in the epitaxial layer [element 120] and extends down to touch the buried layer part B [element 136]).
However, Kim et al does not specifically disclose
[claim 6] A high-voltage isolation semiconductor device, wherein the high-voltage isolation semiconductor device is located in an isolation region of a substrate layer, and the isolation region is isolated between a high-voltage device region and a level shift region of the substrate layer;
the first conductivity type buried layer part A is located in the first conductivity type substrate, and the first conductivity type buried layer part A extends upwards to contact the first conductivity type buried layer part B;
However, Mallikarjunaswamy teaches
[claim 6] the first conductivity type buried layer part A is located in the first conductivity type substrate, and the first conductivity type buried layer part A extends upwards to contact the first conductivity type buried layer part B (figure 15, element 132 is the buried layer part A situated in the substrate and extends up to the buried layer part B [element 108]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Kim et al to incorporate the teachings of Mallikarjunaswamy in order to create a stacked buried layer to create a higher breakdown voltage threshold in order to protect any attached circuit better from any high ESD effects.
However, Kim et al. as modified still does not specifically disclose
[claim 6] A high-voltage isolation semiconductor device, wherein the high-voltage isolation semiconductor device is located in an isolation region of a substrate layer, and the isolation region is isolated between a high-voltage device region and a level shift region of the substrate layer;
However, Siddiqui teaches
[claim 6] A high-voltage isolation semiconductor device, wherein the high-voltage isolation semiconductor device is located in an isolation region of a substrate layer, and the isolation region is isolated between a high-voltage device region and a level shift region of the substrate layer (figure 3, paragraphs 0045-0048, where section 204 is a level shift region, the high voltage isolation device is region 206 and the high voltage region is region 208, where the high-voltage isolation region is situated between elements 204 and 208, the level shift region and the high voltage region).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Kim et al as modified above to incorporate the teachings of Siddiqui et al in order to create protection from a lower voltage semiconductor device by situating a high-voltage isolation region between the high voltage region and a level shift region so no extra ESD effects could disrupt the lower voltage region which is near the level shift region.
Regarding claim 11, Kim as modified further discloses the high-voltage isolation semiconductor device according to claim 6, wherein a second conductivity type buried layer is formed in the substrate layer on at least one side of the high-voltage isolation semiconductor device, and the second conductivity type buried layer is located at the adjoining surface of the first conductivity type substrate and the second conductivity type epitaxial layer; and a lower portion of the second conductivity type buried layer extends into the first conductivity type substrate, and an upper portion of the same extends into the second conductivity type epitaxial layer (figure 8, element 132 is the buried layer of the second conductivity type and the lower portion extends into the substrate and the upper portion extends into the epitaxial layer and is located at the adjoining surface of the substrate and an epitaxial layer and is formed in the high-voltage isolation region of the semiconductor device).
Claim(s) 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 8445357 B2), Mallikarjunaswamy (US 20190157257 A1), and Siddiqui et al (US 20180190816 A1) in further view of Kim et al (US 20170148873 A1).
Kim et al (357) as modified teaches all of the limitations of the parent claim, claim 6, but does not specifically disclose
[claim 9] The high-voltage isolation semiconductor device according to claim 6, wherein a field oxide layer covers at least the first conductivity type epitaxial layer at the position of the isolation region.
[claim 10] The high-voltage isolation semiconductor device according to claim 9, wherein the first conductivity type well region extends upwards to contact the field oxide layer.
However, Kim et al (873) teaches
[claim 9] The high-voltage isolation semiconductor device according to claim 6, wherein a field oxide layer covers at least the first conductivity type epitaxial layer at the position of the isolation region (figure 2, paragraph 0068, where element 178 is the field oxide layer and covers the epitaxial layer [element 116 per paragraph 0057, may be grown epitaxially] within the isolation region [region spanning the width of element 142]).
[claim 10] The high-voltage isolation semiconductor device according to claim 9, wherein the first conductivity type well region extends upwards to contact the field oxide layer (figure 2, paragraph 0065, element 124 is the well region and extends upwards towards the field oxide layer [element 178]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Kim et al (357) with the teachings of Kim et al (873) to incorporate the oxide field layer in the specific region in order to increase the transistors voltage threshold in the off state so as to minimize the ESD from any excess voltage from the circuit while the transistor is in the off state.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Baek (US 20200373293 A1), Kang et al (US 20200343145 A1), Yamaji (US 20200161418 A1), and Yue et al (US 20160240660 A1).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached at 572-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANDREW ZABEL/ Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818
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