DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 13, 2026 has been entered.
Election/Restrictions
Claims 1-22 are pending in this application.
Applicant elected without traverse of Group I, species, B, C, D, 2, and 3 (claims 1-2, 4, 6-8, and 11-15) in the reply filed on April 28, 2025.
Claims 3, 5, 9, 10, and 16-22 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention and/or species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on April 28, 2025.
The Examiner notes that claims 1-2, 4, 6-8, and 11-15 are examined and claims 3, 5, 9, 10, and 16-22 are withdrawn.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed March 13, 2026. Claims 1, 7, and 13 are amended. Claims 3, 5, 9, 10, and 16-22 remain withdrawn. The Examiner notes that claims 1-2, 4, 6-8, and 11-15 are examined.
Claim objections of claims 13-15 are withdrawn because amendment fixed minor informalities.
Claim Rejections - 35 USC § 103
Claims 1, 2, 4, 6-8, and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Hinoue (US 2021/0408025 A1) in view of Kato (US 2020/0303300 A1) and Ravikirthi (US 9,881,929 B1).
With respect to claim 1, Hinoue teaches in Fig. 22B:
An apparatus comprising:
first tiers (insulating layers 132 and 232, electrically conductive layers 146 and 246 above the dielectric structure in a plan view, see annotated Fig. 18B below for assignment of “first” and “second” tiers) located one over another (232/246 are over 132/146, and 232/246 are further over each other while 132/146 are also over each other),
the first tiers including respective first memory cells (memory cells located in the memory array region 100, including memory film 50 extending through the first tiers) and first control gates for the memory cells (para. 154 “A subset of the electrically conductive layers (146, 246) may comprise word lines for the memory elements”),
the first memory cells (cells associated with each word line 146, 246 that comprises memory film 50) located along respective first pillars (memory opening fill structures 58, labeled in Fig. 11), the first pillars extending through the first tiers (58 extends through 132, 146, 242, 246);
a conductive contact (staircase region contact via structures 86) contacting one of the control gates (146, 246), the conductive contact having a length extending in the same direction as the first pillars;
support structures (support pillar structures 20) extending through the first tiers,
wherein the support structures include four support structures (see Fig. 22B, each contact 86 has four nearest neighbor supports 20), and each of the four support structures is a neighbor of the conductive contact (see Fig. 22B);
second tiers (insulating layers 132 and 232, electrically conductive layers 146 and 246 below the dielectric structure in a plan view, see annotated Fig. 18B below for assignment of “first” and “second” tiers) located one over another (232/246 are over 132/146, and 232/246 are further over each other while 132/146 are also over each other),
the second tiers including respective first memory cells (memory cells located in the memory array region 100, including memory film 50 extending through the first tiers) and first control gates for the memory cells (para. 154 “A subset of the electrically conductive layers (146, 246) may comprise word lines for the memory elements”),
the second memory cells (cells associated with each word line 146, 246 that comprises memory film 50) located along respective second pillars (memory opening fill structures 58, labeled in Fig. 11), the second pillars extending through the second tiers (58 extends through 132, 146, 242, 246);
and a dielectric structure (dielectric backside trench fill structure 176) formed in a slit (backside trench 179) between the first tiers and the second tiers the dielectric structure including an edge (top edge) along a length of the slit and adjacent the first tiers wherein the edge has a repeating pattern of a shape (para. 155 “a dielectric material can be deposited in the backside trenches 179”, annotated Fig. 18B below shows the edges of 179, which have a curved repeating pattern)
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Hinoue fails to teach:
and a first select gate and a second select gate associated with the first memory cells
wherein a support of the support structures has a length extending from the first select gate to the second select gate
and the support structure has a cross-section perpendicular to the length of the support structure, and the cross section has a non-circular shape.
wherein the support structures include four support structures having lengths extending from the first select gate to the second select gate
Kato teaches in Fig. 8:
and a first select gate (select gate line SGD) and a second select gate (select gate line SGS) associated with the first memory cells
support structures (support pillars HR) extending through the first tiers,
wherein a support of the support structures has a length extending from the first select gate to the second select gate (HR extends through both SGD and SGS),
Hinoue modified by Kato such that each support structure extends from a first select gate to a second select gate teaches:
wherein the support structures include four support structures having lengths extending from the first select gate to the second select gate
Hinoue discloses the claimed invention except that Hinoue does not specify the locations of all the select gates or teach a support structure through them. Kato discloses that it is known in the art to provide a select drain gates and select source gates at either side of a memory stack with a support pillar extending from one select gate to the other. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the structure of Hinoue with the select gates and support structure of Kato for the purpose of being able to turn on and off the memory cells and provide structural support to prevent warpage during the manufacture of the device. See MPEP 2144.
Ravikirthi teaches:
and the support structure has a cross-section perpendicular to the length of the support structure, and the cross section has a non-circular shape. (col 29, lns. 56-58 “and each of the second support pillar structures 155 has a second horizontal cross-sectional shape (such as an ellipse, a second polygon, or a circle”.)
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have modified the support structures of Hinoue/Kato to be non-circular as taught by Ravikirthi, since it has been held that adjusting the shape of an article involves only routine skill in the art. In re Dailey, 149 USPQ 47 (CCPA 1966). See MPEP 2144.04.
With respect to claim 2, Hinoue further teaches:
wherein the edge of the dielectric structure (top edge of 176 in a plan view) is a first edge,
and wherein the dielectric structure (176 within 179) includes a second edge (bottom edge of 176/179 in a plan view) along the length of the slit and adjacent the second tiers and the second edge has the repeating pattern of a shape (repeating curved shape).
With respect to claim 4, Hinoue further teaches:
wherein the repeating pattern includes curved segments (see Fig. 18B, 179 has repeating pattern of curved segments)
With respect to claim 6, Hinoue further teaches:
wherein the first control gates (146, 246) include respective portions that collectively form a staircase structure (146 and 246 extend into staircase region 200),
wherein the edge of the dielectric structure includes a portion adjacent the staircase structure (see Fig. 18B, dielectric region extends into 200).
With respect to claim 7, Hinoue teaches:
An apparatus comprising:
tiers (insulating layers 132 and 232, electrically conductive layers 146 and 246 above the dielectric structure in a plan view, see annotated Fig. 18B above) located one over another (232/246 are over 132/146, and 232/246 are further over each other while 132/146 are also over each other),
the tiers including respective first memory cells (memory cells located in the memory array region 100, including memory film 50 extending through the first tiers) and control gates for the memory cells (para. 154 “A subset of the electrically conductive layers (146, 246) may comprise word lines for the memory elements”),
the memory cells located along respective pillars, the pillars extending in a direction from one tier to another tier among the tiers (memory cells occur where word lines meet the pillars);
conductive contacts (conductive via structures 86, Fig. 22B) contacting the control gates (246 and 146), the conductive contacts having different lengths extending in the same direction as the pillars (86 extends in the up/down direction and each have different lengths, see Fig. 22A);
and support structures (support pillar structures 20) adjacent the conductive contacts (86, see Fig. 22B) and electrically separated (surrounded by dielectric material portion 265) from the control gates (146 and 246) and the conductive contacts (86), the support structures extending in the same direction as the conductive contacts (both extend in the up/down direction),
wherein the support structures include four support structures (see Fig. 22B, each contact 86 has four nearest neighbor supports 20) having lengths extending from the first select gate to the second select gate, and each of the four support structures is a neighbor of the conductive contact (see Fig. 22B);
Hinoue fails to teach:
the control gates located between a first select gate associated with the memory cells and a second select gate associated with the memory cells
wherein a support of the support structures has a length extending from the first select gate to the second select gate
wherein a support of the support structures has a cross-section perpendicular to the length of the support structure, and the cross-section has a non-circular shape
wherein the support structures include four support structures having lengths extending from the first select gate to the second select gate
Kato teaches in Fig. 8:
the control gates located between a first select gate (select gate line SGD) and a second select gate (select gate line SGS) associated with the memory cells
support structures (support pillars HR) extending through the first tiers,
wherein a support of the support structures has a length extending from the first select gate to the second select gate (HR extends through both SGD and SGS),
Hinoue modified by Kato such that each support structure extends from a first select gate to a second select gate teaches:
wherein the support structures include four support structures having lengths extending from the first select gate to the second select gate
Hinoue discloses the claimed invention except that Hinoue does not specify the locations of all the select gates or teach a support structure through them. Kato discloses that it is known in the art to provide a select drain gates and select source gates at either side of a memory stack with a support pillar extending from one select gate to the other. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the structure of Hinoue with the select gates and support structure of Kato for the purpose of being able to turn on and off the memory cells and provide structural support to prevent warpage during the manufacture of the device. See MPEP 2144.
Ravikirthi teaches:
wherein a support of the support structures has a cross-section perpendicular to the length of the support structure, and the cross-section has a non-circular shape (col 29, lns. 56-58 “and each of the second support pillar structures 155 has a second horizontal cross-sectional shape (such as an ellipse, a second polygon, or a circle”.)
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have modified the support structures of Hinoue/Kato to be non-circular as taught by Ravikirthi, since it has been held that adjusting the shape of an article involves only routine skill in the art. In re Dailey, 149 USPQ 47 (CCPA 1966). See MPEP 2144.04.
With respect to claim 8, Ravikirthi further teaches:
wherein the non-circular shape is a polygon. (col 29, lns. 56-58 “and each of the second support pillar structures 155 has a second horizontal cross-sectional shape (such as an ellipse, a second polygon, or a circle”.)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Hinoue in view of Kato and Ravikirthi as explained above.
With respect to claim 11, Hinoue further teaches:
wherein the control gates (146 and 246) include respective portions that collectively form a staircase structure (see Fig. 22A), and the conductive contacts (86) contact the control gates at a location of the staircase structure (each of 86 contacts the top of a control gate at an individual stair step).
With respect to claim 12, Hineoue further teaches:
wherein the support structures (20) have the same length, and the conductive contacts (86) have difference lengths (see Fig. 22A).
With respect to claim 13, Hinoue teaches in Figs. 22A-B:
An apparatus comprising:
a block of memory cells (memory array region 100) including levels of dielectric materials (insulating layers 132 and 232) interleaved with levels of conductive materials (conductive layers 146 and 246),
the levels of conductive materials (146, 246) forming control gates for the memory cells ([0153] “A subset of the electrically conductive layer (146, 246) located underneath the drain select gate electrodes may function as combinations of a control gate and a word line located at the same level”), the levels of conductive materials including respective portions that collectively form a staircase structure (staircase region 200);
conductive contacts (contact via structure 86) contacting the levels of conductive (146, 246) materials at a location of the staircase structure (Fig. 23B),
the conductive contacts having different lengths extending in a direction from one level to another level among the levels of dielectric materials (see Fig. 22A, each of the conductive vias 86 has a different length and extends from the contact level dielectric layer 80 with the bottom of each instance of 86 coplanar with the bottom of one of the layers 132 or 232);
support structures (support pillar structures 20) adjacent the conductive contacts (86, see Fig. 22B) and electrically separated (surrounded by dielectric material portion 265) from the control gates (146 and 246) and the conductive contacts (86), the support structures extending in the same direction as the conductive contacts (both extend in the up/down direction),
wherein the support structures include four support structures (see Fig. 22B, each contact 86 has four nearest neighbor supports 20), and each of the four support structures is a neighbor of a selected conductive contact of the conductive contacts (see Fig. 22B);
and a dielectric structure (dielectric backside trench fill structure 176) formed in a slit (backside trench 179) adjacent the block of memory cells,
the dielectric structure including an edge along a length of the slit and adjacent the first block of memory cells, wherein the edge has a repeating pattern of a shape (para. 155 “a dielectric material can be deposited in the backside trenches 179”, annotated Fig. 18B below shows the edges of 179, which have a curved repeating pattern)
Hinoue fails to teach:
the control gates located between a first select gate associated with the memory cells and a second select gate associated with the memory cells
wherein a support structure of the support structures has a length extending from the first select gate to the second select gate
wherein the support structures include four support structures having lengths extending from the first select gate to the second select gate
wherein a support of the support structures has a cross-section, and the cross-section has a non-circular shape
Kato teaches in Fig. 8:
the control gates (word lines 24, para. 53, “control gates of the memory cell transistors MT0 to MT15 are coupled in common to respective word lines WL0 to WL15”) located between a first select gate (select gate SGD) associated with the memory cells and a second select gate (select gate SGS) associated with the memory cells
wherein a support of the support structures (support pillar HR) has a length extending from the first select gate to the second select gate (see Fig. 8, HR extends from SGD to SGS)
Hinoue modified by Kato such that each support structure extends from a first select gate to a second select gate teaches:
wherein the support structures include four support structures having lengths extending from the first select gate to the second select gate
Hinoue discloses the claimed invention except that Hinoue does not specify the locations of all the select gates or teach a support structure through them. Kato discloses that it is known in the art to provide a select drain gates and select source gates at either side of a memory stack with a support pillar extending from one select gate to the other. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the structure of Hinoue with the select gates and support structure of Kato for the purpose of being able to turn on and off the memory cells and provide structural support to prevent warpage during the manufacture of the device. See MPEP 2144.
Ravikirthi teaches:
wherein a support of the support structures has a cross-section, and the cross-section has a non-circular shape (col 29, lns. 56-58 “and each of the second support pillar structures 155 has a second horizontal cross-sectional shape (such as an ellipse, a second polygon, or a circle”.)
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have modified the support structures of Hinoue/Kato to be non-circular as taught by Ravikirthi, since it has been held that adjusting the shape of an article involves only routine skill in the art. In re Dailey, 149 USPQ 47 (CCPA 1966). See MPEP 2144.04.
With respect to claim 14, Hinoue further teaches:
wherein the edge of the dielectric structure (top edge of 176/179 in a plan view) is a first edge,
and wherein the dielectric structure includes a second edge opposite the first edge and along the length of the slit (bottom edge of 176/179 in a plan view),
and the second edge has an additional repeating pattern of a shape (bottom edge also includes a curved repeating pattern).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Ravikirthi in view of Hinoue and Kato as explained above.
With respect to claim 15, Hinoue further teaches:
wherein the control gates (146/246 of Hinoue) include respective portions that collectively form a staircase structure (200), wherein the edge is adjacent the staircase structure (Fig. 18B, edge of 176/179 extends into the staircase structure 200 and is adjacent to the staircase).
Response to Arguments
Applicant’s arguments with respect to claims 1, 7, and 13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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