DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The 03/03/2026 amendments of claims 1, 4, 6, 8-10, 22-24, and 27 have been noted and entered.
The 03/03/2026 cancellation of claims 5, 12 and 26 has been noted and entered.
The 03/03/2026 addition of new claims 30-32 has been noted and entered.
Response to Arguments
Applicant’s arguments, see Remarks pages 7-10, filed 03/03/2026, with respect to the rejection of claims 1-8 and 21-24 under 35 U.S.C. 103 have been fully considered and are persuasive in light of the newly added amendments. The rejections of record have been withdrawn.
Applicant’s arguments, see Remarks pages 10-12, filed 03/03/2026, with respect to the rejection(s) of claim(s) 9-10, 12 and 25-29 under 35 U.S.C. 103 have been fully considered and are persuasive in light of the newly added amendments. However, upon further consideration, a new ground(s) of rejection is made in view of Hwang et al, US 20220069100 A1 (Hwang), Xie et al, US 20230178433 A1 (Xie) and Borthakur et al, US 20150243699 A1 (Borthakur).
New Grounds of Rejection
New grounds of rejection, prior art references Hwang et al, US 20220069100 A1 (Hwang), Xie et al, US 20230178433 A1 (Xie) and Borthakur et al, US 20150243699 A1 (Borthakur) appear below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 9 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al, US 20220069100 A1 (Hwang) in view of Xie et al, US 20230178433 A1 (Xie).
Regarding claim 9; Hwang teaches a semiconductor device comprising:
at least one transistor (Hwang: [0019]), a front side structure (Annotated Fig (11) shared in this OA: 255), and a back side structure (220) comprising a buried power rail (BPR), the front side structure (255) being disposed opposite to the back side structure (220) with respect to the transistor; and
a front via (253 + 235) formed at a side of the transistor and connecting the front side structure (255) to the BPR (220),
wherein the front via (253 + 235) is distinct from the BPR (220), the front via (253 + 235) comprising a lower front via (235) that terminates on the BPR (220) and an upper front via (253) on the lower front via (235),
wherein the lower front via (235) and the upper front via (253) are respectively formed in a lower via hole (VH1) and an upper via hole (VH2) which are vertically and directly connected to each other, and
wherein a width of a bottom surface (width of the bottom surface (along -Z-direction) of 253) of the upper front via (253) is different from a width of a top surface (width of the top surface (along +Z-direction) of 235) of the lower front via (235).
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Hwang teaches a front via connecting a front structure to a back structure in a semiconductor device but fails to disclose the relative location of the transistor compared to the vias and the front and back structures. Thus, Hwang fails to teach the front side structure being disposed opposite to the back side structure with respect to the transistor; and a front via formed at a side of the transistor.
Xie teaches the front side structure (Xie: Annotated Fig (14) shared in this OA: 56) being disposed opposite to the back side structure (74) with respect to the transistor (50); and a front via (Front Via) formed at a side of the transistor (50).
Hwang and Xie are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to one of ordinary skill in the art, to modify Hwang by introducing the front and back structures and the front via in the positions disclosed in Xie to achieve the predictable result of making connecting the transistor to power lines easier and more efficient thus leading to a more efficient device and a device construction process that is more reliable.
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Regarding claim 25; Hwang in view of Xie teaches all the limitations of the semiconductor device of claim 9.
Further, Hwang teaches wherein the width of the bottom surface (Hwang: Annotated Fig (11) shared in this OA: width of the bottom surface (along - Z-direction) of 253) of the upper front via is less than the width of the top surface (width of the top surface (along +Z-direction) of 235) of the lower front via (235).
Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al, US 20220069100 A1 (Hwang) in view of Xie et al, US 20230178433 A1 (Xie) in further view of Borthakur et al, US 20150243699 A1 (Borthakur).
Regarding claim 32; Hwang in view of Xie teaches all the limitations of the semiconductor device of claim 9
Hwang in view of Xie does not teach wherein a first portion of the upper front via extends into a shallow trench isolation (STI) structure adjacent to the transistor, and a second portion of the upper front via is on a top surface of the STI structure, and wherein a vertical thickness of the first portion of the upper front via is less than a vertical thickness of the second portion of the upper front via.
Borthakur teaches wherein a first portion of the upper front via (Borthakur: Annotated Fig (2) shared in this OA: 42) extends into a shallow trench isolation (STI) structure (28) adjacent to the transistor ([0022]), and a second portion of the upper front via is on a top surface of the STI structure, and wherein a vertical thickness of the first portion (Thickness of First Portion of the Front Via) of the upper front via (42) is less than a vertical thickness of the second portion (Thickness of second Portion of the Front Via) of the upper front via (42).
Hwang in view of Xie and Borthakur are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Hwang in view of Xie by constructing the front via to pass through the shallow trench isolation region to further improve the isolation of the vias and reduce the possibility of a short circuit leading to a more reliable device.
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Allowable Subject Matter
Claims 1-4, 6-8, 21-24 and 27-31 are allowable over prior art.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1; Hwang in view of Xie teaches a semiconductor device comprising: at least one transistor, a front side structure, and a back side structure comprising a buried power rail (BPR), the front side structure being disposed opposite to the back side structure with respect to the transistor; and a front via formed at a side of the transistor and connecting the front side structure to the BPR, wherein the front via is distinct from the BPR and is formed in a via hole, the via hole comprising a lower via hole that extends to a top surface of the BPR and an upper via hole on the lower via hole, wherein a side surface of the front via has a step profile where the lower via hole is connected to the upper via hole, and wherein the front via extends into a shallow trench isolation (STI) structure adjacent to the transistor.
However, Hwang alone or in combination with other available art does not teach such that the step profile of the side surface of the front via is recessed relative to a top surface of the STI structure and is vertically spaced apart from the BPR in a manner that can be reasonably combined with the rest of the limitations listed above.
Claims 2-4, 6-8, 21-24 and 30-31 are allowable for their dependence on an allowable base claim.
Regarding claim 27; Hwang in view of Xie in further view of other available art such as Nosho et al, US 20180342455 A1 (Nosho) teaches A semiconductor device comprising: at least one transistor, a front side structure, and a back side structure comprising a buried power rail (BPR), the front side structure being disposed opposite to the back side structure with respect to the transistor; and a front via formed at a side of the transistor and connecting the front side structure to the BPR, wherein the front via is distinct from the BPR, the front via comprising a lower front via on the BPR and an upper front via on the lower front via, wherein a connection surface comprising a silicide layer is between the lower front via and the upper front via.
However, Hwang alone or in combination with any other available art does not teach wherein a width of the silicide layer is less than or equal to a width of a top surface of the lower front via, and wherein an interlayer dielectric (ILD) structure is directly on a side surface of the upper front via, without a silicide layer therebetween in a manner that can be reasonably combined with the rest of the limitations listed above.
Claims 28-29 are allowable for their dependence on an allowable base claim.
Claim 10 is objected to as being dependent upon a rejected base claim (claim 9), but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 10; Hwang in view of Xie in further view of other available art such as Nosho et al, US 20180342455 A1 (Nosho) teaches wherein a connection surface comprising a silicide layer is between the lower front via and the upper front via.
However, Hwang alone or in combination with other available art does not teach wherein a width of the silicide layer is less than or equal to a width of the top surface of the lower front via, and wherein an interlayer dielectric (ILD) structure is directly on a side surface of the upper front via, without a silicide layer therebetween in a manner that can be reasonably combined with the rest of the limitations listed above.
Conclusion
Prior art references made of record but not relied upon are considered pertinent to the applicant’s disclosure.
Nosho et al, US 20180342455 A1 (Nosho) teaches a silicide layer between an upper and lower front vias.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/M.K./Examiner, Art Unit 2817 /NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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