DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The 06/16/2026 amendment of claim 9 is noted and entered.
The 06/16/2026 cancellation of claim 10 is noted and entered.
Response to Arguments
Applicant’s arguments, see Remarks page 7, filed 06/16/2026, with respect to the rejection of claims 9-10, 25 and 32 under 35 U.S.C. 103 have been fully considered and are persuasive in light of the newly added amendments. However, upon further consideration, a new ground(s) of rejection is made in view of Gambino et al, US 9455187 B1 (Gambino).
Additionally, the previously indicated allowability of claims 1, 10 and 27 is withdrawn in light of the new grounds of rejection leading to this office action being a Non-Final Office Action.
New Grounds of Rejection
New grounds of rejection, Gambino et al, US 9455187 B1 (Gambino).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 1, 3-4, 7-9, 22-25, 27-29 and 30-31 are rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al, US 20220069100 A1 (Hwang) in view of Xie et al, US 20230178433 A1 (Xie ‘433) in further view of Gambino et al, US 9455187 B1 (Gambino).
Regarding claim 1; Hwang teaches a semiconductor device comprising:
at least one transistor (Hwang: [0019]), a front side structure (Annotated Fig (11) shared in this OA: 255), and a back side structure (220) comprising a buried power rail (BPR), the front side structure (255) being disposed opposite to the back side structure (220) with respect to the transistor; and
a front via (253 + 230) formed at a side of the transistor and connecting the front side (255) structure to the BPR (220),
wherein the front via (253 + 230) is distinct from the BPR (220) and is formed in a via hole (the hole containing 253+230), the via hole comprising a lower via hole (hole that contains 230) that extends to a top surface of the BPR (220) and an upper via hole (hole that contains 253) on the lower via hole (hole that contains 230),
wherein a side surface of the front via (230+253) has a step profile (First Step Profile) where the lower via hole (hole containing 230) is connected to the upper via hole (hole containing 253), and wherein the front via (230+253) extends into a shallow trench isolation (STI) structure (212) adjacent to the transistor,
such that the step profile of the side surface of the front via is recessed relative to a top surface of the STI structure and is vertically spaced apart from the BPR.
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Hwang teaches a front via connecting a front structure to a back structure in a semiconductor device but fails to disclose the relative location of the transistor compared to the vias and the front and back structures. Thus, Hwang fails to teach the front side structure being disposed opposite to the back side structure with respect to the transistor; and a front via formed at a side of the transistor.
Xie ‘433 teaches the front side structure (Xie ‘433: Annotated Fig (14) shared in this OA: 56) being disposed opposite to the back side structure (74) with respect to the transistor (50); and a front via (Front Via) formed at a side of the transistor (50).
Hwang and Xie ‘433 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to one of ordinary skill in the art, to modify Hwang by introducing the front and back structures and the front via in the positions disclosed in Xie ‘433 to achieve the predictable result of making connecting the transistor to power lines easier and more efficient thus leading to a more efficient device and a device construction process that is more reliable.
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Hwang in view of Xie ‘433 does not teach such that the step profile of the side surface of the front via is recessed relative to a top surface of the STI structure and is vertically spaced apart from the BPR.
However, Gambino teaches such that the step profile (Gambino: Annotated Fig (9) shared in this OA: Step Profile) of the side surface of the front via (48+70) is recessed relative to a top surface of the STI structure (22) and is vertically spaced apart from the BPR (BPR, while Gambino does not explicitly describe the horizontal connection connected to 66 as a BPR the entire patent is dedicated to the construction of power delivery through the backside of the substrate (see for example the Abstract of Gambino) allowing for the interpretation of the horizontal connection connected to 66 as a BPR).
Hwang in view of Xie ‘433 and Gambino are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person of ordinary skill in the art, to modify Hwang in view of Xie ‘433 by constructing a step profile between the top and bottom vias as disclosed in Gambino to make establishing contact between the two vias easier leading to a more reliable device production process.
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Regarding claim 3; Hwang in view of Xie ‘433 in further view of Gambino teaches the limitations of the semiconductor device of claim 1.
Hwang in view of Xie ‘433 does not teach wherein an aspect ratio of the lower via hole is greater than an aspect ratio of the upper via hole.
However, Gambino teaches wherein an aspect ratio of the lower via hole (Gambino: Annotated Fig (9) shared in this OA: hole that contains the via 70) is greater than an aspect ratio of the upper via hole (hole that contains the via 48).
Hwang in view of Xie ‘433 and Gambino are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Hwang in view of Xie ‘433 by making the aspect ratio of the lower via hole greater than the aspect ratio of the upper via hole as disclosed in Gambino to make establishing contact between the two vias easier and thus leading to a more reliable and efficient device production process.
Regarding claim 4; Hwang in view of Xie ‘433 in further view of Gambino teaches all the limitations of the semiconductor device of claim 1.
Further, Hwang teaches wherein a bottom width of the upper via hole (Hwang: Annotated Fig (11) shared in this OA: 253) is smaller than a top width of the lower via hole (230).
Regarding claim 7; Hwang in view of Xie ‘433 in further view of Gambino teaches all the limitations of the semiconductor device of claim 1
Further, Hwang teaches wherein the step profile (Hwang Annotated Fig(11) shared in this OA: First Step Profile) is a first step profile, and wherein a second step profile (Second Step Profile)is formed where the lower via hole (hole containing 253) connects to the BPR (220).
Regarding claim 8; Hwang in view of Xie ‘433 in further view of Gambino teaches all the limitations of the semiconductor device of claim 1.
Hwang in view of Xie ‘433 does not teach wherein a connection surface comprising a silicide layer is at an interface between the lower via hole and the upper via hole, wherein a width of the silicide layer is less than or equal to a width of a top surface of the lower via hole, and wherein an interlayer dielectric (ILD) structure is directly on a side surface of the upper via hole, without a silicide layer therebetween.
Gambino teaches wherein a connection surface comprising a silicide layer (Gambino: Annotated Fig (9) shared in this OA: 74) is at an interface between the lower via hole (the hole containing 70)and the upper via hole (48), wherein a width of the silicide layer (74) is less than or equal to a width of a top surface of the lower via hole (70), and wherein an interlayer dielectric (ILD) structure (36+34) is directly on a side surface of the upper via hole (48), without a silicide layer (74) therebetween.
Hwang in view of Xie ‘433 and Gambino are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Hwang in view of Xie ‘433 by using the silicide layer between the two vias as disclosed in Gambino to improve the mechanical and electrical connection between the two vias leading to a more reliable device.
Regarding claim 9; Hwang teaches a semiconductor device comprising:
at least one transistor (Hwang: [0019]), a front side structure (Annotated Fig (11) shared in this OA: 255), and a back side structure (220) comprising a buried power rail (BPR), the front side structure (255) being disposed opposite to the back side structure (220) with respect to the transistor; and
a front via (253 + 230) formed at a side of the transistor and connecting the front side structure (255) to the BPR (220),
wherein the front via (253 + 230) is distinct from the BPR (220), the front via (253 + 230) comprising a lower front via (230) that terminates on the BPR (220) and an upper front via (253) on the lower front via (230),
wherein the lower front via (230) and the upper front via (253) are respectively formed in a lower via hole (VH1) and an upper via hole (VH2) which are vertically and directly connected to each other, and
wherein a width of a bottom surface (width of the bottom surface (along -Z-direction) of 253) of the upper front via (253) is different from a width of a top surface (width of the top surface (along +Z-direction) of 230) of the lower front via (230).
wherein a connection surface comprising a silicide layer is between the lower front via and the upper front via, wherein a width of the silicide layer is less than or equal to a width of the top surface of the lower front via, and wherein an interlayer dielectric (ILD) structure is directly on a side surface of the upper front via, without a silicide layer therebetween.
Hwang teaches a front via connecting a front structure to a back structure in a semiconductor device but fails to disclose the relative location of the transistor compared to the vias and the front and back structures. Thus, Hwang fails to teach the front side structure being disposed opposite to the back side structure with respect to the transistor; and a front via formed at a side of the transistor.
Xie teaches the front side structure (Xie ‘433: Annotated Fig (14) shared in this OA: 56) being disposed opposite to the back side structure (74) with respect to the transistor (50); and a front via (Front Via) formed at a side of the transistor (50).
Hwang and Xie are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to one of ordinary skill in the art, to modify Hwang by introducing the front and back structures and the front via in the positions disclosed in Xie to achieve the predictable result of making connecting the transistor to power lines easier and more efficient thus leading to a more efficient device and a device construction process that is more reliable
Hwang in view of Xie ‘433 does not teach wherein a connection surface comprising a silicide layer is between the lower front via and the upper front via, wherein a width of the silicide layer is less than or equal to a width of the top surface of the lower front via, and wherein an interlayer dielectric (ILD) structure is directly on a side surface of the upper front via, without a silicide layer therebetween.
However, Gambino teaches wherein a connection surface comprising a silicide layer (Gambino: Annotated Fig (9) shared in this OA: 74) is between the lower front via (70) and the upper front via (48), wherein a width of the silicide layer (74) is less than or equal to a width of the top surface of the lower front via (70), and wherein an interlayer dielectric (ILD) structure (36+34) is directly on a side surface of the upper front via (48), without a silicide layer (74) therebetween.
Hwang in view of Xie ‘433 and Gambino are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Hwang in view of Xie ‘433 by using the silicide layer between the two vias as disclosed in Gambino to improve the mechanical and electrical connection between the two vias leading to a more reliable device.
Regarding claim 22; Hwang inn view of Xie ‘433 inn further view of Gambino teaches all the limitations of the semiconductor device of claim 1.
Hwang teaches further comprising an interlayer dielectric (ILD) structure (Hwang: Annotated Fig (11) shared in this OA: 213) at least partially surrounding the front via (230+253) on the top surface of the STI structure (212), wherein the front via is spaced apart from a side surface of a source/drain region of the transistor, with the ILD structure therebetween.
Hwang does not teach wherein the front via is spaced apart from a side surface of a source/drain region of the transistor, with the ILD structure therebetween.
Xie ‘433 teaches wherein the front via (Xie ‘433: Annotated Fig (14) shared in this OA: Front Via) is spaced apart from a side surface of a source/drain region of the transistor (50), with the ILD structure therebetween (54).
Hwang and Xie ‘433 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Hwang by using the interlayer dielectric layer to sperate the via from the transistor to improve the device insulation and thus improve its reliability.
Regarding claim 23; Hwang inn view of Xie ‘433 inn further view of Gambino teaches all the limitations of the semiconductor device of claim 1.
Hwang does not teach wherein the transistor is on a substrate comprising a semiconductor material, and wherein the step profile of the side surface of the front via is recessed relative to a top surface of the substrate.
However, Xie ‘433 teaches wherein the transistor (Xie ‘433: Annotated Fig (14) shared in this OA: 50) is on a substrate (14) comprising a semiconductor material, and wherein the step profile (Step Profile) of the side surface of the front via (Front Via) is recessed relative to a top surface of the substrate (14).
Hwang and Xie ‘433 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person of ordinary skill in the art, to modify Hwang by constructing the front via as disclosed in Xie ‘433 to make facilitate connecting the front of the semiconductor substrate to its back leading to a more reliable and efficient device.
Regarding claim 24; Hwang inn view of Xie ‘433 inn further view of Gambino teaches all the limitations of the semiconductor device of claim 23.
Further, Hwang teaches wherein the STI structure (Hwang: Annotated Fig (14) shared in this OA: 212) is adjacent to the substrate (211).
Regarding claim 25; Hwang in view of Xie ‘433 in further view of Gambino teaches all the limitations of the semiconductor device of claim 9.
Further, Hwang teaches wherein the width of the bottom surface (Hwang: Annotated Fig (11) shared in this OA: width of the bottom surface (along - Z-direction) of 253) of the upper front via is less than the width of the top surface (width of the top surface (along +Z-direction) of 230) of the lower front via (230).
Regarding claim 30; Hwang in view of Xie ‘433 in further view of Gambino teaches all the limitations of the semiconductor device of claim 1.
Hwang in view of Xie ‘433 does not teach wherein the transistor is on a substrate comprising a semiconductor material, and wherein at least a portion of the STI structure is between the substrate and the step profile of the side surface of the front via.
Gambino teaches wherein the transistor (Gambino: Annotated Fig (9) shared in this OA: 14) is on a substrate (62) comprising a semiconductor material, and wherein at least a portion of the STI structure (22) is between the substrate (62) and the step profile (Step Profile) of the side surface of the front via (48+70).
Hwang in view of Xie ‘433 and Gambino are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art to modify Hwang in view of Xie ‘433 by constructing the STI structure as disclosed in Gambino to improve the insulation of the vias thus leading to a more reliable device.
Regarding claim 31; Hwang in view of Xie ‘433 in further view of Gambino teaches all the limitations of the semiconductor device of claim 1.
Further, Hwang teaches wherein a bottom surface of the front via (Hwang: Annotated Fig (11) shared in this OA: 253+230) is substantially coplanar with a bottom surface of the STI structure (212).
Regarding claim 27; Hwang teaches a semiconductor device comprising:
at least one transistor (Hwang: [0019]), a front side structure (Annotated Fig (11) shared in this OA: 255), and a back side structure (220) comprising a buried power rail (BPR), the front side structure (255) being disposed opposite to the back side structure (220) with respect to the transistor; and
a front via (253 + 230) formed at a side of the transistor and connecting the front side structure (255) to the BPR (220),
wherein the front via (253 + 230) is distinct from the BPR (220), the front via (253 + 230) comprising a lower front via (230) on the BPR (220) and an upper front via (253) on the lower front via (230),
wherein a connection surface comprising a silicide layer is between the lower front via and the upper front via, wherein a width of the silicide layer is less than or equal to a width of the top surface of the lower front via, and wherein an interlayer dielectric (ILD) structure is directly on a side surface of the upper front via, without a silicide layer therebetween.
Hwang teaches a front via connecting a front structure to a back structure in a semiconductor device but fails to disclose the relative location of the transistor compared to the vias and the front and back structures. Thus, Hwang fails to teach the front side structure being disposed opposite to the back side structure with respect to the transistor; and a front via formed at a side of the transistor.
Xie teaches the front side structure (Xie ‘433: Annotated Fig (14) shared in this OA: 56) being disposed opposite to the back side structure (74) with respect to the transistor (50); and a front via (Front Via) formed at a side of the transistor (50).
Hwang and Xie are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to one of ordinary skill in the art, to modify Hwang by introducing the front and back structures and the front via in the positions disclosed in Xie to achieve the predictable result of making connecting the transistor to power lines easier and more efficient thus leading to a more efficient device and a device construction process that is more reliable
Hwang in view of Xie ‘433 does not teach wherein a connection surface comprising a silicide layer is between the lower front via and the upper front via, wherein a width of the silicide layer is less than or equal to a width of the top surface of the lower front via, and wherein an interlayer dielectric (ILD) structure is directly on a side surface of the upper front via, without a silicide layer therebetween.
However, Gambino teaches wherein a connection surface comprising a silicide layer (Gambino: Annotated Fig (9) shared in this OA: 74) is between the lower front via (70) and the upper front via (48), wherein a width of the silicide layer (74) is less than or equal to a width of the top surface of the lower front via (70), and wherein an interlayer dielectric (ILD) structure (36+34) is directly on a side surface of the upper front via (48), without a silicide layer (74) therebetween.
Hwang in view of Xie ‘433 and Gambino are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Hwang in view of Xie ‘433 by using the silicide layer between the two vias as disclosed in Gambino to improve the mechanical and electrical connection between the two vias leading to a more reliable device.
Regarding claim 28; Hwang in view of Xie ‘433 in further view of Gambino teaches all the limitations of the semiconductor device of claim 27.
Further, Hwang teaches wherein the lower front via (Hwang: Annotated Fig (11) shared in this OA: 230) and the upper front via (253) are respectively formed in a lower via hole (via hole that contains 230) and an upper via hole (via hole that contains 253) which are vertically and directly connected to each other, and wherein a side surface of the front via (230+253) has a step profile (First Step Profile) where the lower via hole (via hole that contains 230) is connected to the upper via hole (via hole that contains 253).
Regarding claim 29; Hwang in view of Xie ‘433 in further view of Gambino teaches all the limitations of the semiconductor device of claim 27.
Further, Hwang teaches wherein a width of a bottom surface of the upper front via (Hwang: Annotated Fig (11) shared in this OA: 253) is different from the width of the top surface of the lower front via (230), and wherein the width of the silicide layer is less than the width of the top surface of the lower front via.
Hwang does not teach wherein the width of the silicide layer is less than the width of the top surface of the lower front via
Xie ‘433 teaches and wherein the width of the silicide layer (Gambino: Annotated Fig (9) shared in this OA: 74) is less than the width of the top surface of the lower front via (70).
Xie ‘433 teaches wherein the width of the silicide layer (Xie ‘433: [0060]: “…contacts 56, 58 can include a silicide liner”) is less than or equal to a width of a top surface of the lower front via (Annotated Fig (9) shared in this OA: 48, given that [0060] of Xie ‘433 states that the material of 56, 58 contains a silicide, it can be seen from annotated Fig (9) of Xie ‘433 that the silicide will be confined to the surface of bottom part of the via (58) which is a part of the material (56) and which has a smaller surface than the top surface of the bottom via (48)).
Hwang and Xie ‘433 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art to modify Hwang by using the silicide layer disclosed in Xie ‘433 to improve the electrical connectivity between the vias leading to a more efficient device.
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Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al, US 20220069100 A1 (Hwang) in view of Xie et al, US 20230178433 A1 (Xie ‘433) in further view of Gambino et al, US 9455187 B1 (Gambino) in further view of Hsu et al, US 20230215801 A1 (Hsu).
Regarding claim 2; Hwang in view of Xie ‘433 in further view of Gambino teaches all the limitations of the semiconductor device of claim 1.
However, Hwang in view of Xie ‘433 in further view of Gambino does not teach wherein a height of the lower via hole and a height of the upper via hole are substantially equal to each other.
Hsu teaches wherein a height of the lower via hole (Hsu: Fig (2): the lower via hole in which the via (P11) is formed) and a height of the upper via hole (the upper via hole in which the via (P12) is formed) are substantially equal to each other.
Hwang in view of Xie ‘433 in further view of Gambino and Hsu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, modify Hwang in view of Xie ‘433 in further view of Gambino by making the height of the upper and lower via holes the same as disclosed in Hsu to make the device manufacturing simpler leading to a more efficient production process.
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Claims 6 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al, US 20220069100 A1 (Hwang) in view of Xie et al, US 20230178433 A1 (Xie ‘433) in further view of Gambino et al, US 9455187 B1 (Gambino) in further view of Xie et al, US 20230132353 A1 (Xie ‘353).
Regarding claim 6; Hwang in view of Xie ‘433 in further view of Gambino teaches all the limitations of the semiconductor device of claim 1
However, Hwang in view of Xie ‘433 in further view of Gambino does not teach wherein the front side structure is a source/drain region contact plug formed on a source/drain region of the transistor, and wherein the back side structure is a back side power distribution network (BSPDN) structure comprising the BPR.
Further, Xie ‘353 teaches wherein the front side structure (Xie ‘353: Fig (16): 143) is a source/drain region contact plug formed on a source/drain region of the transistor (123), and wherein the back side structure (105) is a back side power distribution network (BSPDN) structure.
Hwang in view of Xie ‘433 in further view of Gambino and Xie ‘353 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Hwang in view of Xie ‘433 in further view of Gambino by using the via structures to connect the front side structure of a transistor to the backside structure to make establishing electrical connections within the device easier leading to a more efficient device construction process.
Regarding claim 21; Hwang in view of Xie ‘433 in further view of Gambino teaches all the limitations of the semiconductor device of claim 1.
However, Hwang in view of Xie ‘433 in further view of Gambino does not teach wherein the front side structure comprises a source/drain region contact plug that is on a source/drain region of the transistor, and wherein a top surface of the source/drain region contact plug is coplanar with a top surface of the front via.
Xie ‘353 teaches wherein the front side structure (Xie ‘353: Fig (16): 143) comprises a source/drain region contact plug (143) that is on a source/drain region (recessed S/D contacts in (143), [0037]) of the transistor (123), and wherein a top surface of the source/drain region contact plug (143) is coplanar with a top surface of the front via (139+107+109).
Hwang in view of Xie ‘433 in further view of Gambino and Xie ‘353 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Hwang in view of Xie ‘433 in further view of Gambino by constructing the connections between the S/D front structures and the power delivery network as disclosed in Xie ‘353 to make establishing electrical connections within the device easier leading to a more reliable device construction process.
Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al, US 20220069100 A1 (Hwang) in view of Xie et al, US 20230178433 A1 (Xie ‘433) in further view of Gambino et al, US 9455187 B1 (Gambino) in further view of Borthakur et al, US 20150243699 A1 (Borthakur).
Regarding claim 32; Hwang in view of Xie ‘433 in further view of Gambino teaches all the limitations of the semiconductor device of claim 9
Hwang in view of Xie ‘433 in further view of Gambino does not teach wherein a first portion of the upper front via extends into a shallow trench isolation (STI) structure adjacent to the transistor, and a second portion of the upper front via is on a top surface of the STI structure, and wherein a vertical thickness of the first portion of the upper front via is less than a vertical thickness of the second portion of the upper front via.
Borthakur teaches wherein a first portion of the upper front via (Borthakur: Annotated Fig (2) shared in this OA: 42) extends into a shallow trench isolation (STI) structure (28) adjacent to the transistor ([0022]), and a second portion of the upper front via is on a top surface of the STI structure, and wherein a vertical thickness of the first portion (Thickness of First Portion of the Front Via) of the upper front via (42) is less than a vertical thickness of the second portion (Thickness of second Portion of the Front Via) of the upper front via (42).
Hwang in view of Xie ‘433 in further view of Gambino and Borthakur are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Hwang in view of Xie ‘433 in further view of Gambino by constructing the front via to pass through the shallow trench isolation region to further improve the isolation of the vias and reduce the possibility of a short circuit leading to a more reliable device.
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Conclusion
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/M.K./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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