DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims presented have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1,2,24,28 and 29 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Huang et al. (US20200176432A1).
Regarding claim 1, annotated Fig. 19 of Huang teaches a method, comprising:
manufacturing an interconnection structure (see annotated Fig.19) of an integrated circuit, the interconnection structure including an insulating layer 130 (para.0023) on a nitride layer 108 (para.0013, wherein dielectric layer 108 is formed of a nitride such as silicon nitride), conductive interconnection elements 106/112 (para.0017, see annotated Fig.19), and a conductive pad 106/112 (see annotated Fig.19) having a first surface opposite a second surface, the conductive interconnection elements 106/112 and the conductive pad extending through the insulating layer 130 and the nitride layer 108, each of the conductive interconnection elements 106/112 having a first surface (see annotated Fig.19) opposite a second surface (see annotated Fig.19), the first surfaces of the conductive interconnection elements coplanar with a first surface of the insulating layer 130, the second surfaces of the conductive interconnection elements coplanar with a first surface (see annotated Fig.19) of the nitride layer 108; and
forming a protection layer 160 (para.0024) on the interconnection structure, the protection layer 160 including a first nitride layer 132/140 (para.0025,128, wherein dielectric layers 132 and 140 are formed of a nitride such as silicon nitride), a second insulating layer 148 (para.0031), and a second nitride layer 156 (para.0034, wherein dielectric layer 156 is formed of a nitride such as silicon nitride), the second insulating layer 148 being between the first 132/140 and second nitride layers 156, the first nitride layer 132/140 being on the first surfaces of the conductive interconnection elements (see annotated Fig.19) and the first surface of the insulating layer 148, the second nitride layer 156 including an alternation of ridges and troughs elements (see annotated Fig.19).
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Regarding claim 2, Huang further teaches the method according to claim 1, wherein the forming of the protection layer 160 (para.0024) includes:
forming, by photolithography, a resin pattern on the first surface of the protection layer 160, the resin pattern being a succession of protrusions separated by openings (see annotated Fig.19); and forming the ridges separated by the troughs (see annotated Fig.19) in the protection layer 160 (para.0046) by etching from the first surface of the protection layer 160, the etching including etching at least a portion of the protection layer 160 using the resin pattern as an etch mask (para.0034, wherein the dielectric layer 156 is formed of a polymer, which may be a photo-sensitive material such as PBO, polyimide, BCB, or the like, that may be patterned using a lithography mask).
Regarding claim 24, annotated Fig. 19 of Huang teaches a method, comprising:
forming an interconnection structure (see annotated Fig.19) of an integrated circuit, the interconnection structure including an insulating layer 130 (para.0023) on a nitride layer 108 (para.0013, wherein dielectric layer 108 is formed of a nitride such as silicon nitride), at least one conductive pad 106/112 (see annotated Fig.19), and conductive vias 106/112 (para.0017, see annotated Fig.19), the at least one conductive pad and the conductive vias extending through the insulating layer 130 and the nitride layer 108, each of the conductive vias and the at least one conductive pad (see annotated Fig.19) having a first surface (see annotated Fig.19) that is opposite a second surface (see annotated Fig.19), the first surfaces of the conductive vias and the at least one conductive pad coplanar with a first surface of the insulating layer 130, the second surfaces of the conductive vias and the at least one conductive pad coplanar with a first surface of the nitride layer 108;
forming a protection layer 160 (para.0024) on the interconnection structure, the protection layer 160 having an upper nitride layer 156 (para.0034, wherein dielectric layer 156 is formed of a nitride such as silicon nitride), the protection layer 160 being on the first surfaces of the conductive vias and the at least one conductive pad, and the insulating layer (see annotated Fig.19); and
forming a roughness (see annotated Fig.19) in a surface of the upper nitride layer 156 of the protection layer 160 to have an alternation of ridges and troughs (see annotated Fig.19) in the protection layer 160, the upper nitride layer 156 delimiting the troughs (see annotated Fig.19).
Regarding claim 28, Huang further teaches the method of claim 24, wherein the forming of the protection layer 160 (para.0024) includes: forming a lower nitride layer 132/140 (para.0025,128, wherein dielectric layers 132 and 140 are formed of a nitride such as silicon nitride); forming an oxide layer 148 (para.0031, wherein dielectric layer 148 is formed of an oxide such as silicon oxide) on the lower nitride layer 132/140; and forming the upper nitride layer 156 (para.0034, wherein dielectric layer 156 is formed of a nitride such as silicon nitride) on the oxide layer 148, the roughness being formed in the upper nitride layer 156.
Regarding claim 29, Huang further teaches the method of claim 24, wherein the forming of the interconnection structure (see annotated Fig.19) includes: forming a first nitride layer 108 (para.0013, wherein dielectric layer 108 is formed of a nitride such as silicon nitride); and forming the insulating layer 130 (para.0023) on the first nitride layer 108.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US20200176432A1) in view of Lin et al. (US20070069347A1).
Regarding claim 3, Huang does not teach wherein widths of the troughs is in a range from 50 nanometers to 5 micrometers and heights of the troughs is in a range from 50 nanometers to 500 nanometers.
Figs.2a-2m of Lin teaches a semiconductor chip that comprises a passivation layer over a first metallization structure and a second metallization structure; wherein the passivation layer includes multiple openings with the greatest transverse dimension of the openings 17 in the passivation layer 18 ranges, for example, from 0.1 microns to 50 microns and, preferably, from 0.5 microns to 20 microns. The greatest transverse dimension of the openings 27 in the polymer layer 20 ranges, for example, from 1 micron to 100 microns, and preferably from 2 microns to 30 microns. By approximating the dimension of the depth in relation to the width, it ranges from 50 nanometers to 500 nanometers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Lin’s dimensions in the depths and widths of Huang’s troughs in order to enhance the routing capability of the topmost thin-film metal layer under the passivation layer (Lin, [para.0083]).
Claims 4,5 and 25-27 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US20200176432A1) in view of Sakai et al. (US20230220587A1).
Regarding claim 4, Huang does not teach wherein the forming of the protection layer includes:
chemical-mechanical polishing the first surface of the protection layer, the polishing including forming a roughness greater than or equal to 5 nanometers, on the first surface of the protection layer, the roughness being defined by a root mean square height of ridges of a surface with respect to an average level defined for the surface.
Sakai teaches, in abstract, a Group-III element nitride semiconductor substrate including a first surface and a second surface; wherein the Group-III element nitride semiconductor substrate has main surface that has a root mean square height Wq of the surface waviness profile of 25 nm or less (para.0048); and wherein chemical mechanical polish (CMP) apparatus is used to process the main surface (para.0060).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to process the first surface of Huang’s protection layer using chemical mechanical polish (CMP) apparatus using a slurry, as taught by Sakai, in order to increase the adhesive or bonding force on the surface.
Regarding claim 5, Sakai further teaches the method according to claim 4, wherein the polishing includes implementing a slurry polishing solution including abrasive balls (para.0060, wherein chemical mechanical polish (CMP) apparatus includes using a slurry such as colloidal silica and a polishing pad made of a nonwoven fabric).
Regarding claim 25, Huang does not teach wherein the forming of the roughness in the surface of the protection layer includes performing a chemical-mechanical polishing on the protection upper nitride layer.
Sakai teaches, in abstract, a Group-III element nitride semiconductor substrate including a first surface and a second surface; wherein the Group-III element nitride semiconductor substrate has main surface and wherein chemical mechanical polish (CMP) apparatus is used to process the main surface (para.0060).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to process the first surface of Huang’s protection layer using chemical mechanical polish (CMP) apparatus using a slurry, as taught by Sakai, in order to increase the adhesive or bonding force on the surface.
Regarding claim 26, Huang does not teach wherein the roughness is greater than or equal to 5 nanometers, and the roughness is defined by a root mean square height of ridges of the surface with respect to an average level defined for the surface.
Sakai teaches, in abstract, a Group-III element nitride semiconductor substrate including a first surface and a second surface; wherein the Group-III element nitride semiconductor substrate has main surface that has a root mean square height Wq of the surface waviness profile of 25 nm or less (para.0048).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to process the first surface of Huang’s protection layer using chemical mechanical polish (CMP) apparatus using a slurry, as taught by Sakai, in order to increase the adhesive or bonding force on the surface.
Regarding claim 27, Sakai further teaches the method according to claim 25, wherein the chemical- mechanical polishing includes implementing a slurry polishing solution including abrasive balls (para.0060, wherein chemical mechanical polish (CMP) apparatus includes using a slurry such as colloidal silica and a polishing pad made of a nonwoven fabric).
Claims 11,20,21 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US20200176432A1) in view of Kim et al. (US20180130761A1).
Regarding claim 11, Huang does not teach forming encapsulation resin in contact with the first surface of the protection layer.
Fig.8 of Kim teaches a semiconductor package that includes insulating protective layer 30 is formed on the corresponding build-up layer 20 and an encapsulating part 5 being in contact with the insulating protective layer 30 (para.00116).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Kim’s an encapsulating part in the teachings of Huang in order to provide more protection.
Regarding claim 20, annotated Fig. 19 of Huang teaches a method, comprising:
forming an interconnection structure (see annotated Fig.19) on a substrate 100 (para.0012), the forming of the interconnection structure including:
forming a first nitride layer 108 (para.0013, wherein dielectric layer 108 is formed of a nitride such as silicon nitride);
forming an insulating layer 130 (para.0023) on the first nitride layer;
forming interconnection elements 106/112 (para.0017, see annotated Fig.19) extending along a first direction through the first nitride layer 108 and the insulating layer 130, each interconnection element 106/112 (para.0017, see annotated Fig.19) having a first surface (see annotated Fig.19) opposite a second surface (see annotated Fig.19), the first surfaces coplanar with a first surface of the insulating layer 130, the second surfaces coplanar (see annotated Fig.19) with a first surface of the first nitride layer 108; and
forming a conductive pad 106/112 (see annotated Fig.19) extending along the first direction through the first nitride layer 108 and the insulating layer 130, the conductive pad having a first surface opposite a second surface (see annotated Fig.19), the first surface of the conductive pad coplanar with the first surfaces of the interconnection elements (see annotated Fig.19), the second surface of the conductive pad coplanar with the second surfaces of the interconnection elements (see annotated Fig.19);
forming a protection layer 160 (para.0024) on the interconnection structure, the forming of the protection layer 160 including:
forming a second nitride layer 132/140 (para.0025,128, wherein dielectric layers 132 and 140 are formed of a nitride such as silicon nitride) on the interconnection structure, the second nitride layer 132/140 in contact with the first surfaces of the insulating layer 130, the conductive pad, and the interconnection elements (see annotated Fig.19);
forming an oxide layer 148 (para.0031, wherein dielectric layer 148 is formed of an oxide such as silicon oxide) on the second nitride layer 132/140; and
forming a third nitride layer 156 (para.0034, wherein dielectric layer 156 is formed of a nitride such as silicon nitride) on the oxide layer 148, the third nitride layer 156 having a first thickness along the first direction, the third nitride layer 156 having a first surface opposite a second surface, the first surface contacts the oxide layer 148;
forming troughs (see annotated Fig.19) in the second surface of the third nitride layer 156, the troughs extending along the first direction for a second thickness that is less than the first thickness of the third nitride layer 156.
Huang does not teach forming encapsulation material on the protection layer and in the troughs in the third nitride layer.
Fig.8 of Kim teaches a semiconductor package that includes insulating protective layer 30 is formed on the corresponding build-up layer 20 and an encapsulating part 5 being in contact with the insulating protective layer 30 (para.00116).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Kim’s an encapsulating part in the teachings of Huang in order to provide more protection.
Regarding claim 21, Huang further teaches the method of claim 20, wherein the forming of the troughs (see annotated Fig.19) includes forming trenches in the third nitride layer 156 (para.0034, wherein dielectric layer 156 is formed of a nitride such as silicon nitride).
Regarding claim 30, Huang does not teach forming encapsulation material on the protection layer and in the troughs in the protection layer.
Fig.8 of Kim teaches a semiconductor package that includes insulating protective layer 30 is formed on the corresponding build-up layer 20 and an encapsulating part 5 being in contact with the insulating protective layer 30 (para.00116).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Kim’s an encapsulating part in the teachings of Huang in order to provide more protection.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US20200176432A1) in view of Kim et al. (US20180130761A1) and in further view of Sakai et al. (US20230220587A1).
Regarding claim 22, Huang does not teach wherein the forming of the troughs includes forming, by chemical-mechanical polishing, a roughness greater than or equal to 5 nanometers in the third nitride layer, and
the roughness is defined by a root mean square height of ridges of a surface with respect to an average level defined for the surface.
Sakai teaches, in abstract, a Group-III element nitride semiconductor substrate including a first surface and a second surface; wherein the Group-III element nitride semiconductor substrate has main surface that has a root mean square height Wq of the surface waviness profile of 25 nm or less (para.0048); and wherein chemical mechanical polish (CMP) apparatus is used to process the main surface (para.0060).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to process the first surface of Huang’s protection layer using chemical mechanical polish (CMP) apparatus using a slurry, as taught by Sakai, in order to increase the adhesive or bonding force on the surface.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT KIPKEMOI RONO whose telephone number is (571)270-5977. The examiner can normally be reached Mon-Fri, 8am-5pm.
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
Prosecution Insights