DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a FINAL OFFICE ACTION in response to the Amendment/ Remarks filed 10/03/2025. Claims 1-18 are pending in the Application, of which Claims 1, 7 and 13 are independent.
Continuity/ Priority Data
The present Application 17885439 filed 08/10/2022 is a Continuation of 16548397, filed 08/22/2019, now U.S. Patent No. 11,416,333.
Response to Arguments
Applicant's arguments, see Amendment/ Remarks filed 10/03/2025, with respect to the rejection of Claims 1-18 under 35 U.S.C. 102(a)(1) as being anticipated by Sturm et al. (U.S. Pub. No. 20080201626), have been fully considered but they are not persuasive, as set forth in the present office action.
Applicant argues that Sturm fails to disclose or suggest each feature of independent claims 1, 7 and 13, as amended, including, inter alia, “blocking an access command that is directed to one or more components of the apparatus that are coupled with the ECC circuit from reaching the one or more components after determining that the ECC function is disabled.”
Applicant has amended the independent claims to recite "blocking an access command ... from reaching the one or more components," to more clearly distinguish Strum, in which the Office Action contends an action directed by a command is "blocked" from being implemented, rather than a command itself being blocked from reaching a destination.
In response to Applicant arguments, the Examiner notes that a command is "blocked" from being implemented as disclosed by Sturm conveys the same function as a command being blocked from reaching a destination as Claimed. Both conditions stop or prevent the process from occurring, from not being implemented or from not reaching a destination.
According to the Dictionary Definition “blocking” has various meanings, such as,
a: to stop or hinder (someone or something) from moving through or going by.
b: to prevent (something, such as a process or action) from occurring.
In this case, the term “blocking” as defined in the Dictionary convey the same meaning to one of ordinary skill in the art the, of disabling something by preventing or stopping a process or action from occurring, such as executing an ECCOFF command to disable components, since “blocking” and “disabling” have the same meaning.
Sturm discloses in para. [0032] FIG. 2. When the ECCOFF signal is in an active state, however, the ECCOFF signal essentially disables the activation of the wordlines, the sense amplifiers and the bitlines in the parity memory portions within memory banks 0-3 that are dedicated to ECC parity bits. As such, this eliminates the power consumption necessary to activate these lines and amplifiers. Consequently, not only is the ECC mode disabled, but the actual portions of the memory array dedicated to the ECC mode are disabled so that power is not being unnecessarily expended on these portions of memory.
The Examiner notes that the ECCOFF signal, corresponding to the command, which disables the activation of the wordlines, as disclosed by Sturm, performs the equivalent function as the Claimed limitation.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sturm et al. (U.S. Pub. No. 20080201626) Pub. Date: August 21, 2008.
Regarding independent Claims 1, 7 and 13, Sturm discloses POWER SAVINGS FOR MEMORY WITH ERROR CORRECTION MODE, comprising:
a memory array including a first portion configured to store user data and a second portion configured to store error checking and correcting (ECC) data,
[0022] FIG. 1 illustrates memory device 1 in accordance with one embodiment of the present invention. In one embodiment, memory device 1 includes ECC circuit 2, ECC control 3, memory control 4, and memory sub-block 5. Memory sub-block 5 includes data memory 8 and parity memory 9.
an ECC circuit coupled with the second portion and performs an ECC function for the user data; [0023] FIG. 1. As such, one embodiment of memory device 1 provides an ECC mode that allows such failures to be detected and/or corrected. In one case, the memory system is configured with error correction code (ECC) circuit 2. As such, ECC circuit 2 is provided to compensate for cell failures in data memory 8. ECC circuit 2, in cooperation with ECC control 3 and memory control 4, generates parity codes that are used to detect and correct errors or failures in memory cells. The error correction codes or parity codes are stored in parity memory 9.
a register configured to indicate whether the ECC function is enabled or disabled, and circuitry configured to determine the ECC function is disabled based on accessing the register; [0024] Because the ECC mode is not always used in memory device 1 for all applications of the device, however, one embodiment of the memory device 1 is configured such that ECC control circuit 3 alternately enables and disables the ECC mode. More specifically, ECC control 3 is configured to provide a parity control signal to first decoder 7, which in turn supplies access control signals to parity memory 9. In this way, the parity control signal from ECC control 3 enables and disables the parity memory 9 within memory sub-block 5. In one case, this control includes controlling wordline signals and sense amplifier signals in the parity memory 9.
[0025] With ECC control circuit 3 and the parity control signal in accordance with one embodiment of the present invention, however, memory device 1 can disable first decoder 7 thereby disabling activation of parity memory 9 and hence saving power. Such disabling saves the operating current that would normally be expended by the parity memory 9, as will be explained in further detail below.
[0026] FIG. 1. For example, ECC control 3 can be configured to receive signals indicative of whether the ECC mode is to be used in memory device 1. One such signal can be a Mode Register set signal “a register configured to indicate” from a pad that enables and disables the ECC mode as controlled via signals provided to the pad. In another instance, a Fuse set signal is provided via a fuse that can be blown or not blown in order to essentially "hard-code" the enabling or disabling of the ECC mode.
blocking an access command that is directed to one or more components of the apparatus that are coupled with the ECC circuit from reaching the one or more components after determining that the ECC function is disabled; [0032] FIG. 2 When the ECCOFF signal is in an active state, however, the ECCOFF signal essentially disables the activation of the wordlines, the sense amplifiers and the bitlines in the parity memory portions within memory banks 0-3 that are dedicated to ECC parity bits. As such, this eliminates the power consumption necessary to activate these lines and amplifiers. Consequently, not only is the ECC mode disabled, but the actual portions of the memory array dedicated to the ECC mode are disabled so that power is not being unnecessarily expended on these portions of memory.
after blocking the access command that was directed to the one or more components, replacing a defective segment of the first portion of the memory array with a replacement segment of the second portion of the memory array. [0023] In fabrication and/or operation of such memory devices, it is possible for cell failures “defective segment” to be introduced in the memory sub-block 5. As such, one embodiment of memory device 1 provides an ECC mode that allows such failures “defective segment” to be detected and/or corrected. In one case, the memory system is configured with error correction code (ECC) circuit 2. As such, ECC circuit 2 is provided to compensate for cell failures in data memory 8 “replacement segment”. ECC circuit 2, in cooperation with ECC control 3 and memory control 4, generates parity codes that are used to detect and correct errors or failures in memory cells.
Regarding independent Claim 13, additionally recites a host device; [0022] FIG. 1 illustrates memory device 1 that includes among other devices, a memory control 4 corresponding to host device.
Regarding Claims 2, 8, 14, Sturm discloses circuitry configured to replace the defective segment with the replacement segment by updating address mapping information stored in a nonvolatile memory array of the apparatus. [0029] Furthermore, in one embodiment, memory device 10 is configured with error correction code (ECC) mode, and thus, includes ECC circuit 27 and ECC control circuit 28 built onto the device. In fabrication and/or operation of memory device 10, it is possible for cell failures to be introduced in the memory. As such, the ECC circuit 27 and ECC control circuit 28 provide an ECC mode, which compensates for cell failures in the memory arrays within the memory banks 0-3 of memory device 10.
Regarding Claims 3, 9, 15, Sturm discloses wherein the nonvolatile memory array is one of a fuse array or a flash memory array; [0035] FIGS. 3 and 4 illustrate memory sub-block 30 of a memory device such as memory device 1 in FIG. 1 or memory device 10 in FIG. 2. For example, memory sub-block 30 may be a portion of any one of memory sub-blocks 12-26 of memory banks 0-3 in FIG. 2. In each case, memory sub-block 30 includes a regular memory array 34 and a parity memory array 32. In FIG. 3, a regular memory array 34 is oriented in a first single discrete location and a parity memory array 32 in second single discrete location adjacent the first location. In FIG. 4, both the regular memory array 34 and parity memory array 32 are divided into multiple locations and dispersed across memory sub-block 30.
Regarding Claims 4, 5, 10, 11, 16, 17, Sturm discloses wherein the defective segment and the replacement segment each comprise a single column of the memory array, and wherein the defective segment and the replacement segment each comprise a plurality of adjacent columns of the memory array, [0024] More specifically, ECC control 3 is configured to provide a parity control signal to first decoder 7, which in turn supplies access control signals to parity memory 9. In this way, the parity control signal from ECC control 3 enables and disables the parity memory 9 within memory sub-block 5. In one case, this control includes controlling wordline signals and sense amplifier signals in the parity memory 9.
Regarding Claims 6, 12, 18, Sturm discloses access circuitry configured, in response to an access command identifying the defective segment, to access memory cells of the replacement segment. [0036] In the examples of FIGS. 3 and 4, memory sub-block 30 is further divided into segments, such that a plurality of segmented wordline driver stripes 36 are provided. These stripes 36 are illustrated in FIGS. 3 and 4 as horizontally (relative to the orientation in the illustration of FIGS. 3 and 4) extending lines. Each of these wordline driver stripes 36 are further coupled to local word lines (LWL) 44. For ease of illustration, only the LWL 44 on one of the segmented wordline driver stripes 36 is actually labeled, but each of the illustrated segmented wordline driver stripes 36 is also coupled to a plurality of LWL 44, represented by short vertical (relative to the orientation in the illustration of FIGS. 3 and 4) extending lines.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: October 15, 2025
Final Rejection 20251015
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV