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Office Actions › Intel Corporation › 17886278
Last updated: October 27, 2026
Application No. 17/886,278

ALTERNATING HIGH K LAYERS ON GLASS PILLARS FOR SUPER CAPACITORS ON GLASS SUBSTRATES

Non-Final OA
Filed
Aug 11, 2022
Examiner
CHI, SUBERR L
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
3 (Non-Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
87%
With Interview

Interview Optional

— +2.7% interview lift. Interview lift (+2.7%) is below the 15.0% threshold. A written response is recommended.
Based on 663 resolved cases, 2023–2026

Examiner Intelligence

CHI, SUBERR L View full profile →
Grants 85% — above average
85%
Career Allowance Rate
561 granted / 663 resolved
+16.6% vs TC avg
Minimal +3% lift
Without
With
+2.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
20 currently pending
Career history
693
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
44.5%
+4.5% vs TC avg
§102
24.0%
-16.0% vs TC avg
§112
28.4%
-11.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 663 resolved cases

Prosecution Timeline

Show 1 earlier event
Jun 06, 2023
Response after Non-Final Action
Feb 03, 2026
Non-Final Rejection mailed
Apr 29, 2026
Response Filed
Jul 09, 2026
Final Rejection mailed
Sep 09, 2026
Response after Non-Final Action
Oct 09, 2026
Request for Continued Examination
Oct 13, 2026
Response after Non-Final Action
Oct 20, 2026
Non-Final Rejection mailed (current)

Precedent Cases

Applications granted by this same examiner with similar technology

18/240,711
Patent 12772563
SEMICONDUCTOR DEVICE INCLUDING FIRST AND SECOND MIDDLE-VOLTAGE ELEMENTS, DISPLAY DRIVING DEVICE INCLUDING THE SAME, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE
3y 1m to grant Granted Oct 20, 2026
18/441,118
Patent 12764993
High Voltage Transistor Structure
2y 8m to grant Granted Oct 13, 2026
17/784,271
Patent 12757537
DISPLAY DEVICE RELATED TO MICRO-LED AND MANUFACTURING METHOD THEREFOR
4y 3m to grant Granted Oct 06, 2026
17/819,039
Patent 12757396
METHOD FOR MANUFACTURING OXIDE FILM, METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR MEMORY DEVICE
4y 1m to grant Granted Oct 06, 2026
18/154,313
Patent 12751110
SUBSTRATE WITH LOW-REFLECTION SURFACE FILM AND STRUCTURE, AND SEMICONDUCTOR DEVICE
3y 8m to grant Granted Sep 29, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

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Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
87%
With Interview (+2.7%)
2y 9m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 663 resolved cases by this examiner. Grant probability derived from career allowance rate.

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Data sourced from USPTO Patent File Wrapper (daily) and Office Action Archive (weekly). Analysis generated by IP Author.

Data: USPTO Patent File Wrapper (daily) • Office Action Archive (weekly) • 89M+ prosecution events

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