Prosecution Insights
Last updated: August 17, 2026
Application No. 17/886,353

ON WAFER DIMENSIONALITY REDUCTION

Final Rejection §103
Filed
Aug 11, 2022
Priority
Aug 18, 2021 — provisional 63/234,654
Examiner
HICKS, AUSTIN JAMES
Art Unit
2142
Tech Center
2100 — Computer Architecture & Software
Assignee
Applied Materials Inc.
OA Round
4 (Final)
75%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 75% — above average
75%
Career Allowance Rate
313 granted / 418 resolved
+19.9% vs TC avg
Strong +26% interview lift
Without
With
+25.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
55 currently pending
Career history
467
Total Applications
across all art units

Statute-Specific Performance

§101
13.1%
-26.9% vs TC avg
§103
54.0%
+14.0% vs TC avg
§102
16.4%
-23.6% vs TC avg
§112
14.1%
-25.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 418 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments filed 5/26/2026 have been fully considered but they are not persuasive. Applicant argues, “as agreed in the Examiner interview, a ‘second model’ that takes as input ‘manufacturing parameters, comprising input settings to a substrate manufacturing device’ and produces as output ‘dimensionally reduced metrology data’ is not taught or suggested by Middlebrooks.” Remarks 8. No agreement was reached in the interview. Arabashi teaches a second model as a retrained first model in paragraph 56 “each time the wafer recipe is executed, the resulting data set from the sensor outputs can be labeled and used to continuously train and retrain the model.“ Arabshahi goes on to teach that the wafer recipe includes input setting to a manufacturing device in paragraph 3, “a wafer recipe that includes control inputs and timing constraints for a semiconductor processing system to process a semiconductor wafer.” The timing and control inputs are both input settings to a substrate manufacturing device to determine substrate processing conditions. The dimensionally reduction is taught by Middlebrooks in paragraph 116, “variational encoder-decoder architecture. In the middle (e.g., middle layers) of the model (e.g., a neural network), the present model formulates a low dimensional encoding (e.g., latent space) that encapsulates information in an input (e.g., a complex electric field image and/or other input associated with a pattern or other features of a semiconductor manufacturing process) to the model.” Middlebrooks and the Arabshahi are obvious to combine for the reasons stated below. Therefore, the claim is made obvious by the prior art. Applicant argues, “Talukder is silent regarding a second machine learning model configured ‘to predict reduced dimensionality metrology data as output based on input comprising the first manufacturing parameters,’ as recited in amended claim 1.” In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3 and 5-20 are rejected under 35 U.S.C. 103 as being unpatentable over US20210116896A1 to Arabshahi et al, WO2021104718A1 to Middlebrooks et al and WO2022140097A1 to Talukder et al. Arabshahi teaches claims 1, 9 and 16. (Currently amended) A method comprising: receiving first metrology data (Arabshahi abs “executing a wafer recipe a semiconductor processing system to process a semiconductor wafer; monitoring sensor outputs from a sensors that monitor conditions associated with the semiconductor processing system…”) training a first machine learning model with data input comprising the first metrology data to generate a first trained machine learning model, (Arabshahi fig. 6 and para 55 “ training a model using the sensor data (614)…”) the first trained machine learning model being capable of (Arabshahi para 55 “Once the model is trained, the internal weights/connections may be configured to receive a new batch of sensor outputs in a time series and determine whether they match the trained “fingerprint” of previous fault conditions.” Arabshahi para 44 “fault output may also include writing a fault indication in a process log, sending a record of the sensor measurements to a data store for analysis and/remodel training, stopping the process being executed by the wafer recipe, sounding an alarm, and/or any other method of alerting users and/or other systems of the possible fault condition.”) Arabshahi doesn’t teach dimensionality reduction. obtaining first manufacturing parameters, comprising input setting to a substrate manufacturing device to determine substrate processing conditions, associated with the second plurality of substrates; and (Arabshahi para 56 “each time the wafer recipe is executed, the resulting data set from the sensor outputs can be labeled and used to continuously train and retrain the model.“ Arabshahi para 3 “a wafer recipe that includes control inputs and timing constraints for a semiconductor processing system to process a semiconductor wafer.” The timing and control inputs are both input settings to a substrate manufacturing device to determine substrate processing conditions.) training a second machine learning model to predict as output based on input comprising the first manufacturing parameters by providing the (Arabshahi para 56 “each time the wafer recipe is executed, the resulting data set from the sensor outputs can be labeled and used to continuously train and retrain the model.“ Retraining creates a second model. Each time the wafer recipe is executed, that is another set of metrology data. Arabshahi’s output is the labels. The sensor outputs are the “training input” and the labels are the “target outputs”.) Arabshahi doesn’t teach dimensionality reduction. However, Middlebrooks teaches that the metrology data is obtained by performing second thickness or in-plane displacement measurements on a second plurality of substrates (Middlebrooks para 35 “ the one or more determined metrology metrics comprise one or more of overlay, a critical dimension, a reconstruction of a three dimensional profile of features of a substrate, or a dose or focus of a lithography apparatus at a moment when the features of the substrate were printed with the lithography apparatus.” 3d profile is thickness and displacement measurements. Overlay is thickness, e.g. 1 or 2 layer thickness/overlay.) reducing dimensionality of second metrology data. (Middlebrooks para 116 “variational encoder-decoder architecture. In the middle (e.g., middle layers) of the model (e.g., a neural network), the present model formulates a low dimensional encoding (e.g., latent space) that encapsulates information in an input (e.g., a complex electric field image and/or other input associated with a pattern or other features of a semiconductor manufacturing process) to the model.”) Arabshahi, Middlebrooks and the claims all use machine learning on wafer production data. It would have been obvious to a person having ordinary skill in the art, at the time of filing, to use dimensionality reduction in Arabshahi to “leverage the low dimensionality and compactness of the latent space to make determinations directly in the latent space.” Middlebrooks para 116. Arabshahi and Middlebrooks don’t teach manufacturing parameters as input to a ML model. However, Talukder teaches a second machine learning model to predict (Talukder para 2 “may use in situ measurements for process control during fabrication of a wafer. For example, in situ measurements may be used to accurately control an etch depth, a deposition depth, etc. during wafer fabrication.” Talukder abs “generating a second machine learning model using the ex situ data and the in situ measurements.” In situ measurements are manufacturing parameters. Applicant’s specification para 15 states ‘There are many manufacturing parameters (e.g., hardware parameters, process parameters, etc.) that cause the resulting properties of substrates.” The resulting property in Talukder is “etch depth”, and the parameter is the in situ measurement “for process control during fabrication…” Talukder para 2. Etch depth is a thickness measurement.) Arabshahi, Middlebrooks, Talukder and the claims all apply machine learning to manufacturing. It would have been obvious to a person having ordinary skill in the art, at the time of filing, to incorporate manufacturing parameters into Arabshahi’s input data when training the second model because “such a model may become out of specification… due to drift of the process chamber…” Talukder para 1. Middlebrooks teaches claims 2, 6 and 19. The method of claim 1, wherein the training of the first machine learning model comprises: reducing dimensionality of the first metrology data to form dimensionally reduced metrology data of the first plurality of substrates; and generating, based on the dimensionally reduced metrology data of the first plurality of substrates, first reconstructed data that is based on the first metrology data. (Middlebrooks para 131 “the dimensional data in the latent space is encoded by the encoder of the encoder-decoder architecture. In some embodiments, predictions, and/or other output from the parameterized model are generated by the decoder of the encoder-decoder architecture.” Middlebrooks para 40 “This may include, for example, a metrology target and/or other measurement structures. The targets may be located inside or outside product areas on a wafer, for example.” Middlebrooks para 116 “variational encoder-decoder architecture. In the middle (e.g., middle layers) of the model (e.g., a neural network), the present model formulates a low dimensional encoding (e.g., latent space) that encapsulates information in an input (e.g., a complex electric field image and/or other input associated with a pattern or other features of a semiconductor manufacturing process) to the model.”) Arabshahi teaches claims 3, 11 and 18. The method of claim 1, wherein: the first trained machine learning model is capable of second (Arabshahi clm 1 “providing the plurality of sensor outputs to a plurality of models, wherein the plurality of models are trained to identify when the conditions associated with the semiconductor processing system indicate a fault in the semiconductor wafer;”) the second machine learning model is to be further trained based on second data input comprising current data associated with production of the second plurality of substrates to perform the one or more corrective actions. (Arabshahi para 56 “each time the wafer recipe is executed, the resulting data set from the sensor outputs can be labeled and used to continuously train and retrain the model.“ Arabshahi para 44 “fault output may also include writing a fault indication in a process log, sending a record of the sensor measurements to a data store for analysis and/remodel training, stopping the process being executed by the wafer recipe, sounding an alarm, and/or any other method of alerting users and/or other systems of the possible fault condition.”) Arabshahi doesn’t teach dimensionality reduction. However, Middlebrooks teaches reducing dimensionality of second metrology data. (Middlebrooks para 116 “variational encoder-decoder architecture. In the middle (e.g., middle layers) of the model (e.g., a neural network), the present model formulates a low dimensional encoding (e.g., latent space) that encapsulates information in an input (e.g., a complex electric field image and/or other input associated with a pattern or other features of a semiconductor manufacturing process) to the model.”) Arabshahi teaches claim 12. The method of claim 3, wherein the current data comprises one or more of sensor data or manufacturing parameters. (Arabshahi para 56 “each time the wafer recipe is executed, the resulting data set from the sensor outputs can be labeled and used to continuously train and retrain the model.“) Arabshahi teaches claims 5 and 13. The method of claim 1, wherein the one or more corrective actions comprise one or more of: providing an alert to a user; updating process parameters of the second manufacturing equipment; updating hardware parameters of the second manufacturing equipment; correcting sensor drift of sensors associated with the second manufacturing equipment; correcting chamber drift associated with the second manufacturing equipment; or updating a process recipe to produce subsequent substrates. (Arabshahi para 44 “fault output may also include writing a fault indication in a process log, sending a record of the sensor measurements to a data store for analysis and/remodel training, stopping the process being executed by the wafer recipe, sounding an alarm, and/or any other method of alerting users and/or other systems of the possible fault condition.” Arabshahi para 55 “Once the model is trained, the internal weights/connections may be configured to receive a new batch of sensor outputs in a time series and determine whether they match the trained “fingerprint” of previous fault conditions.”) Arabshahi teaches claims 6 and 19. The method of claim 2, wherein the reducing of the dimensionality of the first metrology data is via non-linear fit. (Arabshahi para 102 “ the structure or profile of the target giving rise to the detected spectrum may be reconstructed, e.g. by Rigorous Coupled Wave Analysis and non-linear regression or by comparison with a library of simulated spectra.”) Middlebrooks teaches claims 7 and 14. The method of claim 1, wherein the first metrology data comprises spatial maps across surfaces of the first plurality of substrates of one or more of thickness data or in-plane displacement data. (Middlebrooks para 35 “ the one or more determined metrology metrics comprise one or more of overlay, a critical dimension, a reconstruction of a three dimensional profile of features of a substrate, or a dose or focus of a lithography apparatus at a moment when the features of the substrate were printed with the lithography apparatus.” Three-dimensional profile features of a substrate is a spatial map of thickness data and displacement data.) Middlebrooks teaches claims 8, 15 and 20. The method of claim 1, wherein the first machine learning model is a convolutional neural network model. (Middlebrooks para 114 “In some embodiments, the intermediate layers of the one or more neural networks include one or more convolutional layers, one or more recurrent layers, and/or other layers.”) Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Austin Hicks whose telephone number is (571)270-3377. The examiner can normally be reached Monday - Thursday 8-4 PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mariela Reyes can be reached at (571) 270-1006. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AUSTIN HICKS/Primary Examiner, Art Unit 2142
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Prosecution Timeline

Show 6 earlier events
Oct 01, 2025
Final Rejection mailed — §103
Jan 28, 2026
Request for Continued Examination
Feb 06, 2026
Response after Non-Final Action
Feb 26, 2026
Non-Final Rejection mailed — §103
May 15, 2026
Examiner Interview Summary
May 15, 2026
Applicant Interview (Telephonic)
May 26, 2026
Response Filed
Jun 17, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
75%
Grant Probability
99%
With Interview (+25.8%)
3y 2m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 418 resolved cases by this examiner. Grant probability derived from career allowance rate.

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