DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Amendment filed 28 December 2025 is acknowledged. Claim 1 has been amended. Claims 1 and 5-16 are pending. Claims 9-16 remain withdrawn from consideration.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 5-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitations, “said gate on said first region,” and, “said gate on said second region.” There is insufficient antecedent basis for these limitations in the claim.
Claims 5-8 are rejected for merely containing the flaws of the parent claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (US Patent Application Publication 2016/0240646, hereinafter Chiu ‘646) in view of Wong et al. (US Patent Application Publication 2022/0376053, hereinafter Wong ‘053), Chen et al. (US Patent Application Publication 2021/0175343, hereinafter Chen ‘343), Liu et al. (US Patent Application Publication 2024/0030331, hereinafter Liu ‘331), and Hwang et al. (US Patent Application Publication 2020/0328296, hereinafter Hwang ‘296), all five of record.
With respect to claim 1, Chiu ‘646 teaches (FIGs. 2 and 3) a semiconductor device provided with features of depletion mode (D-mode) (see FIG. 3) and enhancement mode (E-mode) (see FIG. 2) GaN devices substantially as claimed, including:
a substrate (102) with a first region (200) and a second region (300) defined thereon ([0017, 0023, 0027]);
a GaN channel layer (108) on said substrate (102) ([0018]);
an AlGaN layer (110) on said GaN channel layer (108) ([0018]);
a p-GaN layer (123; when selected as p-type) on said AlGaN layer (110) in said first region (200) ([0025, 0046]);
an Al-based passivation layer (112 when selected from AlN or AlxB1-xN) on said AlGaN layer (110) and said p-GaN layer (123) ([0019]);
a first Si-based passivation layer (114 when selected from SiNx or SiOx) on said Al-based passivation layer (112) ([0019]);
a second Si-based passivation layer (124 when selected from SiNx or SiOx) on said first Si-based passivation layer (114) ([0026]);
gate contact openings (125; see FIGs. 12 and 18), wherein one of said gate contact openings on said first region (200) extends through said Al-based passivation layer (112), said first Si-based passivation layer (114) and said second Si-based passivation layer (124) to a top surface of said p-GaN layer (123), and one of said gate contact openings on said second region (300) extends through said Al-based passivation layer, said first Si-based passivation layer and said second Si-based passivation layer to a surface of said AlGaN layer (110), and said top surface of said p-GaN layer and said surface of said AlGaN layer are both flat surfaces without recess feature ([0050, 0068]); and
a gate (122) formed in each of said gate contact openings (125) ([0020]).
Thus, Chiu ‘646 is shown to teach all the features of the claim with the exception of:
a titanium nitride hard mask layer on said p-GaN layer, wherein sidewalls of said titanium nitride hard mask layer are aligned with and flush with sidewalls of said p-GaN layer;
wherein the Al-based passivation layer is conformally on said AlGaN layer, said p-GaN layer and said titanium nitride hard mask layer;
wherein the first Si-based passivation layer is conformally on said Al-based passivation layer;
wherein the second Si-based passivation layer is conformally on said first Si-based passivation layer;
wherein the one of said gate contact openings on said first region extends to a top surface of said titanium nitride hard mask layer;
parts of said Al-based passivation layer, said first Si-based passivation layer and said second Si-based passivation layer vertically overlap said titanium nitride hard mask layer; and
wherein said gate on said first region is connected directly with said titanium nitride hard mask layer and said gate on said second region is connected directly with said AlGaN layer.
However, Wong ‘053 teaches (FIG. 1) a semiconductor device (1) comprising a titanium nitride hard mask layer (17) on a p-GaN layer (16 when selected from p-type GaN); wherein an Al-based passivation layer (18 when selected from Al2O3 or AlN) is conformally on an AlGaN layer (15 when selected from AlGaN), said p-GaN layer and said titanium nitride hard mask layer; wherein a first Si-based passivation layer (19 when selected from Si3N4 or SiO2) is conformally on said Al-based passivation layer; wherein a second Si-based passivation layer (22 when selected from Si3N4 or SiO2) is on said first Si-based passivation layer; wherein a gate contact opening (opening housing gate 25) extends to a top surface of said titanium nitride hard mask layer; parts of said Al-based passivation layer, said first Si-based passivation layer and said second Si-based passivation layer vertically overlap said titanium nitride hard mask layer; and wherein said gate (25) on said first region is connected directly with said titanium nitride hard mask layer to protect and provide etch selectivity for an underlying semiconductor layer, to improve bias voltage control of a conductor, to improve a switching speed of a gate, and to reduce leakage current and improve a threshold voltage ([0026, 0028-0033, 0037]).
Further, Chen ‘343 teaches (FIG. 5) sidewalls of a titanium nitride hard mask layer (20) aligned with and flush with sidewalls of a p-GaN layer (18) to further protect and provide etch selectivity for the underlying semiconductor layer ([0013, 0018-0019]).
Still further, Liu ‘331 teaches (FIG. 1) conformally forming a series of passivation layers (120) such that a second Si-based passivation layer (126 when selected from SiO2) is conformally on a first Si-based passivation layer (124 when selected from Si3N4) to effectively block unwanted oxygen diffusion ([0006]).
Still further, Hwang ‘296 teaches (FIG. 1) a gate (34) on a second region connected directly with an AlGaN layer (24) to effectively control the flow of carriers in a simple construction that does not require the additional processing of an insulating layer ([0061]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor device of Chiu ‘646 further comprising a titanium nitride hard mask layer on said p-GaN layer; wherein the Al-based passivation layer is conformally on said AlGaN layer, said p-GaN layer and said titanium nitride hard mask layer; wherein the first Si-based passivation layer is conformally on said Al-based passivation layer; wherein the second Si-based passivation layer is on said first Si-based passivation layer; wherein the one of said gate contact openings on said first region extends to a top surface of said titanium nitride hard mask layer; parts of said Al-based passivation layer, said first Si-based passivation layer and said second Si-based passivation layer vertically overlap said titanium nitride hard mask layer; and wherein said gate on said first region is connected directly with said titanium nitride hard mask layer as taught by Wong ‘053 to protect and provide etch selectivity for an underlying semiconductor layer, to improve bias voltage control of a conductor, to improve a switching speed of a gate, and to reduce leakage current and improve a threshold voltage; to have formed sidewalls of said titanium nitride hard mask layer of Chiu ‘646 and Wong ‘053 aligned with and flush with sidewalls of said p-GaN layer as taught by Chen ‘343 to further protect and provide etch selectivity for the underlying semiconductor layer; to have formed the second Si-based passivation layer of Chiu ‘646, Wong ‘053, and Chen ‘343 conformally on said first Si-based passivation layer as taught by Liu ‘331 to effectively block unwanted oxygen diffusion; and to have formed said gate on said second region of Chiu ‘646, Wong ‘053, Chen ‘343, and Liu ‘331 connected directly with said AlGaN layer as taught by Hwang ‘296 to effectively control the flow of carriers in a simple construction that does not require the additional processing of an insulating layer.
With respect to claim 5, Chiu ‘646, Wong ‘053, Chen ‘343, Liu ‘331, and Hwang ‘296 teach the device as described in claim 1 above, but primary reference Chiu ‘646 does not explicitly teach the additional limitation wherein said top surface of said titanium nitride hard mask layer is a flat surface without recess feature.
However, Wong ‘053 teaches (FIG. 1) a semiconductor device (1) comprising a top surface of a titanium nitride hard mask layer (17) having a flat surface without recess feature to protect and provide etch selectivity for an underlying semiconductor layer, to improve bias voltage control of a conductor, to improve a switching speed of a gate, and to reduce leakage current and improve a threshold voltage ([0029-0030]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor device of Chiu ‘646, Wong ‘053, Chen ‘343, Liu ‘331, and Hwang ‘296 wherein said top surface of said titanium nitride hard mask layer is a flat surface without recess feature as taught by Wong ‘053 to protect and provide etch selectivity for an underlying semiconductor layer, to improve bias voltage control of a conductor, to improve a switching speed of a gate, and to reduce leakage current and improve a threshold voltage.
With respect to claim 6, Chiu ‘646 teaches further comprising metal gates or metal compound gates (122) on said top surface of said p-GaN layer (123) and on said surface of said AlGaN layer (110) ([0020]).
With respect to claim 7, Chiu ‘646 teaches a material of said metal gates or metal compound gates (122) comprises titanium (Ti) or titanium nitride (TiN) ([0020]).
With respect to claim 8, Chiu ‘646 teaches wherein a material of said Al-based passivation layer (112) is aluminum oxide (Al2O3) or aluminum nitride (AlN) ([0019]).
Response to Arguments
Applicant’s arguments with respect to amended claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.M.R./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893