The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (2013/0009226).Regarding claim 13, Park et al. teach in figure 6A and related text a semiconductor memory device, comprising:
a substrate 100 comprising active regions AR (see figure 6B) defined by a device isolation layer 104, each active region including a first impurity region and a second impurity region (inherently therein);
word lines 112 on the active regions and extending in a first direction;
bit line structures 140/145 on the word lines, each bit line structure including a contact portion 134a connected to a first impurity region of the active regions, and a line portion (arbitrarily chosen) on the contact portion and extending in a second direction that crosses the first direction;
contact plugs 148 between the bit line structures and connected to respective second impurity regions;
a connection pattern 134b that connects one of the contact plugs to the respective second impurity regions of the active regions; and
a separation insulating pattern 106a below the line portion,
wherein the connection pattern 134b comprises:
a first surface (see figure 6B) that is concave toward the contact portion; and
a second surface opposite to the first surface that is convex toward the separation insulating pattern,
wherein the contact portion 134a is confined by a spacer 138 in the first direction and by a sidewall insulating pattern 106a in the second direction, wherein the spacer and the sidewall insulating pattern are distinct structures.
Park et al. do not explicitly state that the first surface that is concave toward the contact portion; and the second surface opposite to the first surface that is convex toward the separation insulating pattern.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the first surface as concave toward the contact portion; and the second surface opposite to the first surface as convex toward the separation insulating pattern, in Park et al.’s device, in order to form the device as intended by Park et al. based on the drawing’s disclosure.
Regarding claim 14, Park et al. do not explicitly state that a curvature radius of the second surface is larger than a curvature radius of the first surface. However, figure 6B depicts that a curvature radius of the second surface is larger than a curvature radius of the first surface (annotated FIG. 6B; the radii of the surfaces share the same center point, therefore the curvature radius of the second surface must be greater than that of the first surface. Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the curvature radius of the second surface larger than a curvature radius of the first surface, in Park et al.’s device, in order to form the device as intended by Park et al.
Regarding claim 15, Park et al. teach in figure 6A and related text that the spacer covers a side surface of the line portion, wherein the spacer extends into a region between the first surface and the contact portion.
Regarding claim 16, Park et al. teach in figure 6A and related text that the first surface is in contact with the spacer.
Regarding claim 17, Park et al. teach in figure 6A and related text that the connection pattern is a first connection pattern, the semiconductor memory device further comprising a second connection pattern connected to a different active region, and wherein the first connection pattern and the second connection pattern have a mirror symmetry about the separation insulating pattern (since the memory cell comprises pluralities of identical cells).
Regarding claim 18, Park et al. teach in figure 6A and related text that the insulating pattern is below the line portion.
Regarding claim 20, Park et al. teach in figure 6A and related text semiconductor memory device, comprising:
a substrate 100 comprising active regions AR defined by a device isolation layer 104, each active region including a first impurity region and a second impurity region;
word lines 112 on the active regions and extending in a first direction;
a gate dielectric layer 110 between the word lines and the active regions;
bit line structures 145 on the word lines, each of the bit line structures comprising a contact portion 134a connected to a first impurity region of the active regions, and a line portion (arbitrarily chosen), which is on the contact portion and is extended in a second direction crossing the first direction;
contact plugs 148 between the bit line structures and connected to the second impurity regions, respectively;
connection patterns 134b connecting the contact plugs to the second impurity regions of the active regions; and
a capacitor 150 that is connected to the second impurity regions through the contact plugs and the landing pads,
wherein each of the connection patterns 134b comprises:
a first concave surface that faces the contact portion (see figure 6B and the discussion with respect to claim 13); and
a second convex surface that is opposite to the first concave surface, and
wherein a center width in the first direction of each of the connection patterns 134b at a center region thereof is less than an edge width in the first direction of the connection pattern at an edge portion thereof (see figure 6B),
wherein the contact portion 134a is confined by a spacer 138 in the first direction and by an insulating pattern 106a in the second direction, wherein the spacer and the insulating pattern are distinct structures.
Park et al. do not teach forming landing pads on the contact plugs such that a gapfill structure that at least partially fills a region between the landing pads.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form landing pads on the contact plugs such that a gapfill structure that at least partially fills a region between the landing pads, in Park et al.’s device in order to improve the contact resistance of the device.
Claims 11 and 19 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (2013/0009226) in view of Kim et al. (2017/0294439).Regarding claims 11 and 19, Park et al. teach in figure 6A and related text that the sidewall insulating pattern 106a comprises: a first surface in contact with a side surface of the contact portion 134a; and a second surface that is opposite to the first surface. Park et al. do not teach that the first surface of the sidewall insulating pattern is concave in the second direction and the second surface of the sidewall insulating pattern is convex in the second direction, when viewed in a plan view.
Kim et al. teach in figure 1A and related text that the first surface of the sidewall insulating pattern 135P is concave in the second direction and the second surface of the sidewall insulating pattern is convex in the second direction, when viewed in a plan view.
Kim et al. and Park et al. are analogous art because they are directed to memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Park et al. because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the first surface of the sidewall insulating pattern 135P is concave in the second direction and the second surface of the sidewall insulating pattern is convex in the second direction, when viewed in a plan view, as taught by Kim et al. in Park et al.’s device, in order to prevent electrical shorts between capacitor conductive contact patterns (Kim, [0071]).
Claims 1-10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (2013/0009226) in view of Nakao (8,907,389).Regarding claim 1, Park et al. teach in figure 6A and related text a semiconductor memory device, comprising:
a substrate 100 including active regions defined by a device isolation layer 104, each active region including a first impurity region and a second impurity region; word lines provided on the active regions and extending in a first direction;
bit line structures 140/145 on the word lines, each of the bit line structures including a contact portion 134a connected to a first impurity region of the active regions, and a line portion (arbitrarily chosen), which is provided on the contact portion and which extends in a second direction that crosses the first direction;
contact plugs 148 between the bit line structures and connected to respective second impurity regions; and
connection patterns 134a that connect the contact plugs to the second impurity regions of the active regions,
wherein each of the connection patterns 134b comprises:
a first surface that faces the contact portion 134a; and
a second surface that is opposite to the first surface, and
wherein the first surface is concave in the first direction (see figure 6B) and the second surface is convex in the first direction, when viewed in a plan views.
Park et al. do not teach that the first surface is longer than the second surface in the plan view.
Nakao teaches in figure 1 and related text contact plugs 25 connected to respective second impurity regions 5; and
connection patterns 15 that connect the contact plugs to the second impurity regions of the active regions,
wherein each of the connection patterns 15 comprises:
a first surface that faces the contact portion; and
a second surface that is opposite to the first surface, and
wherein the first surface is concave (at least part thereof) in the first direction and the second surface is convex (at least part thereof) in the first direction, when viewed in a plan views, wherein the first surface is longer than the second surface in the plan view (since the first surface comprises sharper picks which inherently are longer than the second surface which comprises smoother surface. Additionally, the length of the first surface can be arbitrarily chosen such that it is longer than the second surface).
Nakao and Park et al. are analogous art because they are directed to semiconductor devices comprises plugs and one of ordinary skill in the art would have had a reasonable expectation of success to modify Park et al. because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the first surface is longer than the second surface in the plan view, as taught by Nakao in Park et al.’s device, in order to improve the adhesion between the elements.
Regarding claim 2, in the combined device, a curvature radius of the second surface is larger than a curvature radius of the first surface.
Regarding claim 3, Park et al. teach in figure 6A and related text a spacer 138 that covers a side surface of the line portion, wherein the spacer extends into a region between the first surface and the contact portion.
Regarding claim 4, Park et al. teach in figure 6A and related text the first surface contacts the spacer.
Regarding claim 5, Park et al. teach in figure 6A and related text a separation insulating pattern 106a in contact with the second surface, wherein a surface of the separation insulating pattern that is in contact with the second surface is concave in the first direction (see figure 6B).
Regarding claim 6, Park et al. teach in figure 6A and related text the connection patterns comprise a first connection pattern and a second connection pattern, which are connected to respective active regions and are adjacent to each other in the first direction, and wherein the first connection pattern and the second connection pattern have a mirror symmetry about the separation insulating pattern (see figure 6B).
Regarding claim 7, Park et al. teach in figure 6A and related text a first surface of the separation insulating pattern is in contact with the first connection pattern, and a second surface of the separation insulating pattern is in contact with the second connection pattern.
Regarding claim 8, Park et al. teach in figure 6B and related text each of the connection patterns further comprises a third surface and a fourth surface (since the device is a 3D device), each of which connects the first surface to the second surface, and when viewed in a plan view, the third surface and the fourth surface have a line shape.
Regarding claim 9, Park et al. teach in figure 6A and related text intermediate insulating patterns 114 that at least partially fill spaces between the bit line structures, wherein the intermediate insulating patterns comprise a first intermediate insulating pattern that faces the third surface of the connection patterns and a second intermediate insulating pattern that faces the fourth surface of the connection patterns.
Regarding claim 10, Park et al. teach in figure 6A and related text sidewall insulating patterns 106a, which are below the line portion and are in contact with a side surface of the contact portion 134a, wherein each contact portion is enclosed by a pair of the sidewall insulating patterns 106a and a pair of spacers 138, when viewed in a plan view.
Regarding claim 12, Park et al. teach in figure 6A and related text a center width in the first direction of a first of the connection patterns 134b at a center portion thereof is less than an edge width in the first direction of the first connection pattern at an edge portion thereof (see figure 6B).
Response to Arguments
Applicant’s arguments with respect to the claim(s) have been considered but are moot because of the new ground of rejection and also due to considering the “contact portion” as being element 134a in Park et.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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O.N. /ORI NADAV/
5/30/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800
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