DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 4, 6, 9-11, 14, 17-18, 20-23 and 25-28 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Claim 1 recites " A method performed by an electronic device, the method comprising:" which comprising steps of " receiving semiconductor wafer images; determining, by the electronic device, an operation mode from among different operation modes, here each of the operation modes includes a respective processing operation to be performed on candidate semiconductor wafer images implementing, by the electronic device, the determined operation mode by performing the respective processing operation of the determined operation on a candidate semiconductor wafer image from among the semiconductor wafer images; and in response to a semiconductor wafer image result of the performed respective processing operation, determining, by the electronic device, whether the semiconductor image, represents a semiconductor wafer defect by implementing a defect prediction machine learning model to predict a wafer defect in the semiconductor wafer image.". Therefore, it is a process.
Step 2A, Prong 1: Judicial exception recited? Yes. Each limitation as recited in the claim, is a process that, under BRI covers performance of the limitation in the mind but for the recitation of a generic "electronic device" which is a mere indication of the field of use. Nothing in the claim elements precludes the steps from practically being performed in the mind. The mere nominal recitation of a generic technical system does not take the claim limitation out of mental process grouping. Thus the claim recites a mental process.
Each limitation as recited in claim, is a process that, under its broadest limitation, covers performance of the limitation in the mind but for the recitation of a generic "electronic device" which is a mere indication of the field of use. Nothing in the claim elements precludes the steps from practically being performed in the mind. The mere nominal recitation of a generic technical system does not take the claim limitation out of the mental processes grouping.
2A-Prong 2: Integrated into a practical application? No.
This judicial exception is not integrated into a practical application because the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. The claim when viewed alone or in combination recites data gathering such as " receiving semiconductor wafer images; determining, by the electronic device, an operation mode from among different operation modes, here each of the operation modes includes a respective processing operation to be performed on candidate semiconductor wafer images implementing, by the electronic device, the determined operation mode by performing the respective processing operation of the determined operation on a candidate semiconductor wafer image from among the semiconductor wafer images; and in response to a semiconductor wafer image result of the performed respective processing operation, determining, by the electronic device, whether the semiconductor image, represents a semiconductor wafer defect by implementing a defect prediction machine learning model to predict a wafer defect in the semiconductor wafer image".
Step 2B: No. The recited limitations "receiving semiconductor wafer images; determining, by the electronic device, an operation mode from among different operation modes, here each of the operation modes includes a respective processing operation to be performed on candidate semiconductor wafer images implementing, by the electronic device, the determined operation mode by performing the respective processing operation of the determined operation on a candidate semiconductor wafer image from among the semiconductor wafer images; and in response to a semiconductor wafer image result of the performed respective processing operation, determining, by the electronic device, whether the semiconductor image, represents a semiconductor wafer defect by implementing a defect prediction machine learning model to predict a wafer defect in the semiconductor wafer image." are merely data gathering.
Therefore, claim 1 is ineligible.
Similarly, claims 1, 6, 9-11, and 27-28 do not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Claims 14, 17, 18, 20, 21-23 recite "at least one processor" and "memory" which do not offer a meaningful limitation beyond generally linking the apparatus or medium to a particular environment, that is, implementation via an "processor". In other words, the apparatus and medium claims are no different from the method of claim 1 in substance; the method claim recites a mental process while the apparatus claim recites generic components configured to implement the same judicial exception. The claim do not amount to significantly more than the underlying mental process for the same reasons as applied above in claims 14, 17, 18, 20, 21-23.
Claim 4 merely adds a training step which again is merely data gathering as such for the same reasons applied above, claim 4 is also held as ineligible.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, 6, 11, 14, 17-18, 23, 25, and 27-28 are rejected under 35 U.S.C. 103 as being unpatentable over Okuno et al. (U.S. PGPub No. 2023/0410285 A1) in view of Chen et al. (U.S. PGPub No. 2022/0383473 A1).
As to claims 1, 4, 14 and 17, Okuno discloses and shows in figures 2 and 8, an electronic device comprising:
at least one processor (110) configured to receive images (i.e. electronic circuit images) ([0065], ll. 8-11; [0102], ll. 3-5; [0103], ll. 1-3);
a memory storing (120) instructions that, when executed by the at least one processor, configure the at least one processor to ([0070]):
determine an operation from among different operation modes mode (i.e. structure of learning model e.g. 1-3 as disclosed), where each of the operation modes includes a respective processing operation to be performed on candidate images ([0086]-[0088]; [0104]); and
implement the determined operation mode (i.e. structures 1-3, which each have specific kernels) through performance of the respective processing operation of the determined operation on a candidate image from among the images (i.e. the feature extractor from each respect model which has each respective kernel) ([0105]);
in response to an image result of the performed respective processing operation determine, whether an image, represents a defect by implements a defect prediction machine learning model to predict a (i.e. an abnormality) by predicting a defect in the image using a defect prediction model (i.e. feature extractor which is part of model 200) ([0105]-[0107]).
further comprising: training the defect prediction model with training data, wherein the defect prediction model is trained to predict types of wafer defects (i.e. fold, bend, chip, scratch or stain), and wherein the predicted wafer defect is one of the types of wafer defects (implied in any image that has the defective as this is the sole purpose of the inspection) ([0065], ll. 11-16).
Okuno explicitly discloses in ([0065]) that the sample under test that the images are a function of include circuit boards. Circuits as known in the art are a function of semiconductor wafers, in that they are a specific sub-section of a wafer, as such implicitly the images of circuits are also that of a semiconductor wafer after processing, the claim does not require any limitation on what state the semiconductor wafer is in, as such the limitation could be said to be implicitly taught by Okuno. However, merely for compact prosecution the examiner is providing an additional reference to provide evidence that circuits are formed on semiconductor wafers.
Okuno therefore does not explicitly disclose where the images are semiconductor wafer images.
However, Chen does disclose and show in figure 4a-c and (Abstract) the basic concept that circuitry is formed on semiconductor wafers. As such obviously the images of Okuno when being taken of circuitry are also broadly speaking of semiconductor wafers.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Okuno where the images are semiconductor wafer images in order to provide the advantage of increased versatility and expected results, obviously if the images under analysis for anomalies are that of semiconductor wafer circuitry the invention of Okuno can be applied for defect analysis on an extremely large and vital area for defect inspection.
The subject matter of claims 1 and 14 relate in that the technical features of apparatus claim 14 are in each case suitable for implementing the method of claim 1, therefore the method is obvious, in view of the above apparatus rejection.
As to claim 6, Okuno discloses a method, wherein the performing of the respective processing operation of the determined operation mode includes: based on an image quality of the candidate semiconductor wafer images being determined to not satisfy a preset image quality standard (i.e. resizing or not based on the desired degree of accuracy as disclosed), restoring the candidate semiconductor wafer image to satisfy the preset quality standard ([0111]).
As to claims 11 and 23, Okuno discloses a method, wherein the defect prediction machine learning model performs the prediction of the wafer defect based on at least one of a scene graph of the semiconductor wafer image, temperature information related to the semiconductor wafer image, noise information on the semiconductor wafer image, or sensor data related to the semiconductor wafer image (where the examiner is interpreting pixel data is sensor data from the camera) ([0065], ll. 6-8; [0067], ll. 1-6).
As to claim 18, Okuno discloses an electronic device wherein the received semiconductor wafer images all have a same preset size, and wherein, for the performance of the respective processing operation of the determined operation mode, the execution of the instructions are further configures the at least one processor to ([0103]):
Based on a quality of the candidate semiconductor wafer image being determined to not satisfy a preset quality standard, restore the candidate semiconductor wafer image to satisfy the preset quality standard as the respective processing operation of the determined operation mode ([0110]-[0111]).
As to claim 25, Okuno disclose a method, wherein the semiconductor wafer images have a same preset size (preset by the camera which takes the noted images) ([0097], ll. 1-7; for example 256x256 or simply “original size”).
As to claim 27, Okuno discloses a method, wherein the performing of the respective processing operation of the determined operation mode includes selectively resizing the candidate semiconductor wafer image or selectively restoring the candidate semiconductor wafer image to move a region of interest (ROI) within the candidate semiconductor wafer image (where the examiner argues that inherently if the ROI is present and the image is resized the ROI moves inherently in being made either larger or smaller in size, applicant has not claimed any specific move location, merely that it moves) ([0067], ll. 7-10; where both compression and trimming reduce the ROI location relative to the original image).
As to claim 28, Okuno discloses a method, wherein the determining of the operation mode includes determining the operation mode from among the different operation modes based on a consideration of respective information of multiple of the semiconductor wafer images ([0086]-[0088], [0104]; clearly Okuno does not intended the operation mode to be a function of a single image, as disclose “The controller 110 changes the structure of the learning model 200 in accordance with the image sizes of the inspection images 350”)
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 4, 6, 9-11, 14, 17-18, 20-23 and 25-28 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Specifically with regards to the circuit from Okuno being not a semiconductor wafer image. The examiner notes again as noted above that implicitly a circuit is structured on a semiconductor wafer, but also again as provided above for evidence this is a known way of forming circuits.
Applicant's arguments filed 11/17/2025 have been fully considered but they are not persuasive.
As to applicant’s argument that Okuno does not use the model to predict a defect the examiner respectfully disagrees. This is explicitly shown in the flow chart of the controller in figure 6. Applicant appears to be arguing that the abnormality is not directly detected from a model which may be a persuasive argument, however not one commensurate with the broadest reasonable interpretation of the claims. The claims merely require that at some point a model is used as part of the prediction of the defect, as such the prior art does use said model as part of the prediction as shown in the figure 6.
As to the argument that Okuno focuses on not making adjust to sizes of the inspection image, the examiner does agree that this is disclosed in detail in Okuno. However, Okuno provides a teach as well of adjusting image size produced below for clarity. As such the rejection is maintained. “The captured image may be changed to an image having an image size of 512 by 512 pixels or 1024 by 1024 pixels, by trimming, compression, or the like” from [0067].
As to applicant’s argument regarding Okuno seemingly not disclosing determination of operation modes, the examiner respectfully disagrees. The examiner is unclear how applicant is interpreting the selection of 1 of 3 kernels (i.e. 1-3 structures) as disclosed as not a selection of operation modes. The argument is not found to be clear enough to reasonably challenge beyond nothing that the kernels are inherently operations and as such meet the claim limitation.
As to applicant’s argument regarding the selection of the kernel happening before the prediction model, the examiner agrees with applicant’s argument. As noted in applicant’s claim, the second and third claim elements pick and implement an operation (i.e. 1-3 structures/kernels) and then apply the model. The argument is therefore agreed as applicant has stated that the prior art discloses the claimed subject matter as claimed. The claim does not require the operations to come after the model use as seemingly argued.
As to applicant’s arguments that the learning model doesn’t include defect analysis (i.e. abnormality analysis), the examiner respectfully disagrees. “With reference to FIGS. 6 to 8, the following describes abnormality detection processing to be executed using the learning model 200 generated through the foregoing learning processing.”
As to applicant’s argument with respect to Okuno not showing prediction. Applicant is pointed to their own disclosure. “Specifically, in operation 316 the semiconductor wafer image processor 140 may identify a defect in the semiconductor wafer image by using a defect prediction model. In this case, in some implementations, the defect prediction model may be a model that may identify at least one piece of defect-type data related to the semiconductor wafer image. In addition, as described above, the defect prediction model may be trained by analyzing and learning a plurality of pieces of mixed defect-type data related to a plurality of semiconductor wafer images.” (from [0111] of applicant’s specification). As applicant seems to be arguing that their model predicts in the sense of guesses at a future defect, however this is not the broadest reasonable interpretation based on applicant’s own disclosure. Applicant explicitly defines prediction as simply identifying, which Okuno explicitly does noted in the citations. The examiner suggests for compact prosecution if support is present to more clearly define the model and what it actually does to potentially overcome the prior art of record (i.e. define the actual process of the prediction).
As to Okuno not disclosing using the model to perform the defect analysis. The citation quoted above discloses the model performs the anomaly detection, the anomalies as noted by applicant being “fold, a bend, a chip, a scratch, or a stain“. As such the rejection is maintained as Okuno does teach the noted language.
As to the argument regarding claim 6, this is moot in view of the new grounds of rejection.
As to the analysis with regard to claims 11/23, the examiner respectfully disagrees. Okuno discloses defect analysis (i.e. anomaly detection) and this is explicitly a function of applicant’s broadly claimed “sensor data related to the semiconductor wafer image”. As all digital images are a function of sensor data. Applicant seems to be arguing limitations not present, or important some manner of limitation not found to be the broadest reasonable interpretation of the claim.
As to the argument with respect to claim 18, the examiner respectfully disagrees that this is not taught by Okuno. In [0111] it is stated “[0111] In a case where an inspection image 350 has a large image size, a feature map 355 having a size of 8 by 8 pixels causes deterioration of detection accuracy in the abnormality determination since the information is significantly lost due to compression. For example, the detection accuracy is deteriorated in a case where the image size of the inspection image 350 is equal to or more than a size of 1000 by 1000 pixels. In view of this, according to the present embodiment, a feature map 355 having a size proportional to an image size of an input image is extracted. That is, the input unit 111 charges the input image into the learning model 200 as it is without changing the image size of the input image. In other words, the input unit 111 charges the input image into the learning model 200 as it is without resizing the input image to a predetermined size. The feature map 355 having the size proportional to the size of the input image is obtained and the restored image 360 is obtained. With this configuration, according to the present embodiment, an abnormality is detected at a degree of accuracy equal to or more than a certain level, regardless of an image size of an image input to the input unit 111.” The examiner is interpreting that the accuracy to a certain level is the quality preset standard as claimed. That the operation performed is the changing of the input size of the image to match the model size. The restoration being he final output 360 as disclosed. The size requirement is explicitly taught as that is the basis for the change of image size to match the corresponding model. As such it is found all the limitations of the claim are met.
Examiner’s Note
Claims 9, 10, 21, 22 and 26 are not objected to currently at this time due to the 101 rejection. However, it is believed that if the 101 rejection could be overcome, the noted claims could potentially be relied upon for allowable subject matter.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL P LAPAGE whose telephone number is (571)270-3833. The examiner can normally be reached Monday-Friday 8-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tarifur Chowdhury can be reached at 571-272-2287. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Michael P LaPage/Primary Examiner, Art Unit 2877