DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
2. The Arguments filed January 29th, 2026 in response to the Non-Final Office Action mailed 09/30/2025.
3. Claims 1-20 remain pending in the application.
4. Claims 1-20 have been fully considered in examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Weisenbach (U.S. PG Pub No US2019/0295613A1) (of record).
Regarding claim 1, Weisenbach teaches a register file circuit (300) fig. 3 [0026] comprising:
a first write bit line (WBL) (WBL) fig. 3 [0023];
a first P-channel metal oxide semiconductor (PMOS) transistor (P1) fig. 3 [0027, 0034] including a source (transistor necessarily has a source/drain/gate) coupled to the WBL (WBL);
a first inverter (inverter of bit cell 0 comprising N1) fig. 3 [0026-0027] including an input (Vdd) [0021] coupled to a drain of the first PMOS transistor (P1);
a second PMOS transistor (P2) fig. 3 [0027] including a source coupled to an output (TSN) fig. 3 [0027] of the first inverter (comprising N1); and
a second WBL (WBLX) fig. 3 [0023] coupled to a drain of the second PMOS transistor (P2).
For the purposes of Examination, all components of the circuitry are considered, in a broad sense, to be “coupled” to one another through mutual electrical connections. Further, it is assumed that all transistors are necessarily provided with respective “source(s)”, “drain(s)”, and “gate(s)”.
Regarding claim 2, Weisenbach teaches the register file circuit (300) fig. 3 [0026] of claim 1. Weisenbach also teaches further comprising:
a first N-channel metal oxide semiconductor (NMOS) transistor (N3) fig. 3 [0033, 0029] including a gate coupled to the output (TSN) fig. 3 [0027] of the first inverter (inverter of bit cell 0 comprising N1) fig. 3 [0026-0027]; and
a second NMOS transistor (N4) fig. 3 [0033, 0029] including a source coupled to a drain of the first NMOS transistor (N3) (N4 and N3 are coupled).
Regarding claim 3, Weisenbach teaches the register file circuit (300) fig. 3 [0026] of claim 2. Weisenbach also teaches further comprising a first read bit line (RWL0) fig. 3 [0020] coupled to a drain of the second NMOS transistor (N4) fig. 3 [0033, 0029] (RWL0 and N4 are coupled).
Regarding claim 4, Weisenbach teaches the register file circuit (300) fig. 3 [0026] of claim 2. Weisenbach also teaches further comprising:
a third PMOS transistor (P7) fig. 3 [0031] including a gate coupled to the output (TSN) of the first inverter (inverter of bit cell 0 comprising N1) fig. 3 [0026-0027]; and
a fourth PMOS transistor (P6) fig. 3 [0032] comprising a source coupled to a drain of the third PMOS transistor (P7) (P6 and P7 are coupled).
Regarding claim 5, Weisenbach teaches the register file circuit (300) fig. 3 [0026] of claim 4. Weisenbach also teaches further comprising:
a first read bit line (RWL0) fig. 3 [0020, 0024] coupled to a drain of the second NMOS transistor (N4) fig. 3 [0033, 0029];
and a second read bit line (RWL1) fig. 3 [0020, 0024] coupled to a drain of the fourth PMOS transistor (P6) fig. 3 [0032].
Regarding claim 6, Weisenbach teaches the register file circuit (300) fig. 3 [0026] of claim 2. Weisenbach also teaches further comprising a second inverter (inverter of bit cell 0 comprising N2) fig. 3 [0026-0027] including an input (Vdd) fig. 3 [0020] coupled to an output (TSN) fig. 3 [0027] of the first inverter (inverter of bit cell 0 comprising N1) fig. 3 [0026-0027] and an output (CSN) fig. 3 [0027] coupled to a drain of the first NMOS transistor (N3) fig. 3 [0033, 0029].
Regarding claim 7, Weisenbach teaches the register file circuit (300) fig. 3 [0026] of claim 6. Weisenbach also teaches wherein a gate of the first PMOS transistor (P1) fig. 3 [0034, 0027] and a gate of the second PMOS transistor (P2) fig. 3 [0027, 0034] are coupled to a write word line (WWL0) fig. 3 [0023] (P1, P2, WWL0 mutually coupled).
Regarding claim 8, Weisenbach teaches a memory device (IC comprising 10) fig. 1 [0016-0018] comprising:
a memory (main memory 0017]);
a register file (20 comprising 300) fig. 1, fig. 3 [0017, 0026] comprising:
a first write bit line (WBL) (WBL) fig. 3 [0023];
a first P-channel metal oxide semiconductor (PMOS) transistor (P1) fig. 3 [0027, 0034] including a source (transistor necessarily has a source/drain/gate) coupled to the WBL (WBL);
a first inverter (inverter of bit cell 0 comprising N1) fig. 3 [0026-0027] including an input (Vdd) [0021] coupled to a drain of the first PMOS transistor (P1);
a second PMOS transistor (P2) fig. 3 [0027] including a source coupled to an output (TSN) fig. 3 [0027] of the first inverter (comprising N1); and
a second WBL (WBLX) fig. 3 [0023] coupled to a drain of the second PMOS transistor (P2).
For the purposes of Examination, all components of the circuitry are considered, in a broad sense, to be “coupled” to one another through mutual electrical connections. Further, it is assumed that all transistors are necessarily provided with respective “source(s)”, “drain(s)”, and “gate(s)”.
Regarding claim 9, Weisenbach teaches the memory device (IC comprising 10) fig. 1 [0016-0018] of claim 8. Weisenbach does not explicitly disclose wherein the memory device (IC comprising 10 comprising 20) is a static random-access memory (“SRAM”) - Weisenbach’s circuit schematic (in Fig. 3) depicts an SRAM cell in each Bit cell (e.g., see the six transistors within the dotted box for Bit cell 0).
In other words, a common SRAM cell comprises two cross-coupled inverters (e.g., 2 PMOS transistor and 2NMOS transistors, P1, P2, N1, N2 in Fig. 3) and two access transistors (N3 and N4 in Fig. 3). Also, Weisenbach explicitly describes the two cross-coupled inverters in [0027].
Therefore, claim 9 is anticipated by Weisenbach.
Regarding claim 10, Weisenbach teaches the memory device (IC comprising 10) fig. 1 [0016-0018] of claim 8. Weisenbach also teaches wherein the register file (300) fig. 3 [0026] further comprises:
a first N-channel metal oxide semiconductor (NMOS) transistor (N3) fig. 3 [0033, 0029] including a gate coupled to the output of the first inverter (inverter of bit cell 0 comprising N1) fig. 3 [0026-0027]: and
a second NMOS transistor (N4) fig. 3 [0033, 0029] including a source coupled to a drain of the first NMOS transistor (N3) fig. 3 [0033, 0029] (N1, N3, N4 mutually-coupled).
Regarding claim 11, Weisenbach teaches the memory device (IC comprising 10) fig. 1 [0016-0018] of claim 10. Weisenbach also teaches wherein the register file (300) fig. 3 [0026] further comprises a first read bit line (RWL0) fig. 3 [0020] coupled to a drain of the second NMOS transistor (N4) fig. 3 [0033, 0029] (RWL0 and N4 are coupled).
Regarding claim 12, Weisenbach teaches the memory device (IC comprising 10) fig. 1 [0016-0018] of claim 10. Weisenbach also teaches wherein the register file (300) fig. 3 [0026] further comprises:
a third PMOS transistor (P7) fig. 3 [0031] including a gate coupled to the output (TSN) of the first inverter (inverter of bit cell 0 comprising N1) fig. 3 [0026-0027]; and
a fourth PMOS transistor (P6) fig. 3 [0032] comprising a source coupled to a drain of the third PMOS transistor (P7) (P6 and P7 are coupled).
Regarding claim 13, Weisenbach teaches the memory device (IC comprising 10) fig. 1 [0016-0018] of claim 12. Weisenbach also teaches wherein the register file (300) fig. 3 [0026] further comprises:
a first read bit line (RWL0) fig. 3 [0020, 0024] coupled to a drain of the second NMOS transistor (N4) fig. 3 [0033, 0029];
and a second read bit line (RWL1) fig. 3 [0020, 0024] coupled to a drain of the fourth PMOS transistor (P6) fig. 3 [0032].
Regarding claim 14, Weisenbach teaches the memory device (IC comprising 10) fig. 1 [0016-0018] of claim 10. Weisenbach also teaches wherein the register file (300) fig. 3 [0026] further comprises a second inverter (inverter of bit cell 0 comprising N2) fig. 3 [0026-0027] including an input (Vdd) fig. 3 [0020] coupled to an output (CSN) fig. 3 [0027] of the first inverter (inverter of bit cell 0 comprising N1) fig. 3 [0026-0027] and an output coupled to a drain of the first NMOS transistor (N3) fig. 3 [0033, 0029] (components all mutually coupled).
Regarding claim 15, Weisenbach teaches the memory device (IC comprising 10) fig. 1 [0016-0018] of claim 14. Weisenbach also teaches wherein a gate of the first PMOS transistor (P1) fig. 3 [0034, 0027] and a gate of the second PMOS transistor (P2) fig. 3 [0027, 0034] are coupled to a write word line (WWL0) fig. 3 [0023] (P1, P2, WWL0 mutually coupled).
Regarding claim 16, Weisenbach teaches a method (400) fig. 4 [0035-0037] for register file generation (using 300) fig. 3 [0032], the method (400 using 300) comprising:
electrically coupling a source of a first P-channel metal oxide semiconductor (PMOS) transistor (P1) fig. 3 [0027, 0034] to a first write bit line (WBL) (WBL) fig. 3 [0023] (WBL, P1 mutually-coupled);
electrically coupling an input (Vdd) [0021] of a first inverter (inverter of bit cell 0 comprising N1) fig. 3 [0026-0027] to a drain of the first PMOS transistor (P1);
electrically coupling a source of a second PMOS transistor (P2) fig. 3 [0027] to an output of the first inverter (TSN) fig. 3 [0027]; and
electrically coupling a drain of the second PMOS transistor to a second WBL (WBLX).
For the purposes of Examination, all components of the circuitry are considered, in a broad sense, to be “coupled” to one another through mutual electrical connections. Further, it is assumed that all transistors are necessarily provided with respective “source(s)”, “drain(s)”, and “gate(s)”.
Regarding claim 17, Weisenbach teaches the method (400) fig. 4 [0035-0037] of claim 16. Weisenbach also teaches further comprising:
electrically coupling a gate of a first N-channel metal oxide semiconductor (NMOS) transistor (N3) fig. 3 [0033, 0029] to the output of the first inverter (inverter of bit cell 0 comprising N1) fig. 3 [0026-0027]; and
electrically coupling a source of a second NMOS transistor (N4) fig. 3 [0033, 0029] to a drain of the first NMOS transistor (N3) (N1, N3, N4 mutually-coupled).
Regarding claim 18, Weisenbach teaches the method (400) fig. 4 [0035-0037] of claim 17. Weisenbach also teaches further comprising electrically coupling a first read bit line to a drain of the second NMOS transistor (N4) fig. 3 [0033, 0029].
Regarding claim 19, Weisenbach teaches the method (400) fig. 4 [0035-0037] of claim 17. Weisenbach also teaches further comprising:
electrically coupling a gate of a third PMOS transistor (P7) fig. 3 [0031] to the output (TSN) [0027] of the first inverter (inverter of bit cell 0 comprising N1) fig. 3 [0026-0027]; and
electrically coupling a source of a fourth PMOS transistor (P6) fig. 3 [0032] to a drain of the third PMOS transistor (P7) fig. 3 [0031].
Regarding claim 20, Weisenbach teaches the method (400) fig. 4 [0035-0037] of claim 19. Weisenbach also teaches electrically coupling a first read bit line (RWL0) fig. 3 [0020, 0024] to a drain of the second NMOS transistor (N4) fig. 3 [0033, 0029]: and
electrically coupling a second read bit line (RWL1) fig. 3 [0020, 0024] to a drain of the fourth PMOS transistor (P6) fig. 3 [0032].
Response to Arguments
Applicant's arguments filed 01/29/2026 have been fully considered but they are not persuasive.
With respect to Applicant’s arguments that “In Weisenbach's circuit, however, P1 is actually part of an inverter used for a bit cell. Its source cannot be coupled to a write bit line because instead, it is coupled (exclusively) to a high voltage supply reference. The only transistors in Weisenbach that are coupled to its write bit lines are NMOS transistors (e.g., N3, N4).” and likewise “Weisenbach cannot teach its inverter having an input coupled to the drain of its first PMOS (P1) because P1, itself is part of the inverter. Its gate is coupled to the inverter input, but its drain is coupled to the input of the second inverter, as well as to the drain of its NMOS access transistor (N3).” Applicant's required interpretation of "coupled to" is narrower than that required by a broadest reasonable interpretation (BRI) of the term “coupled to.” Under a broad yet reasonable interpretation of the term “coupled to”, "WBL" (in Fig. 3 of Weisenbach) is coupled (e.g., electrically connected) to both source and drain of P1 sometime during operation of the SRAM. In other words, the access transistor N3 is switched "on", and P1 is also switched "on", then the source/drain of N3 is coupled (or electrically connected) to the source/drain of P1. Therefore, "coupled to" is disclosed by "electrically connected to", so it appears applicant is requiring a narrow interpretation in the Remarks that is not required by the current claim language. Likewise, the other claimed components are considered “coupled to” each other “through mutual electrical connections” – based on the interpretation of “coupled to” set forth in the Non-Final rejection of record, which has not been specifically addressed by Applicant’s Remarks filed 01/29/2026.
If the claims were amended to read "directly coupled to", as is reflected in the language of what is meant by the term “coupled to” in Applicant’s Remarks, then this amendment would overcome the 35 U.S.C. 102(a)(1) rejection of claim 1 in view of primary reference Weisenbach (U.S. PG Pub No US2019/0295613A1) (of record).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Liu (US 20160260474 A1) teaches another example of an SRAM structure with inverter circuitry.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 05/11/2026
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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