DETAILED ACTION
This application, 17/887273, attorney docket AD8401-US 111548-272705, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application is assigned to Intel Inc, and has an effective filing date of 8/12/2022 based on the filing date. Applicant's election without traverse of Group I, claims 1-15 in the reply filed on 11/17/2025 is acknowledged. Claims 16-20 are withdrawn from further consideration.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-12 are rejected under 35 U.S.C. 102a1/a2 as being anticipated by Park et al. (U.S. 2007/0155165).
As for claim 1,
Park teaches in figure 4B, a substrate (41) comprising:
a first layer (43);
a first volume of a first material in the first layer (liner 52, between the walls of 43), wherein the first volume of the first material in the first layer extends from a first side of the first layer to a second side of the first layer opposite the first side of the first layer;
a second layer (44) on the first side of the first layer;
a second volume (52 between walls of 44) of a second material in the second layer, wherein the second volume of the second material extends from a first side of the second layer to a second side of the second layer opposite the first side of the second layer; and
wherein the second volume of the second material in the second layer is adjacent to the first volume of the first material in the first layer. (it is directly above and contiguous)
As for claim 2,
Park teaches the substrate of claim 1, wherein the second volume of the second material completely overlaps the first volume of the first material in the first layer (from the top view, the second volume completely covers the first volume).
As for claim 3,
Park teaches the substrate of claim 1, wherein a bottom surface of the first volume of the first material in the first layer proximate to the second side of the first layer is not coplanar with the second side of the first layer. (it extends only to the top of the transistor gate 42b).
As for claim 4,
Park teaches the substrate of claim 1, wherein the first material includes a selected one or more of: an epoxy material, a liquid mold material, or dielectric material; and wherein the second material includes a selected one or more of: a dielectric or an epoxy. (Liner 56 is a dielectric TaN. [0033]).
As for claim 5,
Park teaches the substrate of claim 1, and teaches that the first material and the second material are a same material. (they are continuous, and deposited together).
As for claim 6,
Park teaches the substrate of claim 1, and teaches a liner over the first liner [0037], which, when remapped to the first material, the first liner 56 physically separates the first volume of the liner of the first material from the first layer and physically separates the second volume of the second material from the second layer.
As for claim 7,
Park teaches the substrate of claim 6, wherein the liner (the second liner) includes a selected one or more of: a dielectric material, an epoxy material, or liquid mold material. (liner is TaN [0037).
As for claim 8,
Park teaches the substrate of claim 1, and teaches that that a side of the first volume of the first material in the first layer that extends from the first side of the first layer to the second side of the second layer is substantially perpendicular to the first side of the first layer. (shown in figure 4A, vertical sidewalls are the result of anisotropic etch [0033].)
As for claim 9,
Park teaches the substrate of claim 1 and teaches that the first layer includes portions of a circuit. (42 is a transistor [0042]).
As for claim 10,
Park teaches the substrate of claim 1, wherein the substrate is a portion of a selected one or more of: one or more bonded wafers, a wafer that includes one or more individual dies, a package substrate, or a packaged unit. (the device on is substrate that comprises transistor, which inherently require separation into individual dies to provide a useful device).
As for claim 11,
Park teaches in figure 4B a wafer comprising:
a first layer (43) with a first side and a second side opposite the first side;
a second layer (44) with a first side and a second side opposite the first side, wherein the second side of the second layer is on the first side of the first layer;
a third layer (46) with a first side and a second side opposite the first side, wherein the second side of the third layer is on the first side of the second layer;
and a cavity (48, on right side of figure) extending from the first side of the third layer to the second side of the first layer.
and a side of the cavity in the first layer is substantially perpendicular to the first side of the first layer. (shown in figure 4A, vertical sidewalls are the result of anisotropic etch [0033].)
As for claim 12,
Park teaches the wafer of claim 11, wherein a bottom of the cavity proximate to the second side of the first layer is not coplanar with the second side of the first layer. (offset by the height of the transistor 42).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Hua et al. (U.S. 2014/0131876).
As for claim 13,
Park teaches the wafer of claim 11, but does not teach a comprising a volume of epoxy in the cavity, the volume of epoxy extending from the second side of the first layer to the first side of the first layer.
However, Park uses an adhesive barrier layer of TaN to line the via before filling to protect the ILD from metal contamination and pealing (Park [0033]), and Hua suggest that an epoxy can be used for the same reason (Hua [0020]).
Using epoxy as a substitute adhesive barrier was known, the technical ability existed to substitute epoxy for TaN, and the result of the substitution was predictable. It would have been obvious to one of ordinary skill in the art at the time of the invention to substitute epoxy for a dielectric adhesive, because polymers improve moisture resistance in the barrier to protect the metal from corrosion.
As for claim 14,
Park in view of Hua make obvious the wafer of claim 13, and in the combination, Park teaches a dielectric on the volume of epoxy. (Park uses a second liner over the first liner before forming the upper metal in figure 4d. [0037].)
As for claim 15,
Park in view of Hua makes obvious the wafer of claim 14, and in the combination, the dielectric completely overlaps the volume of epoxy. ([0037]).
Conclusion
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/JOHN A BODNAR/Primary Examiner, Art Unit 2893