DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 - 16 are rejected under 35 U.S.C. 103 as being unpatentable over Ching et al. [US 2019/0067445 A1], “Ching” in view of Wu et al. [US 2019/0043857 A1], “Wu.”
Regarding claim 10, Ching discloses a semiconductor structure (Fig. 1E(annotated below), 100, Fig. 2A – 16: (for clarification, please refer to the annotated figure below)), comprising:
a gate structure (Fig. 1E, 118) formed over a substrate (102);
a first source/drain (S/D) structure (114a) formed adjacent to the gate structure (as shown);
a second S/D structure (114b) adjacent to the first S/D structure (as shown); and
a dielectric wall (108 and 112) between the first S/D structure (114a) and the second S/D structure (114b), wherein the first S/D structure extends above a top surface of the dielectric wall (as shown the top of the first S/D structure extends above and beyond the top surface of the dielectric wall. The Examiner notes that the limitation does not require the first S/D structure to be directly over the dielectric wall).
Ching does not disclose the top surface of the dielectric wall is concave.
Wu discloses a FinFET structure with isolation structures (Fig. 1H: 114a, 114b, 114c, 114d and 114e) has a concave top surface in order to support the fin structure during the etching process (¶0065]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to change the shape of the dielectric wall as taught in Wu in the device of Ching such that the top surface of the dielectric wall is concave because creating the concave in the top surface of the dielectric wall will help prevent the fins from bending (¶[0065] of Wu).
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Regarding claim 11, Ching as modified discloses claim 10, Ching further discloses a spacer layer (Fig. 1E, 112) formed adjacent to the first S/D structure (114a), wherein a height (H2) of the dielectric wall (108) is greater than a height (H1) of the spacer layer (112) (as shown) (see ¶[0033]).
Regarding claim 12, Ching as modified discloses claim 10, Ching further discloses a first stack structure (Fig. 1E, 114a) and a second stack structure (114b) formed over the substrate (102), wherein the dielectric wall (108 and 112 – specifically 112) is between and in direct contact with the first stack structure and the second stack structure (as shown in Fig. 1E).
Regarding claim 13, Ching as modified discloses claim 12, Ching further disclose the dielectric wall (108 and 112) comprises a core dielectric layer (108) and a liner dielectric layer (112), and the liner dielectric layer (112+106) below the core dielectric layer (108) (as shown) is in direct contact with the first stack structure and the second stack structure (as shown in Fig. 1E).
Regarding claim 14, Ching as modified discloses claim 13, Ching further disclose the gate structure (Fig. 1E, 118) comprises a gate dielectric layer, and the gate dielectric layer is in direct contact with the liner dielectric layer of the dielectric wall (as shown in figure 1E, the layer 112 also works as the gate dielectric layer).
Regarding claim 15, Ching as modified discloses claim 10, Ching further discloses an S/D contact structure (Fig. 1E, 120) formed over the first S/D structure (114a), wherein a bottom surface of the S/D contact structure is higher (as shown) than the top surface of the dielectric wall (108).
Regarding claim 16, Ching as modified discloses claim 10, Ching further discloses an etching stop layer (Fig. 1E, 115) formed over the first S/D structure (114a), wherein a portion of the etching stop layer (115) is in direct contact with the first portion (top portion) of the dielectric wall (108).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21-24 are rejected under 35 U.S.C. 102(b)(1) as being anticipated by Ju et al. [US 2021/0343713 A1], “Ju”.
Regarding claim 21, Ju discloses a semiconductor structure (Fig. 27A, 200), comprising:
a first source/drain (S/D) structure (310A);
a second S/D structure (310B);
a dielectric wall (264 and 266) between (as shown) a first portion of a sidewall of the first S/D structure (left sidewall of 310A) and a first portion of a sidewall of the second S/D structure right sidewall of 310B), wherein:
the dielectric wall comprises a liner dielectric layer (264) and a core dielectric layer (266), and
a bottommost surface of the core dielectric layer (266) is above a topmost surface of the liner dielectric layer (264); and
an etch stop layer (322) between (as show) a second portion of the sidewall of the first S/D structure (310A) and a second portion of the sidewall of the second S/D structure (310B).
Regarding claim 22, Ju discloses claim 21, Ju discloses the etch stop layer (Fig. 27A, 322) contacts a top surface of the dielectric wall (266) (as shown).
Regarding claim 23, Ju discloses claim 21, Ju discloses an interlayer dielectric (Fig. 27A, 320) disposed between (as shown) the second portion of the sidewall of the first S/D structure and the second portion of the sidewall of the second S/D structure and separated (as shown) from the second portion of the sidewall of the first S/D structure and the second portion of the sidewall of the second S/D structure by the etch stop layer (322).
Regarding claim 24, Ju discloses claim 21, Ju discloses a spacer (Fig. 27A, 262), wherein the first S/D structure (310A) is between the spacer (262) and the dielectric wall (266/264).
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection required by Applicant’s amendment.
Allowable Subject Matter
Claims 1-9 are allowed.
Regarding claim 1, none of the prior art teaches or suggests, alone or in combination, all of the structural features of the claims, specifically including but not limited to, “the dielectric wall has a first portion directly below the S/D contact structure and a second portion directly below the gate structure, a bottommost surface of the first S/D structure is below a bottommost surface of the dielectric wall, the first portion has a first height along a vertical direction, the second portion has a second height along the vertical direction, and the first height is smaller than the second height,” as required by the claim.
Claims 2-9 are allowed by virtues of their dependency on claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Pranatharthi et al. [US 2021/0305361 A1] discloses a device structure with gate stacks is formed over channel regions of a first nanosheet stack (102 – right side) and second nanosheet stack (102- left side) adjacent to the first nanosheet stack. An isolation pillar (602) is positioned between the first gate stack and the second gate stack.
Chiang et al. [US 2021/0057525 A1] discloses a device structure with gate stacks and hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins.
Ju et al. [US 2023/0260998 A1] teaches a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A dielectric gate isolation fin separates the first metal gate from the second metal gate. Ju et al. does not teach bottommost surface of the first S/D structure is below a bottommost surface of the dielectric wall.
Ko et al. [US 2020/0006557 A1] discloses a semiconductor structure, comprising: a gate structure formed over a substrate; a first source/drain (S/D) structure formed adjacent to the gate structure; an S/D contact structure formed over the first S/D structure; and a dielectric wall formed below the gate structure and the S/D contact structure and the dielectric wall has a first portion directly below the S/D contact structure and a second portion directly below the gate structure, a bottommost surface of the first S/D structure is below a bottommost surface of the dielectric wall. Ko does not teach the first portion has a first height along a vertical direction, the second portion has a second height along the vertical direction, and the first height is smaller than the second height.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRIYA M RAMPERSAUD whose telephone number is (571)272-3464. The examiner can normally be reached Mon-Wed 9am-6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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PRIYA M. RAMPERSAUD
Examiner
Art Unit 2897
/P.M.R/Examiner, Art Unit 2897
/MARK W TORNOW/Primary Examiner, Art Unit 2891