DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/01/2025 has been entered.
Status of Application
In response to Office action mailed 09/30/2025, Applicants amended claims 1, 10,13-16 and 19-20 in the response filed 12/01/2025
Claim(s) 1-7, 9-17 and 19-20 are pending examination.
Response to Arguments
Applicant’s arguments, 12/01/2025 Remarks, with respect to the objection of claim 20 has been fully considered and is persuasive. The objection of claim 20 has been withdrawn in view of the amendment to claim 20.
Applicant’s arguments, see 12/01/2025 Remarks, with respect to the rejection of claim 11 under 35 U.S.C. § 112 has been fully considered and is persuasive. The rejection of claim 11 under 35 U.S.C. § 112 has been withdrawn.
Applicant’s arguments with respect to claim(s) 1-7, 9-17 and 19-20 have been considered but are moot because the arguments do not apply to the new combination of references being used in the current rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 4-5 and 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (PG Pub 2019/0273065; hereinafter Yu), Yu et al. (PG Pub 2019/0035757; hereinafter Yu-2) and Lin et al. (PG Pub 2021/0111153; hereinafter Lin).
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Regarding claim 1, refer to the Examiner’s mark-up of Fig. 3 provided above, Yu teaches an electronic device 100 (para [0018-0079]) comprising:
a system on chip (SoC) (annotated “SoC” in Fig. 3 above); and
a memory device 110 on the SoC;
wherein the SoC comprises an SoC package substrate 150;
a first die 130 on the SoC package substrate, and having a logic circuit thereon (annotated circuit” in Fig. 3 above); and
a second die 120 on the first die, and having a logic circuit thereon 131 (see Fig. 3 above).
Yu does not explicitly teach an interconnection via, wherein the interconnection via vertically extends in a direction from a contact location with the first die within the SoC to an external surface of the SoC facing the memory device, the contact location being outside an outermost perimeter of the second die.
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In the same field of endeavor, refer to the Examiner’s mark-up of Fig. 12 provided above, Lin teaches a multi-chip package 2000 comprising: an SoC 600 comprises an SoC package substrate 610;
a first die 620 on the SoC package substrate (see Fig. 12); a second die 650 on the first die (see Fig. 12); and an interconnection via 622; wherein the interconnection via vertically extends in a direction (vertically) from a contact location with the first die (620-top surface) within the SoC to an external surface of the SoC (600-top surface) facing a second package (annotated “pkg-2” in Fig. 12 above), the contact location being outside an outermost perimeter of a second die (see Fig. 12).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the interconnection via(s), as taught by Lin, into the electronic device of Yu, to provide means for electrically connecting the first die with the second die and the second package (aka the memory device of Yu). In addition, to adding mechanical support to the package.
Yu does not explicitly teach a printed circuit board; and a system on chip (SoC) on the printed circuit board.
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In the same field of endeavor, refer to the Examiner’s mark-up of Fig. 8-provided above, Yu-2 teaches a semiconductor package 800 (para [0015-0063]) comprising: a printed circuit board 880 (para [0057]); and a system on chip (SoC) (annotated “SoC” in Fig. 8 above) on the printed circuit board (see Fig. 8 above).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the SoC package of Yu on a printed circuit board, as taught by Yu-2, to mechanically support and electrically connect the package to various components.
Regarding claim 4, refer to the figures provided above, in the combination of Yu, Lin and Yu-2, Yu teaches a size of the first die 130 is greater than a size of the second die 120 (see Fig. 3).
Regarding claim 5, refer to the figures provided above, in the combination of Yu, Lin and Yu-2, Yu teaches a size of the second die 120 is less than a size of the first die 130 (see Fig. 3). Yu does not teach the size of the second die is greater than a size of the first die However, one of ordinary skill in the art would have found it obvious to change the size of the second die (ex. to be smaller than, larger than or equal to) that of the first die to be a mere routine expedient yielding the same intended results. According, to MPEP § 2144(IV), where the facts in a prior legal decision are sufficiently similar to those in an application under examination, the examiner may use the rationale used by the court. Examples directed to various common practices which the court has held normally require only ordinary skill in the art and hence are considered routine expedients are discussed below.” See In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.). See Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree “will not sustain a patent’); and /n re Williams, 36 F.2d 436, 438 (CCPA 1929) (‘It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.”).
Regarding claim 10, refer to the figures provided above, Yu, Lin and Yu-2 teach the SoC (“SoC”) comprises a memory controller (140-Yu = 620-right of Lin) configured to transmit a data input/output signal to the memory device, and receive the data input/output signal from the memory device, and a signal path electrically connecting the memory controller to the memory device (refer to circuitry within 150) and configured to transmit the data input/output signal, the signal path comprising an interconnection via 622-Lin vertically extending in a direction from the first die to the memory device (see cited figures).
The recited “configured to transmit a data input/output signal to the memory device, and receive the data input/output signal from the memory device” and “configured to transmit the data input/output signal, the signal path comprising an interconnection via vertically extending in a direction from the first die to the memory device” (i.e., function) does not structurally distinguish an apparatus claim from the prior art apparatus see In re Danly, 263 F.2d 844, 838 (CCPA 1959) (apparatus claims must distinguish in terms of structure rather than function). The only structural limitation that appears to be required for the prior art apparatus to be capable of performing the aforementioned function is having a memory controller electrically connected to the interconnection via of the SoC, which Yu clearly shows or in other words, the prior art appears to inherently possess the capability of performing the recited functions. "[T]he discovery of a previously unappreciated property of a prior art composition, or of a scientific explanation for the prior art’s functioning, does not render the old composition patentably new to the discoverer." Atlas Powder Co. v. IRECO Inc., 190 F.3d 1342, 1347, 51 USPQ2d 1943, 1947 (Fed. Cir. 1999). Thus, the claiming of a new use, new function or unknown property which is inherently present in the prior art does not necessarily make the claim patentable. In re Best, 562 F.2d 1252, 1254, 195 USPQ 430, 433 (CCPA 1977). See In re Swinehart, 439 F.2d 210 (CCPA 1971) to emphasize that “where the Patent [and Trademark] Office has reason to believe that a functional limitation asserted to be critical for establishing novelty in the claimed subject matter may, in fact be an inherent characteristic of the prior art, it possesses the authority to require the applicant to prove that the subject matter shown to be in the prior art does not possess the characteristic relied on.").
Regarding claim 11, refer to the figures provided above, in the combination of Yu, Lin and Yu-2, Yu teaches the SoC (“SoC”) comprises a memory controller 140 configured to transmit a data input/output signal to the memory device, and receive the data input/output signal from the memory device 110 (see Fig. 3), and a signal path (circuitry electrically connecting the memory controller to the memory device and configured to transmit the data input/output signal, the signal path comprising the interconnection via 101 (see Fig. 3).
The recited “configured to transmit a data input/output signal to the memory device, and receive the data input/output signal from the memory device” and “and configured to transmit the data input/output signal, the signal path comprising the interconnection via” (i.e., function) does not structurally distinguish an apparatus claim from the prior art apparatus see In re Danly, 263 F.2d 844, 838 (CCPA 1959) (apparatus claims must distinguish in terms of structure rather than function). The only structural limitation that appears to be required for the prior art apparatus to be capable of performing the aforementioned function is having a an interconnection via connecting the memory controller to the memory device, which Yu clearly shows or in other words, the prior art appears to inherently possess the capability of performing the recited functions. "[T]he discovery of a previously unappreciated property of a prior art composition, or of a scientific explanation for the prior art’s functioning, does not render the old composition patentably new to the discoverer." Atlas Powder Co. v. IRECO Inc., 190 F.3d 1342, 1347, 51 USPQ2d 1943, 1947 (Fed. Cir. 1999). Thus, the claiming of a new use, new function or unknown property which is inherently present in the prior art does not necessarily make the claim patentable. In re Best, 562 F.2d 1252, 1254, 195 USPQ 430, 433 (CCPA 1977). See In re Swinehart, 439 F.2d 210 (CCPA 1971) to emphasize that “where the Patent [and Trademark] Office has reason to believe that a functional limitation asserted to be critical for establishing novelty in the claimed subject matter may, in fact be an inherent characteristic of the prior art, it possesses the authority to require the applicant to prove that the subject matter shown to be in the prior art does not possess the characteristic relied on.").
Regarding claim 12, refer to the figures provided above, in the combination of Yu, Lin and Yu-2, Yu-2 teaches an interposer substrate (RDL1 and RDL2; para [0055]) between the SoC and the memory device, and electrically connecting the SoC to the memory device (see Fig. 8).
Regarding claim 13, refer to the Examiner’s mark-up of Fig. 3 provided above, Yu teaches an electronic device 100 (para [0018-0079]) comprising:
a system on chip (SoC) (annotated “SoC” in Fig. 3 above) on a SoC package substrate 150 and comprising at least two logic die 130,140; the two logic die having a logic circuit thereon (see Fig. 3).
Yu does not explicitly teach “a printed circuit board; and a system on chip (SoC) on the printed circuit board.”
In the same field of endeavor, refer to the Examiner’s mark-up of Fig. 8-provided above, Yu-2 teaches a semiconductor package 800 (para [0015-0063]) comprising: a printed circuit board 880 (para [0057]); and a system on chip (SoC) (annotated “SoC” in Fig. 8 above) on the printed circuit board (see Fig. 8 above).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the SoC package of Yu on a printed circuit board, as taught by Yu-2, to mechanically support and electrically connect the package to various components.
Yu does not explicitly teach an interconnection via vertically extending in a direction from a contact location with one of the at least two logic die to the memory device within the SoC to an external surface of the SoC facing the memory device, the contact location being outside an outermost perimeter of another one of the at least two logic die.
In the same field of endeavor, refer to the Examiner’s mark-up of Fig. 12 provided above, Lin teaches a multi-chip package 2000 comprising: an SoC 600; wherein the SoC comprises an SoC package substrate 610; an interconnection via 622 vertically extending in a direction from a contact location with one of the at least two logic die (620-top surface) to a memory device (pkg-2) within the SoC to an external surface of the SoC facing the memory device (see Fig. 12), the contact location being outside an outermost perimeter of another one of the at least two logic die (beside 650) (see Fig. 12).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the interconnection via(s), as taught by Lin, into the electronic device of Yu, to provide means for electrically connecting the first die with the second die and the second package (aka the memory device of Yu). In addition, to adding mechanical support to the package.
Claim(s) 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Yu, Lin and Yu-2, as applied to claim 1 above, and further in view of Yu et al. (PG Pub 2019/0035767; hereinafter Yu-3).
Regarding claim 2, refer to the figures provided above, in the combination of Yu, Lin and Yu-2, Yu teaches the first die 130 and the second die 120, he does not explicitly teach the first die “comprises a first substrate, and a first active layer on the first substrate and having a semiconductor element thereon, the second die comprises a second substrate, and a second active layer on the second substrate and having a semiconductor element thereon, the first active layer faces the SoC package substrate, and the second active layer faces the first die.”
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In the same field of endeavor, refer to Fig. 2-provided above, Yu-3 teaches a semiconductor package (para [0011-0063]) comprising: a first die 200 (para 0021]) comprises a first substrate 202 (para [0021]), and a first active layer 206 (para [0022]) on the first substrate and having a semiconductor element thereon (para [0021]), a second die 100 (para [0014]) comprises a second substrate 102 (para [0015]), and a second active layer 104 (para [0016]) on the second substrate and having a semiconductor element thereon (para [0015)).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first and second active layer, of the respective first and second die, face each other, as taught by Yu-3, to lower the bonding temperature (para 0011).
Regarding claim 3, refer to the figures provided above, in the combination of Yu, Lin and Yu-2, Yu teaches the first die 130 faces the SoC package substrate (SoC) (see Fig. 3). Yu does not explicitly teach the first die “comprises a first substrate, and a first active layer on the first substrate and having a semiconductor element thereon, the second die comprises a second substrate, and a second active layer on the second substrate and having a semiconductor element thereon, the first active layer faces the SoC package substrate, and the second active layer faces the first die.”
In the same field of endeavor, refer to Fig. 2-provided above, Yu-3 teaches a semiconductor package (para [0011-0063]) comprising: a first die 200 (para 0021]) comprises a first substrate 202 (para [0021]), and a first active layer 206 (para [0022]) on the first substrate and having a semiconductor element thereon (para [0021]), a second die 100 (para [0014]) comprises a second substrate 102 (para [0015]), and a second active layer 104 (para [0016]) on the second substrate and having a semiconductor element thereon (para [0015]); wherein the first active layer faces the SoC package substrate, and the second active layer faces the first die (see Fig. 2).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first and second active layer, of the respective first and second die, face each other, as taught by Yu-3, to lower the bonding temperature (para 0011).
3. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Yu, Lin and Yu-2, as applied to claim 1 above, and further in view of Bruno et al. (PG Pub 2016/0218094; hereinafter Bruno).
Regarding claim 6, refer to the Examiner’s mark-up of Fig. 3 provided above, Yu does not teach a voltage regulator, wherein the voltage regulator is configured to receive an input voltage and generate an output voltage to be used by the SoC, wherein the voltage regulator is mounted on the SoC package substrate.
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In the same field of endeavor, refer to Fig. 4-provided above, Bruno teaches a package with SoC and integrated memory (para [0016-0033]) comprising: a component 114 (para [0021]; voltage regulator, inductors, capacitors, resistors, or other components); wherein the voltage regulator is configured to receive an input voltage and generate an output voltage to be used by an SoC (para [0021-0023]), wherein the voltage regulator is mounted on an SoC package substrate 104 (para [0021]).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the component of Bruno on the bottom side of the SoC package of Yu to aid in voltage regulation to the package (para [0021)).
4. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yu, Lin, Yu-2 and Bruno, as applied to claim 6 above, and further in view of Jain et al. (PG Pub 2019/0304915; hereinafter Jain).
Regarding claim 7, refer to the figures provided above, in the combination of Yu, Lin, Yu-2 and Bruno, Bruno teaches the voltage regulator 114 is in parallel with the first die 318, he does not explicitly teach on a same flat surface.
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In the same field of endeavor, refer to Fig. 1-provided above, Jain teaches a semiconductor package (para [0024-0084]) comprising: a voltage regulator 114-3 (para [0036)) is in parallel with s first die 114-1 (para [0036]) on a same flat surface (surface of SoC substrate 170-2) (para [0036)).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a voltage regulator on the same flat surface, as taught by Jain, to provide a more robust power delivery package.
5. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Yu, Lin and Yu-2, as applied to claim 1, and further in view of Parto (US Patent No. 10,504,848).
Regarding claim 9, refer to the figures provided above, in the combination of Yu, Lin and Yu-2, Yu teaches the SoC (SoC”) and the first 130 and second die 120; he does not explicitly teach a voltage regulator configured to receive an input voltage and generate an output voltage to be used by the SoC, wherein the voltage regulator is embedded in one of the first die and the second die.
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In the same field of endeavor, refer to Fig. 1a-provided above, Parto teaches chip embedded integrated voltage regulator (col. 5, line 45 through col. 9, line 21) comprising: a voltage regulator (CEIVR) configured to receive an input voltage and generate an output voltage to be used by an SoC (akaa package; col. 1, lines 35-67), wherein the voltage regulator is embedded in one of the first die and the second die (see Fig. 1a).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a voltage regulator into one of the first or second dies, as taught by Parto, to provide a regulated power to a multitude of dies.
6. Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Yu, Yu-2 and Lin, in view of claim 13 above, and further in view of Parto (US Patent No. 10,504,848).
Regarding claim 19, refer to the figures provided above, in the combination of Yu, Yu-2 and Lin, Yu teaches the SoC (SoC") and the first 130 and second die 120; he does not explicitly teach a voltage regulator configured to receive an input voltage and generate an output voltage to be used by the SoC, wherein the voltage regulator is embedded in one of the first die and the second die.
In the same field of endeavor, refer to Fig. 1a-provided above, Parto teaches chip embedded integrated voltage regulator (col. 5, line 45 through col. 9, line 21) comprising: a voltage regulator (CEIVR) configured to receive an input voltage and generate an output voltage to be used by an SoC (aka package; col. 1, lines 35-67), wherein the voltage regulator is embedded in one of the first die and the second die (see Fig. 1a).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a voltage regulator into one of the first or second dies, as taught by Parto, to provide a regulated power to a multitude of dies.
7. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (PG Pub 2019/0273065; hereinafter Yu), Lin et al. (PG Pub 2021/0111153; hereinafter Lin) and Parto (US Patent No. 10,504,848).
Regarding claim 20, refer to the Examiner’s mark-up of Fig. 3 provided above, Yu teaches a system on chip (SoC) having a three-dimensional (3D) chiplet structure (see claim limitations below) the SoC comprising:
an SoC package substrate 150;
a first die 130 on the SoC package substrate using a first bump (annotated “bump” in Fig. 3 above), and having a first logic circuit thereon (annotated “logic circuit” in Fig. 3 above);
a second die 120 on the first die, and having a second logic circuit thereon 131;
Yu does not explicitly teach “the first logic circuit and the second logic circuit receive an output voltage via an output voltage path, from a voltage regulator on the SoC package substrate.”
In the same field of endeavor, refer to Fig. 1a-provided above, Parto teaches chip embedded integrated voltage regulator (col. 5, line 45 through col. 9, line 21) comprising: a first logic circuit (CPU; col. 6, line 40); a second logic circuit (HBM1; col. 6, line 41); wherein the first logic circuit and the second logic circuit receive an output voltage via an output voltage path, from a voltage regulator on the SoC package substrate (col. 1, line 35-61).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a voltage regulator, as taught by Parto, to enable communication between multiple devices.
Yu does not explicitly teach an interconnection via; wherein the interconnection via vertically extends in a direction from a contact location with the first die within the SoC to an external surface of the SoC opposite the SoC package substrate facing a second package, the contact location being outside an outermost perimeter of the second die.
In the same field of endeavor, refer to the Examiner’s mark-up of Fig. 12 provided above, Lin teaches a multi-chip package 2000 comprising: an SoC 600 comprises an SoC package substrate 610;
a first die 620 on the SoC package substrate (see Fig. 12); a second die 120 on the first die (see Fig. 12); and an interconnection via 622; wherein the interconnection via vertically extends in a direction (vertically) from a contact location with the first die 620-top surface) within the SoC to an external surface of the SoC (600-top surface) opposite the SoC package substrate (see Fig. 12) facing a second package, the contact location being outside an outermost perimeter of the second die (see Fig. 12).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the interconnection via(s), as taught by Lin, into the electronic device of Yu, to provide means for electrically connecting the first die with the second die and the second package (aka the memory device of Yu). In addition, to adding mechanical support to the package.
Allowable Subject Matter
Claims 14-15 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 14 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 14, the at least one logic die comprises a plurality of vertically stacked logic dies, and the interconnection via is vertically extending in a direction from a first die, which is lowermost of the plurality of vertically stacked logic dies, to the memory device.
Claim 15 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 15, the at least one logic die comprises a plurality of vertically stacked logic dies, and the interconnection via is vertically extending in a direction from a second die, which is uppermost of the plurality of vertically stacked logic dies, to the memory device.
Claim 17 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 17, an interposer substrate between the SoC and the memory device, and electrically connecting the SoC to the memory device, wherein the interconnection via comprises a through silicon via penetrating the interposer substrate
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christina A Sylvia whose telephone number is (571)272-7474. The examiner can normally be reached on 8am-4pm (M-F).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on (571) 272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTINA A SYLVIA/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817