DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed 04 August 2025 fails to comply with 37 CFR 1.98(a)(3)(i) because it does not include a concise explanation of the relevance, as it is presently understood by the individual designated in 37 CFR 1.56(c) most knowledgeable about the content of the information, of each reference listed that is not in the English language. It has been placed in the application file, but the information referred to therein has not been considered.
Drawings
The drawings are objected to because:
The drawings contain deficient line quality. All drawings must be made by a process which will give them satisfactory reproduction characteristics. Every line must be durable, clean, black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. Refer to 37 CFR 1.84(l). See Figure(s) 1-7.
The sheets of drawings should be numbered in consecutive Arabic numerals, starting with 1. The drawing sheet numbering must be clear and larger than the numbers used as reference characters to avoid confusion. The number of each sheet should be shown by two Arabic numerals placed on either side of an oblique line, with the first being the sheet number and the second being the total number of sheets of drawings, with no other marking. See Page(s) 1-17.
The view numbering format is improper because non-partial independent views are inexplicably designated alphanumerically instead of being consecutively numbered using Arabic numerals, leading to a confusing numbering scheme. Only partial views intended to form one complete view, on one or several sheets, must be identified by the same number followed by a capital letter. The different views must otherwise be numbered in consecutive Arabic numerals, starting with 1, independent of the numbering of the sheets and, if possible, in the order in which they appear on the drawing sheet(s). Refer to 37 CFR 1.84(u). See Figure(s) 2a-c, 3a-b, 4a-b, 6a-c, 7a-j.
The drawings comprise at least one figure comprising two or more independent figures requiring individual designation as separate features and therefore the drawings require a numbering change to the figures. Otherwise, if the multiple figures designated as one should be properly identified as an exploded view using brackets as already objected to supra. For numbering figures, the different views must be numbered in consecutive Arabic numerals, starting with 1, independent of the numbering of the sheets and, if possible, in the order in which they appear on the drawing sheet(s). Refer to 37 CFR 1.84(u). See Figure(s) 7a-j.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Long Channel Back-Side Power Rail Multi-Bridge Channel FET.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Huang et al. (U.S. 2021/0335690).
Regarding Claim 1, Huang et al., Figure 28, discloses a semiconductor device, comprising:
a buried interconnection line extending in a first direction (buried interconnection line 120/122);
a gate electrode extending in a second direction intersecting the buried interconnection line, the gate electrode on the buried interconnection line (gate electrode 102);
channel layers spaced apart from each other in a third direction perpendicular to the first direction and the second direction, the channel layers on the buried interconnection line and surrounded by the gate electrode (channel layers 55),
the buried interconnection line including a metal layer and a semiconductor layer stacked in the third direction (metal layer 122, semiconductor layer 120);
a buried insulating layer between the channel layers and the buried interconnection line (buried insulating layer 110);
a first source/drain region and a second source/drain region, the first and second source/drain regions in contact with the channel layers on both sides of the gate electrode and the second source/drain region penetrating through the buried insulating layer and in contact with the semiconductor layer of the buried interconnection line (source/drain region 90);
a contact plug on the first source/drain region, and connected to the first source/drain region (contact plug 104); and
a via below the buried interconnection line, and connected to the buried interconnection line (via 124).
Regarding Claim 2, Huang et al., Figure 28,, further disclose the semiconductor device of claim 1, wherein, in the buried interconnection line, each of the metal layer and the semiconductor layer has a line shape extending in the first direction (buried interconnection line 122/120).
Regarding Claim 3, Huang et al., Figure 28, further disclose the semiconductor device of claim 1, wherein a level of a lower end of the second source/drain region is lower than a level of a lower end of the first source/drain region (source/drain region 90).
Regarding Claim 4, Huang et al., Figure 28, further disclose the semiconductor device of claim1, wherein the first source/drain region is spaced apart from the buried interconnection line (source/drain region 90).
Regarding Claim 5, Huang et al., Figure 28, further disclose the semiconductor device of claim 1, wherein the metal layer of the buried interconnection line comprises a first metal layer, and a second metal layer between the first metal layer and the semiconductor layer (buried interconnection line 122/120, [0072]).
Regarding Claim 6, Huang et al., Figure 28, further disclose the semiconductor device of claim 5, wherein the first metal layer has a first width in the second direction, and the second metal layer has a second width narrower than the first width in the second direction (buried interconnection line 122/120, [0072]).
Regarding Claim 7, Huang et al., Figure 28, further disclose the semiconductor device of claim 5, wherein side surfaces of the second metal layer in the second direction are coplanar with side surfaces of the semiconductor layer in the second direction (buried interconnection line 122/120, [0072]).
Regarding Claim 8, Huang et al., Figure 28, further disclose the semiconductor device of claim 1, wherein, in the second direction, the buried interconnection line has a first width, and the channel layers have a second width equal to or narrower than the first width (buried interconnection line 122/120, [0072]).
Regarding Claim 9, Huang et al., Figure 28, further disclose the semiconductor device of claim 1, wherein the buried interconnection line has inclined side surfaces and the buried interconnection line decreases in width toward the first and second source/drain regions (buried interconnection line 122/120, [0072]).
Regarding Claim 10, Huang et al., Figure 28, further disclose the semiconductor device of claim 1, further comprising:
an active layer on the buried insulating layer, overlapping the buried interconnection line and extending in the first direction (buried interconnection line 122/120, [0072]).
Regarding Claim 11, Huang et al., Figure 28, further disclose the semiconductor device of claim 10, wherein a lower surface of the first source/drain region is in contact with the active layer (source/drain region 90).
Regarding Claim 12, Huang et al., Figure 28, further disclose the semiconductor device of claim 1, further comprising: a device isolation layer covering at least a portion of side surfaces of the buried interconnection line (buried interconnection line 122/120, [0072]).
Regarding Claim 13, Huang et al., Figure 28, further disclose the semiconductor device of claim 1, wherein the contact plug is above the buried interconnection line, and each of the contact plug and the via have inclined side surfaces, and
each of the contact plug and the via decrease in width toward the buried interconnection line (buried interconnection line 122/120, [0072]).
Claim(s) 14-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Huang et al. (U.S. 2021/0335690).
Regarding Claim 14, Huang et al., Figure 28, discloses a semiconductor device, comprising:
a buried interconnection line extending in a first direction (buried interconnection line 122/120, [0072]);
a buried insulating layer on the buried interconnection line (buried insulating layer 110);
an active structure on the buried insulating layer (active structure 32/54/58/26);
a gate electrode extending in a second direction intersecting the active structure, the gate electrode on the buried insulating layer (gate electrode 98); and
a first source/drain region and a second source/drain region, the first and second source/drain regions on both sides of the gate electrode in regions where the active structure is recessed (source/drain region 90),
the buried interconnection line including a semiconductor layer extending in the first direction and in contact with the second source/drain region (buried interconnection line 122/120, [0072]).
Regarding Claim 15, Huang et al., Figure 28, further disclose the semiconductor device of claim 14, wherein the first source/drain region has a depth different from a depth of the second source/drain region (source/drain region 90).
Regarding Claim 16, Huang et al., Figure 28, further disclose the semiconductor device of claim 14, wherein the second source/drain region penetrates through the buried insulating layer and is connected to the semiconductor layer of the buried interconnection line (source/drain region 90).
Regarding Claim 17, Huang et al., Figure 28, further disclose the semiconductor device of claim 14, wherein the semiconductor layer of the buried interconnection line has a single crystal structure (buried interconnection line 122/120, [0072]).
Regarding Claim 18, Huang et al., Figure 28, further disclose the semiconductor device of claim 14, wherein the buried interconnection line further comprises a metal layer in contact with the semiconductor layer and extending in the first direction (buried interconnection line 122/120, [0072]).
Claim(s) 19 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Huang et al. (U.S. 2021/0335690).
Regarding Claim 19, Huang et al., Figure 28, discloses a semiconductor device, comprising:
a buried interconnection line extending in a first direction (buried interconnection line 122/120, [0072]);
a buried insulating layer on the buried interconnection line (buried insulating layer);
a gate electrode extending in a second direction intersecting the first direction, the gate electrode on the buried insulating layer (98);
channel layers spaced apart from each other in a third direction perpendicular to the first direction and the second direction, the channel layers on the buried insulating layer and surrounded by the gate electrode (32/54/58/62); and
source/drain regions on both sides of the gate electrode, the buried interconnection line overlapping the channel layers in the third direction, and connected to a portion of the source/drain regions below the source/drain regions (source/drain region 90).
Regarding Claim 20, Huang et al., Figure 28, further disclose the semiconductor device of claim 19, wherein side surfaces of the channel layers in the second direction and side surfaces of the buried interconnection line in the second direction are on a straight line (buried interconnection line 122/120, [0072]).
Conclusion
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Abbigale Boyle whose telephone number is 571-270-7919. The Examiner can normally be reached from 11 A.M to 7 P.M., Monday through Friday.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Zandra Smith, can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Abbigale Boyle
Examiner, Art Unit 2899
/ABBIGALE A BOYLE/Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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