Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's request for reconsideration of the finality of the rejection of the last Office action during the interview conducted on 11/20/2025 is persuasive and, therefore, the finality of that action is withdrawn.
Applicant’s arguments, see section titled “Remarks,” filed 09/04/2025, with respect to the rejection(s) of claims 1-11 under 35 USC 102 and 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejection is made in view of Scarbrough et al. (US20220278051A1, hereinafter Scarbrough) and Hwang et al. (US20200144380A1, hereinafter Hwang).
Regarding amended claim 1. Scarbrough discloses a semiconductor device, comprising:
a memory stack of gate layers and insulating layers, the gate layers and the insulating layers being stacked alternatingly and forming stair steps in a staircase region (Fig. 1H tiers 142 comprise an alternating memory stack of conductive structures 140 and insulative structures 141);
a first landing structure disposed on a first gate layer of a first stair step of the stair steps in the staircase region (Fig. 1H composite pad structure 135 disposed on a first conductive structure 140 of a first stair step 110), the first landing structure comprising a first upper structure and a first isolation layer between the first upper structure and the first gate layer (Fig. 1H composite pad structure 135 comprises upper pad structure 126 and middle pad structure 134 disposed between first conductive structure 140 and upper pad structure 126. Par. 48 states that “portions of the dielectric liner material 116…form middle pad structures 134” and par. 34 states that “the dielectric liner material 116 is formed of and includes SiOx (e.g., SiO2)”); and
a first contact structure extending through the contact isolation layer and the first landing structure and being connected with the first gate layer of the first stair step (Fig. 1J rightmost contact structure 148 extends through composite pad structure 135 and insulating structure 141 to contact conductive structure 140).
wherein the first upper structure comprises a same conductive material as the first gate layer (Par. 37 teaches that “the second liner material 118 may be formed of…conductive material (e.g., a metal, an alloy, a conductive metal-containing material)” and par. 55 teaches that “[t]he conductive structures 140 may be formed of and include at least one conductive material, such as one or more of a metal, an alloy” and so they can both comprise the same conductive material of a metal. Examiner notes that second liner material 118 is formed into upper pad structure 126 as taught by par. 40 which states that “the second liner material 118 (FIG. 1C) may be doped…form a doped second liner material 120” and par. 45 which states that “portions 122 (FIG. 1D) of the doped second liner material 120…form upper pad structures 126”).
Scarbrough does not appear to teach
the first landing structure comprising a first isolation stack
the first upper structure being etch-selective to a contact isolation layer that covers the staircase region.
Hwang teaches
the first upper structure being etch-selective to a contact isolation layer that covers the staircase region (Par. 36 “The pad dielectric pattern 25 may include a dielectric material having an etch selectivity with respect to the etch stop pattern 35” and “the pad dielectric pattern 25 may include the same dielectric material as that of the dielectric layers ILD.” Therefore, etch stop pattern 35 has etch selectivity with respect to ILD 55 which covers the staircase region).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Scarbrough with the teachings of Hwang because the inclusion of a pad dielectric layer deposited over the stairstep structure as taught by Hwang that has etch selectivity with respect to the etch stop layer allows precise engineering and reduces the likelihood of damaging the memory device during production.
Therefore, the combination of Scarbrough and Hwang also teaches the limitation
the first landing structure comprising a first isolation stack (Scarbrough par. 34 states that “the dielectric liner material 116 is formed of and includes SiOx (e.g., SiO2)” and Hwang teaches the inclusion of a pad dielectric layer to improve etching precision. The combination of dielectric liner material 116 and the pad dielectric as taught by Hwang are a first isolation stack).
Similar arguments apply to amended independent claim 11 and will not be repeated for brevity, see below rejection for full claims mapping.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-7, and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Scarbrough (US20220278051A1) in view of Hwang (US20200144380A1).
Regarding claim 1. Scarbrough discloses a semiconductor device, comprising:
a memory stack of gate layers and insulating layers, the gate layers and the insulating layers being stacked alternatingly and forming stair steps in a staircase region (Fig. 1H tiers 142 comprise an alternating memory stack of conductive structures 140 and insulative structures 141);
a first landing structure disposed on a first gate layer of a first stair step of the stair steps in the staircase region (Fig. 1H composite pad structure 135 disposed on a first conductive structure 140 of a first stair step 110), the first landing structure comprising a first upper structure and a first isolation layer between the first upper structure and the first gate layer (Fig. 1H composite pad structure 135 comprises upper pad structure 126 and middle pad structure 134 disposed between first conductive structure 140 and upper pad structure 126. Par. 48 states that “portions of the dielectric liner material 116…form middle pad structures 134” and par. 34 states that “the dielectric liner material 116 is formed of and includes SiOx (e.g., SiO2)”); and
a first contact structure extending through the contact isolation layer and the first landing structure and being connected with the first gate layer of the first stair step (Fig. 1J rightmost contact structure 148 extends through composite pad structure 135 and insulating structure 141 to contact conductive structure 140).
wherein the first upper structure comprises a same conductive material as the first gate layer (Par. 37 teaches that “the second liner material 118 may be formed of…conductive material (e.g., a metal, an alloy, a conductive metal-containing material)” and par. 55 teaches that “[t]he conductive structures 140 may be formed of and include at least one conductive material, such as one or more of a metal, an alloy” and so they can both comprise the same conductive material of a metal. Examiner notes that second liner material 118 is formed into upper pad structure 126 as taught by par. 40 which states that “the second liner material 118 (FIG. 1C) may be doped…form a doped second liner material 120” and par. 45 which states that “portions 122 (FIG. 1D) of the doped second liner material 120…form upper pad structures 126”).
Scarbrough does not appear to teach
the first landing structure comprising a first isolation stack
the first upper structure being etch-selective to a contact isolation layer that covers the staircase region.
Hwang teaches
the first upper structure being etch-selective to a contact isolation layer that covers the staircase region (Par. 36 “The pad dielectric pattern 25 may include a dielectric material having an etch selectivity with respect to the etch stop pattern 35” and “the pad dielectric pattern 25 may include the same dielectric material as that of the dielectric layers ILD.” Therefore, etch stop pattern 35 has etch selectivity with respect to ILD 55 which covers the staircase region).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Scarbrough with the teachings of Hwang because the inclusion of a pad dielectric layer deposited over the stairstep structure as taught by Hwang that has etch selectivity with respect to the etch stop layer allows precise engineering and reduces the likelihood of damaging the memory device during production.
Therefore, the combination of Scarbrough and Hwang also teaches the limitation
the first landing structure comprising a first isolation stack (Scarbrough par. 34 states that “the dielectric liner material 116 is formed of and includes SiOx (e.g., SiO2)” and Hwang teaches the inclusion of a pad dielectric layer to improve etching precision. The combination of dielectric liner material 116 and the pad dielectric as taught by Hwang are a first isolation stack).
Regarding claim 3. The combination of Scarbrough and Hwang teaches the semiconductor device of claim 1 further comprising:
a second landing structure disposed on a second gate layer of a second stair step of the stair steps in the staircase region (See below annotated fig. 1J. Second landing structure 135 disposed on second conductive structure 140 of a second stair step), the second landing structure comprising a second upper structure of the conductive material and a second isolation stack between the second upper structure and the second gate layer (See below annotated fig. 1J second landing structure comprises upper pad structure 126 and middle pad structure 134. Similar to the above rejection of claim 1, Scarbrough’s dielectric liner material 116 and the pad dielectric comprise a second isolation stack); and
a second contact structure extending through the contact isolation layer and the second landing structure and being connected with the second gate layer of the second stair step (See below annotated fig. 1J second contact structure 148 extends through composite pad structure 135 and insulating structure 141 to contact conductive structure 140), the first upper structure and the second upper structure being isolated by the contact isolation layer (See below
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annotated fig. 1J first and second upper pad structures 126 isolated by lower pad structure 132).
Regarding claim 4. The combination of Scarbrough and Hwang teaches the semiconductor device of claim 3, wherein:
the first isolation stack and the second isolation stack share a stair step isolation layer that extends over the stair steps (See above rejection of claims 1 and 3. A first isolation stack comprises Scarbrough’s dielectric material 116 and pad dielectric as taught by Hwang and a second isolation stack comprises Scarbrough’s dielectric material 116 and pad dielectric as taught by Hwang that is disposed under the second landing structure, see above annotated fig. 1J).
Regarding claim 5. The combination of Scarbrough and Hwang teaches the semiconductor device of claim 4, wherein:
the stair step isolation layer covers the stair steps in a conformal manner (Hwang teaches the inclusion of a pad dielectgric layer to improve etch selectivity and in par. 145 they state that “[o]n the connection region CNR, the electrode structure ST may have a stepwise structure and the pad dielectric pattern 25 may conformally cover the stepwise structure of the electrode structure ST.” Therefore, the combination of Scarbrough and Hwang would also have the pad dielectric layer deposited in a conformal manner).
Regarding claim 6. The combination of Scarbrough and Hwang teaches the semiconductor device of claim 4, wherein:
the stair step isolation layer comprises a dielectric material that is etch-selective to silicon nitride (Hwang par. 36 “[t]he pad dielectric pattern 25 may include a dielectric material having an etch selectivity with respect to the etch stop pattern 35” and Hwang par. 38 says that “the etch stop pattern 35 may include a silicon nitride.” Therefore, the pad dielectric pattern 25 is comprises a dielectric that is etch-selective to silicon nitride. As Hwang teaches the pad dielectric, they also teach the specific materials which include materials etch-selective to silicon nitride).
Regarding claim 7. The combination of Scarbrough and Hwang teaches the semiconductor device of claim 4, wherein:
the first isolation stack further comprises one of the insulating layers that is stacked on the first gate layer (Scarbrough par. 34 states that “the dielectric liner material 116 is formed of and includes SiOx (e.g., SiO2)” and Hwang teaches the inclusion of a pad dielectric layer to improve etching precision. The combination of dielectric liner material 116 and the pad dielectric as taught by Hwang are a first isolation stack and can further comprise the insulative structure 141).
Regarding claim 10. The combination of Scarbrough and Hwang teaches the semiconductor device of claim 1, wherein:
the first upper structure comprises a first etch stop structure (Fig. 1J upper pad structure 126 is a part of composite pad structure 135 and par. 57 teaches that “[t]he composite pad structures 135 may serve as so-called “etch stop” structures to mitigate (e.g., prevent) undesirable damage”).
Regarding claim 11. Scarbrough teaches a memory system device, comprising:
a semiconductor memory device, comprising:
a memory stack of gate layers and insulating layers, the gate layers and the insulating layers being stacked alternatingly and forming stair steps in a staircase region (Fig. 1H tiers 142 comprise an alternating memory stack of conductive structures 140 and insulative structures 141);
a landing structure disposed on a first gate layer of a first stair step of the stair steps in the staircase region (Fig. 1H composite pad structure 135 disposed on a first conductive structure 140 of a first stair step 110), the landing structure comprising an etch stop structure and an isolation layer between the etch stop structure and the first gate layer (Fig. 1H composite pad structure 135 comprises upper pad structure 126 and middle pad structure 134 disposed between first conductive structure 140 and upper pad structure 126. Par. 48 states that “portions of the dielectric liner material 116…form middle pad structures 134” and par. 34 states that “the dielectric liner material 116 is formed of and includes SiOx (e.g., SiO2).” Par. 57 teaches that “[t]he composite pad structures 135 may serve as so-called “etch stop” structures to mitigate (e.g., prevent) undesirable damage”);
a contact structure extending through the contact isolation layer and the landing structure and being connected with the first gate layer of the first stair step (Fig. 1J rightmost contact structure 148 extends through composite pad structure 135 and insulating structure 141 to contact conductive structure 140); and
a channel structure extending through the memory stack of gate layers and insulating layers in an array region (Fig. 2 memory cells 220 extending through memory stack of gate layers and insulating layers); and
a control circuitry coupled with the semiconductor memory device to control data storage operations on the semiconductor memory device (Scarbrough par. 72 “[t]he base structure 236 may include at least one control logic region including control logic devices configured to control various operations of other features (e.g., the vertical strings 219 of memory cells 220) of the microelectronic device 200”),
wherein the etch stop structure comprises a same conductive material as the first gate layer (Par. 37 teaches that “the second liner material 118 may be formed of…conductive material (e.g., a metal, an alloy, a conductive metal-containing material)” and par. 55 teaches that “[t]he conductive structures 140 may be formed of and include at least one conductive material, such as one or more of a metal, an alloy” and so they can both comprise the same conductive material of a metal. Examiner notes that second liner material 118 is formed into upper pad structure 126 as taught by par. 40 which states that “the second liner material 118 (FIG. 1C) may be doped…form a doped second liner material 120” and par. 45 which states that “portions 122 (FIG. 1D) of the doped second liner material 120…form upper pad structures 126”).
The combination of Scarbrough and Hwang does not appear to teach
the landing structure comprising a isolation stack
the etch stop structure being etch-selective to a contact isolation layer that covers the staircase region.
Hwang teaches
the first upper structure being etch-selective to a contact isolation layer that covers the staircase region (Par. 36 “The pad dielectric pattern 25 may include a dielectric material having an etch selectivity with respect to the etch stop pattern 35” and “the pad dielectric pattern 25 may include the same dielectric material as that of the dielectric layers ILD.” Therefore, etch stop pattern 35 has etch selectivity with respect to ILD 55 which covers the staircase region).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Scarbrough with the teachings of Hwang because the inclusion of a pad dielectric layer deposited over the stairstep structure as taught by Hwang that has etch selectivity with respect to the etch stop layer allows precise engineering and reduces the likelihood of damaging the memory device during production.
Therefore, the combination of Scarbrough and Hwang also teaches the limitation
the first landing structure comprising a first isolation stack (Scarbrough par. 34 states that “the dielectric liner material 116 is formed of and includes SiOx (e.g., SiO2)” and Hwang teaches the inclusion of a pad dielectric layer to improve etching precision. The combination of dielectric liner material 116 and the pad dielectric as taught by Hwang are a first isolation stack).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Scarbrough (US20220278051A1) and Hwang (US20220278051A1) as applied to claim 1 above, and further in view of Kim et al. (US9865540B2, hereinafter Kim).
Regarding claim 8, the combination of Scarbrough and Hwang teaches the semiconductor device of claim 1.
The combination of Scarbrough and Hwang does not appear to teach wherein
the first upper structure includes a recessed sidewall profile.
Kim teaches an etch stop layer with a recessed sidewall profile (Fig. 40 etch stop layer 116 has thicker profile on top and thinner recessed portions on the sidewalls).
Being in analogous arts, it would have been obvious to further modify the combination of Scarbrough and Hwang with the teachings of Kim prior to the effective filing date because as both Scarbrough and Kim teach suitable etch stop layer structures for stopping an etch, it would have been obvious to substitute the conformally deposited dielectric pad layer as taught by Hwang with Kim’s recessed sidewall etch stop layer to achieve the predictable result of forming a dielectric pad layer with a recessed sidewall profile.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Scarbrough (US20220278051A1) and Hwang (US20220278051A1) as applied to claim 1 above, and further in view of Nam et al. (US20190013237A1, hereinafter Nam).
Regarding claim 9. The combination of Scarbrough and Hwang teaches the semiconductor device of claim 1.
The combination of Scarbrough and Hwang does not appear to teach wherein the first contact structure comprises:
a vertical portion; and
a horizontal portion protruding into the first upper structure,
wherein along a first direction parallel to the gate layers, the horizontal portion is longer than the vertical portion. and along a second direction perpendicular to the gate layers, the horizontal portion is spaced apart from and positioned between two opposing ends of the vertical portion.
Nam does teach wherein the first contact structure comprises:
a vertical portion (Fig. 1E contact plug PLG2 has a vertical portion directly below conductive pattern CP); and
a horizontal portion protruding into the first upper structure (Fig. 1E contact plug PLG2 has horizontal portions protruding into etch stop layer 30),
wherein along a first direction parallel to the gate layers, the horizontal portion is longer than the vertical portion (Fig. 1E horizontal portion of contact plug PLG2 is longer in a first direction parallel to etch stop layer 30), and along a second direction perpendicular to the gate layers, the horizontal portion is spaced apart from and positioned between two opposing ends of the vertical portion (Fig. 1E horizontal portion of plug PLG2 is spaced apart from and positioned between two opposing ends of the vertical portion extending above and below the horizontal portion).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Scarbrough and Hwang with the teachings of Nam because as both Scarbrough and Nam teach suitable shapes for a contact, it would have been obvious to substitute Scarbrough’s straight contacts with Nam’s contacts with protruding portions to achieve the predictable result of forming contacts with protruding portions.
Conclusion
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/COLE LEON LINDSEY/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812