DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/01/2026 has been entered.
Response to Amendment
An amendment filed on 06/01/2026 in response to the Office Action mailed on 04/01/2026 is
being acknowledged and entered into the record. The present Non-Final rejection is made by taking into fully consideration all the amendments.
Response to Arguments
On page 8 of the remarks, filed on 06/01/2026, with respect to the rejection of Claim 1, Applicant argues that there is no teaching or suggestion in Pagaila that the conductive vias 104 "extend (i) peripherally around the stack of upper semiconductor dies," as recited in amended claim 1. This argument is fully considered but is not persuasive. The rejection of Claim 1 is based on a combination of two different embodiments of Pagaila shown in Fig. 9 and Fig. 10, in which the upper die 100 of Fig. 10 is replaced with the stack of dies 80 of Fig. 9 (see detailed rejection below). As such, the combination of embodiments of Pagaila teaches the conductive vias 86 extend peripherally around the stack of upper semiconductor dies 80,". Therefore, Pagaila is still relied upon to teach some of the limitations of amended claim 1.
On page 8 of the remarks, filed on 06/01/2026, with respect to the rejection of Claim 1, Applicant argues that the conductive vias 104 of Pagaila are not exposed at sidewalls of the semiconductor device assembly, as recited in amended claim 1. This argument is fully considered and is persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of previously applied prior art references of Pagaila/Bitz/Bartley and newly found prior art of Dimaano. Dimaano teaches the above newly added limitation of amended Claim 1.
On page 8 of the remarks, filed on 06/01/2026, with respect to the rejection of Claim 1, Applicant argues that Pagaila fails to disclose, teach, or suggest
"an encapsulant material ... horizontally extending between the conductive package perimeter material and the lower semiconductor die" and
"the conductive package perimeter material extends . .. vertically from (a) an upper surface of a portion of the encapsulant material that horizontally extends over the lower semiconductor die to (b) a lower surface of the thermal interface layer," as recited in amended claim 1.
These arguments are fully considered but are not persuasive. Pagaila does teach the above limitation A, i.e., an encapsulant material 136 ... horizontally extending between the conductive package perimeter 104 material and the lower semiconductor die 120 (see the gap between dies 100 and 120 in Fig. 10: 136, 104, 120). Furthermore, one cannot show non-obviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). As such, the combination of Pagaila and Barley suggests the above limitation B. i.e., a person of ordinary skill in the art would have recognized that when the thermal interface layer of Barley is disclosed over the stack of upper semiconductor die in the semiconductor device of Pagaila et al., the conductive package perimeter material can be made to extend vertically from (a) an upper surface of a portion 136 of the encapsulant material 105, 136 that horizontally extends over the lower semiconductor die 120 to (b) a lower surface of the thermal interface layer. Therefore, Pagaila and Bartley are still relied upon to teach some of the limitations of Claim 1.
On page 9 of the remarks, filed on 06/01/2026, with respect to the rejection of Claim 1, Applicant argues that Bitz fails to disclose the conductive package perimeter material is exposed at sidewalls of the semiconductor device assembly, as recited in amended claim 1. This argument is fully considered and is persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of previously applied prior art references of Pagaila/Bitz/Bartley and newly found prior art of Dimaano. Dimaano teaches the above limitation of amended Claim 1.
On page 9 of the remarks, filed on 06/01/2026, with respect to the rejection of Claim 1, Applicant argues that Bitz fails to show "the conductive package perimeter material extends . .. vertically from (a) an upper surface of a portion of the encapsulant material that horizontally extends over the lower semiconductor die to (b) a lower surface of the thermal interface layer," as recited in amended claim 1. These arguments are fully considered but are not persuasive for the same reasons indicated in paragraph 4 above.
On page 10 of the remarks, filed on 06/01/2026, with respect to the rejection of Claim 8, Applicant argues that Pagaila and/or Bitz fails to disclose, teach, or suggest "wherein the conductive rectangular annulus extends vertically from an upper surface of the lower semiconductor die to a plane comprising an upper surface of an uppermost semiconductor die of the stack of upper semiconductor dies,” as recited in amended claim 8. This argument is fully considered but is not persuasive for the same reasons indicated in paragraph 1 of this section. Therefore, Pagaila is still relied upon to teach the above limitation of Claim 8.
On page 10 of the remarks, filed on 06/01/2026, with respect to the rejection of Claim 8, Applicant argues that Pagaila and/or Bitz fails to disclose, teach, or suggest wherein the conductive rectangular annulus is exposed at sidewalls of the semiconductor device assembly," as recited in amended claim 8. This argument is fully considered and is persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of previously applied prior art references of Pagaila/Bitz/Bartley and newly found prior art of Dimaano. Dimaano teaches the above limitation of amended Claim 8.
New grounds of rejections are also made for all claims dependent on Claim 1 and Claim 8.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Pagaila et al. (US 20120018899 A1), in view of Bitz et al. (US 20190333840 A1), Bartley et al. (US 20120007229 A1) and Dimaano JR. et al. (US 20190051614 A1).
Regarding Claim 1, Pagaila et al. discloses a semiconductor device assembly, comprising:
a lower semiconductor die 120 (Fig. 10: 120, paragraph 0049);
a stack of upper semiconductor dies 100, disposed over the lower semiconductor die 120 (Fig. 10: 100, 112, 120, paragraph 0049);
Note that while Fig. 10 shows only one upper semiconductor die 100, in a different embodiment shown in Fig. 9, Pagaila teaches a stack of semiconductor dies 80 and that any one of the semiconductor die in the different embodiments shown in Figs, 3-9 can be integrated into the semiconductor device assembly shown in FIG. 10 (see paragraph 0051). Therefore, a person of ordinary skill in the art, would have combined the different embodiments of Pagaila et al. and disposed the stacked semiconductor die 80 of Fig. 9 in place of the upper semiconductor die 100 of Fig. 10, such that a stack of upper semiconductor dies 80 (of Fig. 9) are disposed over the lower semiconductor die 120 (of Fig. 10).
a thermal interface layer disposed above the stack of upper semiconductor dies;
a conductive package perimeter material 104/86 surrounding the stack of upper semiconductor dies 80/100 (see Fig. 9: 80, 86, Fig. 10: 104, 100, paragraph 0048, 0049);
and an encapsulant material 105, 136 disposed between sidewalls of the stack of upper semiconductor dies 100/80 and the conductive package perimeter material 104/86, and horizontally extending between the conductive package perimeter material 104 and the lower semiconductor die 120 (Fig. 10: 105, 136, 104, 120, 100, paragraph 0049, 0050).
Note that in Fig. 10, encapsulant material 105 is disposed between sidewalls of the upper semiconductor die 100 and the conductive package perimeter material 104, and encapsulant material 136 horizontally extends between the conductive package perimeter material 104 and the lower semiconductor die 120 within the gap between the dies 100 and 120. Both 105, 136 are made of a molding compound (see paragraph 0037, which indexes the encapsulant material as 43 in a different embodiment, and paragraph 0050).
wherein the encapsulant material fully electrically isolates the conductive package perimeter material from the stack of upper semiconductor dies,
wherein the conductive package perimeter material extends 104/86 (i) peripherally around the stack of upper semiconductor dies 100/80 and (ii) vertically from (a) an upper surface of a portion 105 of the encapsulant material 105, 136 that horizontally extends over the lower semiconductor die 120 to (b) a lower surface of the thermal interface layer,
and wherein the conductive package perimeter material is exposed at sidewalls of the semiconductor device assembly.
Bartley et al. discloses a semiconductor device assembly, comprising the following limitation not disclosed in Pagaila et al.:
a thermal interface layer 240 disposed above a stack of upper semiconductor dies 231 (Fig. 4: 240, 231, paragraph 0021).
Therefore, a person of ordinary skill in the art, would have combined the teachings of Pagaila et al. with teachings of Bartley et al. in order to have a thermal interface layer disposed above the stack of upper semiconductor dies. Doing so would provide cooling for the die stack as recognized by Bartley et al. (paragraph 0020).
Further, a person of ordinary skill in the art would have recognized that when the thermal interface layer of Barley is disclosed over the stack of upper semiconductor die in the semiconductor device of Pagaila et al., the conductive package perimeter material can be made to extend vertically from (a) an upper surface of a portion 136 of the encapsulant material 105, 136 that horizontally extends over the lower semiconductor die 120 to (b) a lower surface of the thermal interface layer.
Bitz et al. discloses a semiconductor device assembly comprising the following limitations not disclosed in Pagaila et al.:
wherein the encapsulant material 110 fully electrically isolates the conductive package perimeter material 480 from the stack of upper semiconductor dies 124 (Fig. 4: 110, 480, 124, paragraph 0025).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Pagaila et al. and Bitz et al. in order to have the encapsulant material fully electrically isolate the conductive package perimeter material from the stack of upper semiconductor dies. Doing so would ensure the conductive package material provides EMI shielding without creating any short circuits.
Dimaano JR. et al. discloses a semiconductor device assembly comprising the following limitations not disclosed in Pagaila et al.:
and wherein the conductive package perimeter material 150 is exposed at sidewalls of the semiconductor device assembly 100a (Fig 1a: 150, 100a, paragraph 0020, 0028).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Pagaila et al. and Dimaano JR. et al. in order to have the conductive package perimeter material exposed at sidewalls of the semiconductor device assembly. Doing so would provide a low impedance grounding and EMI shielding path.
Regarding Claim 2, Pagaila et al. fails to teach the semiconductor device assembly of claim 1, wherein the encapsulant material 136, 105 fully electrically isolates the conductive package perimeter material 104 from the lower semiconductor die 120.
However, Bitz et al., in a different embodiment, teaches a spacer 558 formed of the encapsulant material 510 between the lower semiconductor die 104 and the channel 550 (Fig. 5: 558, 550, 104, paragraph . Therefore, it would have been obvious to a person of ordinary skill in the art to have combined the different embodiments of Bitz et al. in order to have the spacer 558 including the encapsulant material 110/510 formed in the semiconductor device assembly of Fig. 4 such that the encapsulant material 110/550 fully electrically isolates the conductive package perimeter material 480 from the lower semiconductor die 104. Doing so would ensure the conductive package material provides EMI shielding without creating any short circuits.
Regarding Claim 4, Pagaila et al. teaches the semiconductor device assembly of claim 1, wherein the conductive package perimeter material 104 comprises copper, silver, gold, nickel, tungsten, or a combination thereof (paragraph 0041).
Regarding Claim 6, Pagaila et al. teaches the semiconductor device assembly of claim 1, wherein a top surface of the stack of upper semiconductor dies 80 and a top surface of the conductive package perimeter material 86 are coplanar (see Fig. 9).
Note that the layer 84 that appears to be a protruding portion of the conductive package perimeter material 86 from the top surface corresponds to a contact pad 84 formed on the top surface (see Fig. 9 and paragraph 0048).
Regarding Claim 7, Pagaila et al. teaches the semiconductor device assembly of claim 1, wherein the encapsulant material 136, 105 is a molding compound including at least one of an epoxy-based liquid compound with granules, an epoxy-based liquid compound without granules, a granular compound, a thin- film based underfill, a thin-film based compound, a resin-based encapsulant, or a polymer (see paragraph 0037 and paragraph 0050).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Pagaila et al. (US 20120018899 A1), in view of Bitz et al. (US 20190333840 A1), Bartley et al. (US 20120007229 A1) and Dimaano JR. et al. (US 20190051614 A1), as applied to Claim 1 above, further in view of Patil et al. (US 20210249359 A1).
The combination of Pagaila et al., Bitz et al., Dimaano Jr. et al. and Bartley et al. fails to explicitly teach the semiconductor device assembly of claim 1, wherein the thermal interface layer is configured to provide electromagnetic interference (EMI) shielding for the semiconductor device assembly.
However, Patil et al. teaches a semiconductor device assembly comprising a thermal interface layer 140, 150, wherein the thermal interface layer 140, 150 is configured to provide electromagnetic interference (EMI) shielding for the semiconductor device assembly (Fig. 1A: 140, 150, paragraph 0018, 0020-0022).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention using the combined teachings of Pagaila et al., Bartley et al. and Patil et al., would have recognized that the thermal interface layer is configured to provide electromagnetic interference (EMI) shielding for the semiconductor device assembly. Doing so would provide both provide thermal and EMI shield solution in a single structure, as recognized by Patil et al. (paragraph 0018).
Claim 8 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Pagaila et al. (US 20120018899 A1), in view of Dimaano JR. et al. (US 20190051614 A1).
Regarding Claim 8, Pagaila et al. teaches a semiconductor device assembly, comprising:
a lower semiconductor die 120 (Fig. 10: 120, paragraph 0049);
a stack of upper semiconductor dies 100, disposed over the lower semiconductor die 120 (Fig. 10: 100, 120, paragraph 0049);
Note that while Fig. 10 shows only one upper semiconductor die 100, in a different embodiment shown in Fig. 9, Pagaila teaches a stack of semiconductor dies 80 and that any one of the semiconductor die in the different embodiments shown in Figs, 3-9 can be integrated into the semiconductor device assembly shown in FIG. 10 (see paragraph 0051). Therefore, a person of ordinary skill in the art, would have combined the different embodiments of Pagaila et al. and disposed the stacked semiconductor die 80 of Fig. 9 in place of the upper semiconductor die 100 of Fig. 10, such that a stack of upper semiconductor dies 80 (of Fig. 9) are disposed over the lower semiconductor die 120 (of Fig. 10).
a conductive rectangular annulus 104/86 surrounding sidewalls of the upper semiconductor dies 100/80 and having a footprint within a footprint of the lower semiconductor die 120, (Fig. 10: 104, 100, see Fig. 9: 80, 86, paragraph 0049);
Note that according to Fig. 2e, the conductive material 46 is initially formed in a rectangular annulus. Further note that Pagaila et al. teaches the conductive package perimeter material 86 in Fig. 9 surrounds sidewalls of the stack of semiconductor dies 80 (see Fig. 9: 80, 86, paragraph 0048).
wherein the conductive rectangular annulus 104/86 extends vertically from an upper surface of the lower semiconductor die 102 to a plane comprising an upper surface of an uppermost semiconductor die 80 of the stack of upper semiconductor dies 80/100 (Fig. 10: 104, 100, see Fig. 9: 80, 86, paragraph 0048, 0049),
Note that when the semiconductor die stack 80 of Fig. 9 is disposed in the semiconductor assembly of Fig. 10 in place of the die 100, the conductive package perimeter material 104/86 will extend vertically from an upper surface of the lower semiconductor die 102 to a plane comprising an upper surface of an uppermost semiconductor die 80 of the stack of upper semiconductor dies 80/100.
and wherein the conductive rectangular annulus is exposed at sidewalls of the semiconductor device assembly;
and an encapsulant material 88 fully electrically isolating sidewalls of the stack of upper semiconductor dies 80 from the conductive rectangular annulus 86 (see Fig. 9: 80, 86, 88, paragraph 0049).
Note that the encapsulating material 88 is located between the stack of upper semiconductor dies 80 and the conductive rectangular annulus 86 of Fig. 9 and hence would fully electrically isolate sidewalls of the stack of upper semiconductor dies 80 from the conductive rectangular annulus 86.
Dimaano JR. et al. discloses a semiconductor device assembly comprising the following limitations not disclosed in Pagaila et al.:
and wherein the conductive package perimeter material 150 is exposed at sidewalls of the semiconductor device assembly 100a (Fig 1a: 150, 100a, paragraph 0020, 0028).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Pagaila et al. and Dimaano JR. et al. in order to have the conductive package perimeter material exposed at sidewalls of the semiconductor device assembly. Doing so would provide a low impedance grounding and EMI shielding path.
Regarding Claim 11, Pagaila et al. teaches the semiconductor device assembly of claim 8, wherein the conductive rectangular annulus 104 comprises copper, silver, gold, nickel, tungsten, or a combination thereof (paragraph 0041).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Pagaila et al. (US 20120018899 A1), in view of Dimaano JR. et al. (US 20190051614 A1), as applied to Claim 8 above, further in view of Bartley et al. (US 20120007229 A1).
The combination of Pagaila et al. and Dimaano JR. et al. fails to teach the semiconductor device assembly of claim 8, further includes a thermal interface layer disposed above the stack of upper semiconductor dies and the conductive rectangular annulus.
However, Bartley et al. discloses a semiconductor device assembly, comprising a thermal interface layer 240 disposed above a stack of upper semiconductor dies 231 (Fig. 4: 240, 231, paragraph 0021).
Therefore, a person of ordinary skill in the art, would have combined the teachings of Pagaila et al. with teachings of Bartley et al. in order to have a thermal interface layer disposed above the stack of upper semiconductor dies. Doing so would provide cooling for the die stack as recognized by Bartley et al. (paragraph 0020).
Furthermore, a person of ordinary skill in the art would have recognized that the thermal interface layer of Bartley et al. could be disposed above the stack of upper semiconductor dies and the conductive rectangular annulus in the semiconductor device assembly of Pagaila et al.
Allowable Subject Matter
Claims 12-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding Claim 12, Pagaila et al. (US 20120018899 A1) teaches a method of forming a plurality of semiconductor assemblies, comprising:
stacking a plurality of semiconductor die 32, 36 to a device wafer 28 (Fig. 2b: 28, 32, 36, paragraph 0034);
disposing a spacer assembly structure 48, 46 including a spacer material 48 and a conductive package perimeter material 46 around each of the plurality of semiconductor die 32, 36 (Fig. 2e: 48, 46, 32, 36, paragraph 0041);
disposing an encapsulant material 43 between the conductive package perimeter material 46 of the spacer assembly structure 48, 46 and the corresponding semiconductor die 32, 36 (Fig. 2e: 48, 43, 46, 32, 36, paragraph 0042);
Pagaila et al. fails to explicitly teach the plurality of semiconductor die 32, 36 are die stacks, and the spacer assembly structure 48, 46 is a preformed spacer assembly structure, and heating the plurality of semiconductor assemblies in an elevated temperature to expand the spacer material, wherein an expansion of the spacer material singulates the device wafer into the plurality of semiconductor assemblies.
However, in a different embodiment, Pagaila et al. teaches a method of forming a semiconductor assembly, comprising a semiconductor die stack 80 (see Fig. 9: 80, paragraph 0048).
Therefore, a person of ordinary skill in the art, would have combined the different embodiments of Pagaila et al. and disposed the semiconductor die stack 80 of Fig. 9 in place of the semiconductor die 32, 36 of Fig. 2b in order to come up with the claimed invention. By doing so, a semiconductor assembly with two or more stacked semiconductor die can be formed in one step, as recognized by Pagaila et al. (paragraph 0048).
Furthermore, Liu et al. (US 6800169 B2) teaches a preformed spacer assembly including a spacer material 50 and a conductive package perimeter material 56 formed on a carrier wafer 58 (Fig. 8: 50, 56, 58, column 13, lines 8-15, lines 22-45),
Note that the assembly of Fig. 8 shows metal posts 56 formed on a carrier wafer 58 and a spacer material 50 is formed over the metal posts 56, and openings 60 are formed in the spacer material 50, leaving behind a structure which is similar to the structure of a preformed spacer assembly of the claimed invention as depicted in Fig. 2C and Fig. 2D of the originally filed disclosure.
Therefore, a person of ordinary skill in the art, would have combined the teachings of Pagaila et al. with Liu et al. in order to form a pre-formed spacer assembly structure similar to that taught by Liu et al. and incorporate it in the semiconductor assembly of Pagaila et al. By doing so, the spacer assembly can be separately formed and attached to the semiconductor die assembly in a later step, thereby preventing the semiconductor die from being exposed to high temperatures and solvents used during the spacer assembly formation process.
However, the prior art of record fails to teach heating the plurality of semiconductor assemblies in an elevated temperature to expand the spacer material, wherein an expansion of the spacer material singulates the device wafer into the plurality of semiconductor assemblies.
Claims 13-20 are allowed due to their dependency on Claim 12.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNA F IQBAL whose telephone number is 571-272-1587. The examiner can normally be reached M-F: 8.30 am - 5.30 pm EST.
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/HAMNA FATHIMA IQBAL/Examiner, Art Unit 2817 06/09/2026
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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