DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
An amendment filed on 07/28/2025 in response to the Office Action mailed on 08/14/2025 is
being acknowledged and entered into the record. The present Final rejection is made by taking into fully
consideration all the amendments.
Response to Arguments
Applicant’s arguments, see page, filed on 10/28/2025, with respect to the objection to the specification have been fully considered and are persuasive. The objection to the specification has been withdrawn.
Applicant’s arguments, see page, filed on 10/28/2025, with respect to the 112(a) rejection of Claim 5 have been fully considered and are persuasive. The rejection has been withdrawn.
Applicant’s arguments, see page, filed on 10/28/2025, with respect to the 112(b) rejection of Claim 5 have been fully considered and are persuasive. The rejection has been withdrawn.
Applicant’s arguments, see page, filed on 10/28/2025, with respect to the 112(b) rejection of Claim 19 have been fully considered and are persuasive. The rejection has been withdrawn.
Applicant’s arguments, see pages 8, filed 07, with respect to the rejection of claim 1 under 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of previously applied prior art of new ground of rejection is also made for all dependent claims.
Applicant’s arguments, see pages 9-10, filed 07, with respect to the rejection of claim 8 under 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of previously applied prior art of new ground of rejection is also made for all dependent claims.
Applicant’s arguments, see pages 9-10 of the remarks, filed on 10/28/2025, with respect to the 103 rejection of Claim 12 have been fully considered and are persuasive. The rejection of Claim 12 and all dependent Claims has been withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 6-8, 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Pagaila et al. (US 20120018899 A1), in view of Bitz et al. (US 20190333840 A1).
Regarding Claim 1, Pagaila et al. discloses a semiconductor device assembly, comprising:
a lower semiconductor die 120 (Fig. 10: 120, paragraph 0049);
a stack of upper semiconductor dies 100, 112 disposed over the lower semiconductor die 120 (Fig. 10: 100, 112, 120, paragraph 0049);
a conductive package perimeter material 104 surrounding an upper semiconductor die 100 (Fig. 10: 104, 100, paragraph 0049);
and an encapsulant material 105, 136 is disposed between sidewalls of the upper semiconductor die 100 and the conductive package perimeter material 104, and horizontally extending between the conductive package perimeter material 104 and the lower semiconductor die 120 (Fig. 10: 105, 136, 104, 120, 100, paragraph 0049, 0050).
Note that in Fig. 10, encapsulant material 105 is disposed between sidewalls of the upper semiconductor die 100 and the conductive package perimeter material 104, and encapsulant material 105 horizontally extends between the conductive package perimeter material 104 and the lower semiconductor die 120. Both 105, 136 are made of a molding compound (see paragraph 0037, which indexes the encapsulant material as 43 in a different embodiment, and paragraph 0050).
Pagaila et al. fails to explicitly teach the conductive package perimeter material surrounds the stack of upper semiconductor dies 100, 112, and an encapsulant material 136, 105 is disposed between sidewalls of the stack of upper semiconductor dies 100, 112 and the conductive package perimeter material 104, wherein the encapsulant material 136, 105 fully electrically isolates the conductive package perimeter material 104 from the stack of upper semiconductor dies 100, 112.
However, in a different embodiment, Pagaila et al. teaches the conductive package perimeter material 86 surrounds the stack of semiconductor dies 80, and an encapsulant material 88 is disposed between sidewalls of the stack of semiconductor dies 80 and the conductive package perimeter material 86 (see Fig. 9: 80, 86, 88, paragraph 0048). Pagaila further teaches that any one of the semiconductor die in the different embodiments can be integrated into the semiconductor device assembly shown in FIG. 10 (see paragraph 0051).
Therefore, a person of ordinary skill in the art, would have combined the different embodiments of Pagaila et al. and disposed the stacked semiconductor die 80 of Fig. 9 in place of the upper semiconductor die 100 of Fig. 10, such that the conductive package perimeter material surrounds the stack of semiconductor dies, and an encapsulant material is disposed between sidewalls of the stack of semiconductor dies and the conductive package perimeter material 86. By doing so, the spacer assembly in the back-to-back stacking scheme can be formed in one step for two or more stacked semiconductor die, as recognized by Pagaila et al. (paragraph 0048).
Furthermore, Bitz et al. discloses a semiconductor device assembly, wherein the encapsulant material 110 fully electrically isolates the conductive package perimeter material 480 from the stack of upper semiconductor dies 124 (Fig. 4: 110, 480, 124, paragraph 0025).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Pagaila et al. and Bitz et al. in order to have the encapsulant material fully electrically isolates the conductive package perimeter material from the stack of upper semiconductor dies. Doing so would ensure the conductive package material provides EMI shielding without creating any short circuits.
Regarding Claim 2, Pagaila et al. fails to teach the semiconductor device assembly of claim 1, wherein the encapsulant material 136, 105 fully electrically isolates the conductive package perimeter material 104 from the lower semiconductor die 120.
However, Bitz et al., in a different embodiment, teaches a spacer 558 formed of the encapsulant material 510 between the lower semiconductor die 104 and the channel 550 (Fig. 5: 558, 550, 104, paragraph . Therefore, it would have been obvious to a person of ordinary skill in the art to have combined the different embodiments of Bitz et al. in order to have the spacer 558 including the encapsulant material 110/510 formed in the semiconductor device assembly of Fig. 4 such that the encapsulant material 110/550 fully electrically isolates the conductive package perimeter material 480 from the lower semiconductor die 104. Doing so would ensure the conductive package material provides EMI shielding without creating any short circuits.
Regarding Claim 4, Pagaila et al. teaches the semiconductor device assembly of claim 1, wherein the conductive package perimeter material 104 comprises copper, silver, gold, nickel, tungsten, or a combination thereof (paragraph 0041).
Regarding Claim 6, Pagaila et al. teaches the semiconductor device assembly of claim 1, wherein a top surface of the stack of upper semiconductor dies 80 and a top surface of the conductive package perimeter material 86 are coplanar (see Fig. 9).
Note that the layer 84 that appears to be a protruding portion of the conductive package perimeter material 86 from the top surface corresponds to a contact pad 84 formed on the top surface (see Fig. 9 and paragraph 0048).
Regarding Claim 7, Pagaila et al. teaches the semiconductor device assembly of claim 1, wherein the encapsulant material 136, 105 is a molding compound including at least one of an epoxy-based liquid compound with granules, an epoxy-based liquid compound without granules, a granular compound, a thin- film based underfill, a thin-film based compound, a resin-based encapsulant, or a polymer (see paragraph 0037 and paragraph 0050).
Regarding Claim 8, Pagaila et al. teaches a semiconductor device assembly, comprising:
a lower semiconductor die 120 (Fig. 10: 120, paragraph 0049);
a stack of upper semiconductor dies 100, 112 disposed over the lower semiconductor die 120 (Fig. 10: 100, 112, 120, paragraph 0049);
a conductive rectangular annulus 104 surrounding sidewalls of the upper semiconductor dies and having a footprint within a footprint of the lower semiconductor die 120 (Fig. 10: 104, 100, paragraph 0049);
Note that according to Fig. 2e, the conductive material 46 is initially formed in a rectangular annulus.
and an encapsulant material 105, 136 (Fig. 10: 105, 136, 104, 120, 100, paragraph 0049, 0050).
Pagaila et al. fails to explicitly teach the conductive rectangular annulus 104 surrounds sidewalls of the stack of upper semiconductor dies 100, 112, and the encapsulant material 105, 136 electrically isolates sidewalls of the stack of upper semiconductor dies 100, 112 from the conductive rectangular annulus 104, and the encapsulant material 105, 136 fully electrically isolating the conductive rectangular annulus 104 from an upper surface of the lower semiconductor die 120.
However, in a different embodiment, Pagaila et al. teaches the conductive package perimeter material 86 surrounds sidewalls of the stack of semiconductor dies 80, and an encapsulant material 88 electrically isolates sidewalls of the stack of upper semiconductor dies 80 from the conductive rectangular annulus 86 (see Fig. 9: 80, 86, 88, paragraph 0048). Pagaila further teaches that any one of the semiconductor die in the different embodiments can be integrated into the semiconductor device assembly shown in FIG. 10 (see paragraph 0051).
Therefore, a person of ordinary skill in the art, would have combined the different embodiments of Pagaila et al. and disposed the stacked semiconductor die 80 of Fig. 9 in place of the upper semiconductor die 100 of Fig. 10, such that the conductive rectangular annulus surrounds sidewalls of the stack of upper semiconductor dies and the encapsulant material electrically isolates sidewalls of the stack of upper semiconductor dies from the conductive rectangular annulus. By doing so, the conductive rectangular annulus can be formed in one step for two or more stacked semiconductor die, as recognized by Pagaila et al. (paragraph 0048).
Furthermore, Bitz et al., in one embodiment discloses a semiconductor device assembly comprising a conductive rectangular annulus 480 wherein the encapsulant material 110 fully electrically isolating the conductive rectangular annulus 480 from the stack of upper semiconductor dies 124 (Fig. 4: 110, 480, 124, paragraph 0025). Further, in a different embodiment, Bitz et al. teaches a spacer 558 formed of the encapsulant material 510 between the lower semiconductor die 104 and the channel 550 (Fig. 5: 558, 550, 104, paragraph 0027. Therefore, it would have been obvious to a person of ordinary skill in the art to have combined the teachings of Pagaila et al. with the teachings in the different embodiments of Bitz et al. in order to have the spacer 558 including the encapsulant material 110/510 formed in the semiconductor device assembly of Fig. 4 such that the encapsulant material 110/550 fully electrically isolates the conductive rectangular annulus 480 from an upper surface of the lower semiconductor die 104 (see Fig. 4: 480, 110, Fig. 5: 558, 510, paragraph 0027). Doing so would ensure the conductive rectangular annulus provides EMI shielding without creating any short circuits. .
Regarding Claim 10, Pagaila et al. teaches the semiconductor device assembly of claim 8, wherein a top surface of the stack of upper semiconductor dies 80 and a top surface of the conductive rectangular annulus 86 are coplanar (see Fig. 9).
Note that the layer 84 that appears to be a protruding portion of the conductive package perimeter material 86 from the top surface corresponds to a contact pad 84 formed on the top surface (see Fig. 9 and paragraph 0048).
Regarding Claim 11, Pagaila et al. teaches the semiconductor device assembly of claim 8, wherein the conductive rectangular annulus 104 comprises copper, silver, gold, nickel, tungsten, or a combination thereof (paragraph 0041).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Pagaila et al. (US 20120018899 A1), in view of Bitz et al. (US 20190333840 A1), as applied to Claim 1 above, further in view of Bartley et al. (US 20120007229 A1).
Pagaila et al. fails to teach the semiconductor device assembly of claim 1, further including a thermal interface layer disposed above the stack of upper semiconductor dies and the conductive package perimeter material.
However, Bartley et al. discloses a semiconductor device assembly, comprising a thermal interface layer 240 disposed above a stack of upper semiconductor dies 231 (Fig. 4: 240, 231, paragraph 0021).
Therefore, a person of ordinary skill in the art, would have combined the teachings of Pagaila et al. with teachings of Bartley et al. in order to have a thermal interface layer disposed above the stack of upper semiconductor dies. Doing so would provide cooling for the die stack as recognized by Bartley et al. (paragraph 0020).
Furthermore, a person of ordinary skill in the art would have recognized that the thermal interface layer of Bartley et al. could be disposed above the stack of upper semiconductor dies and the conductive package perimeter material in the semiconductor device assembly of Pagaila et al.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Pagaila et al. (US 20120018899 A1), in view of Bitz et al. (US 20190333840 A1), further in view of Bartley et al. (US 20120007229 A1), as applied to Claim 3 above, further in view of Patil et al. (US 20210249359 A1).
The combination of Pagaila et al., Bitz et al. and Bartley et al. fails to explicitly teach the semiconductor device assembly of claim 3, wherein the thermal interface layer is configured to provide electromagnetic interference (EMI) shielding for the semiconductor device assembly.
However, Patil et al. teaches a semiconductor device assembly comprising a thermal interface layer 140, 150, wherein the thermal interface layer 140, 150 is configured to provide electromagnetic interference (EMI) shielding for the semiconductor device assembly (Fig. 1A: 140, 150, paragraph 0018, 0020-0022).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention using the combined teachings of Pagaila et al., Bartley et al. and Patil et al., would have recognized that the thermal interface layer is configured to provide electromagnetic interference (EMI) shielding for the semiconductor device assembly. Doing so would provide both provide thermal and EMI shield solution in a single structure, as recognized by Patil et al. (paragraph 0018)
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Pagaila et al. (US 20120018899 A1), in view of Bitz et al. (US 20190333840 A1), as applied to Claim 8 above, further in view of Bartley et al. (US 20120007229 A1).
The combination of Pagaila et al. and Bitz et al. fails to teach the semiconductor device assembly of claim 8, further includes a thermal interface layer disposed above the stack of upper semiconductor dies and the conductive rectangular annulus.
However, Bartley et al. discloses a semiconductor device assembly, comprising a thermal interface layer 240 disposed above a stack of upper semiconductor dies 231 (Fig. 4: 240, 231, paragraph 0021).
Therefore, a person of ordinary skill in the art, would have combined the teachings of Pagaila et al. with teachings of Bartley et al. in order to have a thermal interface layer disposed above the stack of upper semiconductor dies. Doing so would provide cooling for the die stack as recognized by Bartley et al. (paragraph 0020).
Furthermore, a person of ordinary skill in the art would have recognized that the thermal interface layer of Bartley et al. could be disposed above the stack of upper semiconductor dies and the conductive rectangular annulus in the semiconductor device assembly of Pagaila et al.
Allowable Subject Matter
Claims 12-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding Claim 12, Pagaila et al. (US 20120018899 A1) teaches a method of forming a plurality of semiconductor assemblies, comprising:
stacking a plurality of semiconductor die 32, 36 to a device wafer 28 (Fig. 2b: 28, 32, 36, paragraph 0034);
disposing a spacer assembly structure 48, 46 including a spacer material 48 and a conductive package perimeter material 46 around each of the plurality of semiconductor die 32, 36 (Fig. 2e: 48, 46, 32, 36, paragraph 0041);
disposing an encapsulant material 43 between the conductive package perimeter material 46 of the spacer assembly structure 48, 46 and the corresponding semiconductor die 32, 36 (Fig. 2e: 48, 43, 46, 32, 36, paragraph 0042);
Pagaila et al. fails to explicitly teach the plurality of semiconductor die 32, 36 are die stacks, and the spacer assembly structure 48, 46 is a preformed spacer assembly structure, and heating the plurality of semiconductor assemblies in an elevated temperature to expand the spacer material, wherein an expansion of the spacer material singulates the device wafer into the plurality of semiconductor assemblies.
However, in a different embodiment, Pagaila et al. teaches a method of forming a semiconductor assembly, comprising a semiconductor die stack 80 (see Fig. 9: 80, paragraph 0048).
Therefore, a person of ordinary skill in the art, would have combined the different embodiments of Pagaila et al. and disposed the semiconductor die stack 80 of Fig. 9 in place of the semiconductor die 32, 36 of Fig. 2b in order to come up with the claimed invention. By doing so, a semiconductor assembly with two or more stacked semiconductor die can be formed in one step, as recognized by Pagaila et al. (paragraph 0048).
Furthermore, Liu et al. (US 6800169 B2) teaches a preformed spacer assembly including a spacer material 50 and a conductive package perimeter material 56 formed on a carrier wafer 58 (Fig. 8: 50, 56, 58, column 13, lines 8-15, lines 22-45),
Note that the assembly of Fig. 8 shows metal posts 56 formed on a carrier wafer 58 and a spacer material 50 is formed over the metal posts 56, and openings 60 are formed in the spacer material 50, leaving behind a structure which is similar to the structure of a preformed spacer assembly of the claimed invention as depicted in Fig. 2C and Fig. 2D of the originally filed disclosure.
Therefore, a person of ordinary skill in the art, would have combined the teachings of Pagaila et al. with Liu et al. in order to form a pre-formed spacer assembly structure similar to that taught by Liu et al. and incorporate it in the semiconductor assembly of Pagaila et al. By doing so, the spacer assembly can be separately formed and attached to the semiconductor die assembly in a later step, thereby preventing the semiconductor die from being exposed to high temperatures and solvents used during the spacer assembly formation process.
However, the prior art of record fails to teach heating the plurality of semiconductor assemblies in an elevated temperature to expand the spacer material, wherein an expansion of the spacer material singulates the device wafer into the plurality of semiconductor assemblies.
Claims 13-20 are allowed due to their dependency on Claim 12.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNA F IQBAL whose telephone number is 571-272-1587. The examiner can normally be reached M-F: 8.30 am - 5.30 pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at 571-272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HAMNA FATHIMA IQBAL/Examiner, Art Unit 2817 03/26/2026
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 March 27, 2026