DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 16, and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “packaging a power device in plastic to form a power semiconductor component by soldering the first substrate to a first face of the power device using a second material.” It is unclear how the soldering of the first substrate to a first face of the powder device using a second material is related to the plastic packaging step, i.e. it is unclear how the plastic packaging is achieved by soldering the substrate to the power device.
Claims 16 and 18 require a second arc-shaped segment disposed on a first/second heat sink. It is unclear, however, which element the claims are requiring to be arc-shaped and to be disposed on the first/second heat sink. Applicant has disclosed that the first and second substrates are formed to be arc-shaped (bent, para. [0184]), and this is the only element or part of the device that is ever disclosed as having an arc-shape at some point in the manufacturing process. However, MPEP 2111 reads: “[t]hough understanding the claim language may be aided by explanations contained in the written description, it is important not to import into a claim limitations that are not part of the claim.” However, claims 16 and 18 do not require that the second substrate is the intended are arc-shaped (as this feature is only claimed in claim 17), thus it would be improper to read the specification into the claims regarding the second arc-shaped segment. For examination purposes, the examiner will interpret “second arc-shaped segment” disposed on the first/second heat sink its broadest reasonable interpretation to mean an element of the device in the shape of an arc or a constituent of an arc shape is disposed on the heat sink. It is also unclear if the label “second arc-shaped segment” recited in both claims 16 and 18 are referring to the same element of the device or if the claims are each referring to two different elements of the device but using the same label. If these elements are intended to refer to different elements of the device, the examiner suggests changing the label of one of the claimed “second arc-shaped segments” to make the distinction clear between the two. For examination purposes, the examiner will interpret
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 7-8, 13, and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Funakoshi et al. (“Funakoshi” US 2009/0116197), Ishimatsu et al. (“Ishimatsu” US 2023/0163078), and Hong et al. (“Hong” US 2019/0273034).
Regarding claim 1, Funakoshi discloses:
A method for producing a power semiconductor system (Figure 1 inverted, shown below) comprising:
packaging a power device (1) in plastic (25, epoxy resin) to form a power semiconductor component (portion of device in Figure 1 encapsulated by sealing resin 25) by soldering a first substrate (18) to a first face of the power device (1, lower surface) using a second material (15, para. [0028]);
forming a first heat dissipation face (lower surface of sealed power semiconductor component) on a surface of the power semiconductor component (lower surface);
heating a first material (12, 22, para. [0031]) between a first heat sink (23) and the first heat dissipation face (shown in Figure 1); and
cooling the first material (12, 22) on the first heat dissipation face to couple the power semiconductor component and the first heat sink (23, since the first material 12, 22 is heated, it is apparent that it would be subsequently removed from the furnace used, para. [0031], to heat the first material 12, 22, thereby cooling the first material 12, 22 and coupling the components).
In the event that Funakoshi does not disclose cooling the first material, which the examiner does not concede, it would have been obvious to cool the first material to couple the component to the heat sink as this is a well-known method of bonding a semiconductor component to a metallic medium together in the art as disclosed by Ishimatsu in para, [0067]: “by heating and then cooling the conductive bonding paste, the conductive bonding material is obtained from the conductive bonding paste. As result, the semiconductor chip 4a is bonded to the lead 11 via the conductive bonding material, and the semiconductor chip 4b is bonded to the lead 12 via the conductive bonding material.” Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the present invention to incorporate the heating and cooling bonding technique as disclosed by Ishimatsu into the teachings of Funakoshi.
Funakoshi does not disclose forming a first substrate into a first arc-shaped segment, wherein the first arc-shaped segment is located in a middle portion of the first substrate.
However, Hong discloses a process of pre-bending a substrate in an arc shape in a center portion of a substrate, see Figure 1 and para. [0010]).
It would have been obvious to one having ordinary skill in the art to incorporate the pre-bending process of the substrate as taught by Hong into the teachings of Funakoshi in order to increase reliability of the package (Hong, para. [0010]).
Regarding claim 2, Funakoshi discloses:
The method of claim 1, wherein a second melting point of the second material (15) is equal to or higher than a first melting point of the first material (12, 22, para. [0030]), and wherein forming the first heat dissipation face comprises forming the first heat dissipation face on a second face of the first substrate (18, lower surface in inverted Figure 1) that is away from the power device (shown below).
Regarding claim 7, Funakoshi discloses:
The method of claim 2, wherein packaging the power device further comprises:
soldering, using a fourth material (3, para. [0024]), a conductive pad (5, interpreted to be a conductive pad because it is a conductive material) to a third face of the power device (1, upper surface in inverted Figure 1) that is away from the first substrate (18, shown below);
wherein a fourth melting point of the fourth material (3) is equal to or higher than the first melting point of the first material (12, 22, para. [0030]);
soldering, using a fifth material (7, para. [0025]), a second substrate (9) to a fourth face of the conductive pad (upper surface of conductive pad 5) that is away from the power device (1), wherein a fifth melting point of the fifth material (7) is equal to or higher than the first melting point of the first material (12, 22, para. [0030]); and
forming a second heat dissipation face on a fifth face of the second substrate (9, upper surface in inverted Figure 1) that is away from the power device (1).
Regarding claim 8, Funakoshi discloses:
The method of claim 7, wherein heating the first material comprises:
heating the first material (12, 22) between a second heat sink (13) and the second heat dissipation face (upper surface of 9 in inverted Figure 1), and wherein the method further comprises: cooling the first material (12, 22) on the second heat dissipation face to couple the power semiconductor component and the second heat sink (13, since the first material 12, 22 is heated, it is apparent that it would be subsequently removed from the furnace used, para. [0031], to heat the first material 12, 22, thereby cooling the first material 12, 22 and coupling the components).
In the event that Funakoshi does not disclose cooling the first material, which the examiner does not concede, it would have been obvious to cool the first material to couple the component to the heat sink as this is a well-known method of bonding a semiconductor component to a metallic medium together in the art as disclosed by Ishimatsu in para, [0067]: “by heating and then cooling the conductive bonding paste, the conductive bonding material is obtained from the conductive bonding paste. As result, the semiconductor chip 4a is bonded to the lead 11 via the conductive bonding material, and the semiconductor chip 4b is bonded to the lead 12 via the conductive bonding material.” Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the present invention to incorporate the heating and cooling bonding technique as disclosed by Ishimatsu into the teachings of Funakoshi.
Regarding claim 13, Funakoshi discloses:
The method of claim 1, wherein before heating the first material (12, 22), the method further comprises:
disposing, on the first heat dissipation face, an elevation member (34) configured to identify a usage amount of the first material (12, 22), and wherein the elevation member comprises any one of:
a metal material that is disposed on the first heat dissipation face, and that protrudes from the first heat dissipation face to form the elevation member;
a bump (34) that is fastened on the first heat dissipation face, and that forms the elevation member (shown in Figure 1); or
a groove that is disposed on the first heat dissipation face, and that forms the elevation member.
It is the examiner’s position that the elevation member 34 of Funakoshi performs the function of identifying a usage of the first material because protrusions 33, 34 ensure the minimum thickness of the joining materials 12, 22 (para. [0033]) and thus would ensure that a certain amount of first material is used because a thickness of a layer can indicate and control the amount of material is used in that layer.
Regarding claim 16, Funakoshi discloses:
The method of claim 1, wherein before heating the first material (12, 22), the method further comprises: disposing a second arc-shaped segment (24, see Figure 1) on the first heat sink (23), and wherein the second arc-shaped segment is located at a position of the first heat sink (23) that corresponds to the power device (1, here “correspond” is interpreted to indicate that the arc-shaped segment is vertically overlapping or aligned with the power device 1).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to heat the first material after disposing an arc-shaped segment on the first heat sink since the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946); In re Gibson, 39 F.2d 975, 5 USPQ 230 (CCPA 1930). See MPEP § 2144.04.
Regarding claim 17, Funakoshi does not disclose forming the second substrate into a second arc-shaped segment prior to soldering the second substrate to the fourth face.
However, Hong discloses a process in which before soldering the second substrate (9) to the fourth face (discloses a pre-bending technique, para. [0004]-0010]), the method further comprises forming the second substrate (9) into a second arc-shaped segment (see Figure 1), and wherein the second arc-shaped segment is located in a middle part of the second substrate (see Figure 1).
It would have been obvious to one having ordinary skill in the art to incorporate the pre-bending process of the substrate as taught by Hong into the teachings of Funakoshi in order to increase reliability of the package (Hong, para. [0010]). Note that the same process of pre-bending is incorporated also by Hong into the first substrate in claim 1, and it should be appreciated that the same process can be used for the second substrate as well even though Hong does not explicitly disclose a stacked configuration as Funakoshi teaches.
Regarding claim 18, Funakoshi discloses:
The method of claim 8, further comprising:
disposing the second heat sink (13) on the second heat dissipation face (shown in Figure 1); and
disposing a second arc-shaped segment (14) on the second heat sink (13) before heating the first material (12, 22) between the second heat sink (13) and the second heat dissipation face, wherein the second arc-shaped segment (14) is located at a position of the second heat sink (13) that corresponds to the power device (1, here “correspond” is interpreted to indicate that the arc-shaped segment is vertically overlapping or aligned with the power device 1).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to dispose an arc-shaped segment on the second heat sink before heating the first material since the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946); In re Gibson, 39 F.2d 975, 5 USPQ 230 (CCPA 1930). See MPEP § 2144.04.
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Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Funakoshi, Ishimatsu, and Hong as applied to claim 8 above, and further in view of Hori et al. (“Hori” US 2020/0035637).
Regarding claim 10, Funakoshi does not explicitly disclose wherein heating the first material further comprises: heating the first material using sintering.
Hori discloses wherein heating the first material (bonding material, para. [0020]) further comprises: heating the first material using sintering (para. [0020]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of sintering of Hori into the teachings of Funakoshi for the purpose of forming a bonding layer with high shear strength (Hori, para. [0020]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Funakoshi, Ishimatsu, Hong, and Hori as applied to claim 10 above, and further in view of Hung et al. (“Hung” US 2021/0242117).
Regarding claim 11, Funakoshi does not disclose wherein a temperature range of the sintering is 270 degrees Celsius (°C) to 290°C, wherein the first material comprises nano silver, wherein the second material comprises lead-tin-silver alloy (PbSnAg), wherein the fourth material comprises PbSnAg, and wherein the fifth material comprises PbSnAg.
Hori discloses wherein a temperature range of the sintering is 270 degrees Celsius (°C) to 290°C (para. [0020]), wherein the first material comprises nano silver (silver particles 1 to 100nm in size, and thus are considered nano silver particles).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Hori into the teachings of Funakoshi to include the sintering temperature and nano silver particles for the first material for the purpose of forming a bonding layer with high shear strength (Hori, para. [0020]).
Hori discloses a sintering temperature range of 200 to 350°C which overlaps with the claimed temperature range. It is the position of the Office that in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists (see MPEP 2144.05).
Hung discloses using a lead-tin-silver alloy (PbSnAg) in para. [0020].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Hung to use a PbSnAg alloy for solder materials (second, fourth, and fifth materials) for the purpose of employing a known conductive material with low resistivity (Hung, para. [0020]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Funakoshi, Ishimatsu, and Hong as applied to claim 1 above, and further in view of Kajihara et al. (“Kajihara” US 2021/0305111).
Regarding claim 12, Funakoshi discloses:
The method of claim 1, wherein before heating the first material (12, 22), the method further comprises: plating a metal plating layer (terminal/lead 27) outside the first heat sink (23, since the plating layer lead 27 is not directly contacting the first heat sink 23, 27 is then considered as being outside the heat sink 23, further 27 extends outside the edge of the heat sink).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to heat the first material after plating a metal plating layer since the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946); In re Gibson, 39 F.2d 975, 5 USPQ 230 (CCPA 1930). See MPEP § 2144.04.
Funakoshi does not explicitly disclose wherein the metal plating layer comprises any one or more of silver (Ag), nickel (Ni), tin (Sn), and gold (Au).
Kajihara discloses using a plating layer comprising gold, silver, nickel, or tin for coating a metallic material (para. [0036]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of the plating of Kajihara into the teachings of Funakoshi for the purpose of improving corrosion resistance (para. [0036]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Funakoshi Ishimatsu, and Hong as applied to claim 2 above, and further in view of Akram (US Patent No. 6,387,732).
Regarding claim 14, Funakoshi discloses packaging the power device, but does not disclose wherein after packaging the power device, the method further comprises: trimming a power semiconductor.
Akram discloses: wherein after packaging the [power] device, the method further comprises: trimming (col. 1 line 52 – col. 2 line 9 discloses that once packaging is complete, trimming from the lead frame strip is performed).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Akram of trimming into the teachings of packaging the power semiconductor of Funakoshi for the purpose of forming outer shapes and leads of the package into the desired configuration (Akram, col. 1 line 52 – col. 2 line 9).
Claims 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Funakoshi Ishimatsu, and Hong as applied to claims 1 and 7 above, and further in view of Momose et al. (“Momose” US 2018/0190570).
Regarding claim 21, Funakoshi discloses:
The method of claim 1, wherein before heating the first material (12, 22), the method further comprises plating a metal plating layer (21) on an outer surface of the first heat sink (23), wherein the outer surface faces the first heat dissipation face (see Figure 1).
Funakoshi does not disclose that the metal plating layer comprises any one or more of silver (Ag), nickel (Ni), tin (Sn), and gold (Au).
Hong discloses a metal plating layer (123, Figure 1, para. [0027], on an outer surface of heat sink 140) comprising any one or more of silver (Ag), nickel (Ni), tin (Sn), and gold (Au) (see para. [0027], gold or silver are used).
It would have been obvious to one having ordinary skill in the art to incorporate silver or gold for the copper metal plate of Funakoshi for the purpose of using material with high thermal conductivity as taught by Momose (Momose, para. [0027]).
Regarding claim 22, Funakoshi discloses:
The method of claim 7, wherein before heating the first material (12, 22), the method further comprises:
plating a first metal plating layer (21) on a first outer surface of the first heat sink (23), wherein the first outer surface faces the first heat dissipation face (see Figure 1); and
plating a second metal plating layer (11) on a second outer surface of a second heat sink (13), wherein the second outer surface faces the second heat dissipation face (see Figure 1).
Funakoshi does not disclose that the first metal plating layer and the second metal plating layer each comprises any one or more of silver (Ag), nickel (Ni), tin (Sn), and gold (Au).
Momose discloses a metal plating layer (123, Figure 1, para. [0027], on an outer surface of heat sink 140) comprising any one or more of silver (Ag), nickel (Ni), tin (Sn), and gold (Au) (see para. [0027], gold or silver are used), which could be applied to both the first and second metal plating layers of Funakoshi.
It would have been obvious to one having ordinary skill in the art to incorporate silver or gold for the copper metal plates (11, 21) of Funakoshi for the purpose of using material with high thermal conductivity as taught by Momose (Momose, para. [0027]).
Response to Arguments
Applicant’s amendments, see Claims, filed September 25, 2025, with respect to the 112(a) and 112(b) rejections of claim 17 have been fully considered and overcome the 112 rejections. The 112 rejections of claim 17 are thus withdrawn.
However, the amendments to claims 16 and 18 have not overcome the 112(b) rejections. The amendments to claims 16 and 18 merely change the label of “arc-shaped segment” to “second arc-shaped segment” which is not a substantial difference in scope, rather only a labeling change. Thus claims 16 and 18 are still indefinite for the same reasons as stated in the Nonfinal Rejection. See also the restated rejection above Claim Rejections - 35 USC § 112.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 5712707877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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