DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/17/2025 has been entered.
Status of the Application
Claims 1-24 remain pending in this application. Acknowledgement is made of the amendment received 11/24/2025. Claims 15-24 remain withdrawn, and claims 1 and 10 are amended.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 3, 4, and 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (US 20070059931 A1, hereafter Park) in view of Laser (US 20080023776 A1), and further in view of Bohr et al (US 20040262683 A1, hereafter Bohr).
Regarding claim 1, Park teaches: A semiconductor device (Park fig 2C), comprising:
a first transistor (Park 218a) having first source/drain regions (Park 217a, ¶0040, 0064, 0065, n-type or p-type) separated by a first channel (Park ¶0026, “a first channel region interposed between the first source/drain regions 217a”, ¶0040, fig 2C);
a second transistor (Park 218b) having second source/drain regions (Park 217b, ¶0040, 0064, 0065, n-type or p-type) separated by a second channel (Park ¶0026, “a second channel region interposed between the second source/drain regions 217b”, ¶0041, fig 2C);
a first silicide interface contact (Park 221a, under a broadest reasonable interpretation (BRI) of “interface contact”, there is at least an interface in contact between 221a and 217a/225a, fig 2C, wherein 225a is a contact, ¶0038) on the first source/drain regions (Park fig 2C, ¶0038); and
a second silicide interface contact (Park 221b, under BRI of “interface contact”, there is at least an interface in contact between 221b and 217b/225b, fig 2C, wherein 225b is a contact, ¶0038) on the second source/drain regions (Park fig 2C, ¶0038) different from the first silicide interface contact (Park ¶0038, 0045, first and second silicide layers are different at least by their different thicknesses t1 and t2, fig 2C); and
wherein the first silicide interface contact and the second silicide interface contact includes an embedded portion (Park fig 2C, ¶0038).
Park does not explicitly teach: the first source/drain regions are n-type; the second source/drain regions are p-type; and
wherein only one of the first silicide interface contact and the second silicide interface contact includes an embedded portion.
Laser, in the same field of endeavor of semiconductor device manufacturing, teaches: A semiconductor device (Laser ¶0002), comprising: an n-type transistor (Laser ¶0002 “NMOS”) and a p-type transistor (Laser ¶0002 “PMOS”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Park such that the first source/drain regions and the second source/drain regions are n-type and p-type, respectively, forming both an NMOS and PMOS on the same device, as taught by Laser, in order to reduce the overall power consumption of the device (Laser ¶0002), and/or to provide a combination of driving signals (i.e. high or low) with good performance.
Further, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have an n-type and p-type source/drain regions to form n-type and p-type transistors in CMOS device to reduce power consumption, which are known and commonly used in semiconductor devices, and that the use of conventional materials to perform their known function is prima-facie obvious (See MPEP 2144.07).
Park in view of Laser does not explicitly teach: wherein only one of the first silicide interface contact and the second silicide interface contact includes an embedded portion.
Bohr, in the same field of endeavor of semiconductor device manufacturing, teaches: a first transistor (Bohr 503, ¶0037, NMOS) having n-type source/drain regions (Bohr 203, ¶0018, n-type);
a second transistor (Bohr 504, ¶0037, PMOS) having p-type source/drain regions (Bohr 204, 470, 480 ¶0018, p-type, ¶0024), including raised source/drain regions (Bohr 470, 480);
a first silicide interface contact (Bohr 523) on the n-type source/drain regions (Bohr fig 4); and
a second silicide interface contact (Bohr 524) on the p-type source/drain regions (Bohr fig 4), wherein only one of the first silicide interface contact and the second silicide interface contact includes an embedded portion (Bohr fig 4, ¶0025, 523 is at least embedded in 203 and below the top surface of a substrate 136, where 524 is raised above 136, and therefore, at least not embedded in the substrate).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the p-type source/drain regions of Park in view of Laser to include a raised source/drain regions, as taught by Bohr, and to thereby form the second silicide such that it is not embedded within the substrate, and such that “only one of the first silicide interface contact and the second silicide interface contact includes an embedded portion”, in order to provide compressive strain to the second channel (Bohr ¶0024-0026)., thereby improving hole mobility.
Regarding claim 3, Park in view of Laser and Bohr teaches: The semiconductor device of claim 1, wherein the first silicide interface contact (Park 221a) penetrates into a portion of the n-type source/drain regions (Park 217a, as modified by Laser to be n-type)(Park fig 2C).
Regarding claim 4, Park in view of Laser and Bohr teaches: The semiconductor device of claim 1, wherein the first silicide interface contact (Park 221a) includes a self-aligned silicide interface contact (Park discloses silicide layer 221a is formed via the common self-alignment process, ¶0069-0072).
Further, the claim recites “a self-aligned silicide interface contact”, which is a process claim that does not appear to impart a distinctive structural characteristic to the device, the process of forming a device is not germane to the issue of patentability of the device itself (MPEP 2113). Therefore, this limitation has not been given patentable weight.
In this instant case, “self-aligned” is a process of formation of the silicide interface contact, and does not appear to impart a distinctive structural characteristic.
Regarding claim 6, Park in view of Laser and Bohr teaches: The semiconductor device of claim 1, wherein the p-type source/drain regions (Park 217b, as modified by Laser to be p-type and to include Bohr 470, 480) include embedded silicon germanium (Bohr ¶0024, “silicon germanium (SiGe)”).
Regarding claim 7, Park in view of Laser and Bohr teaches: The semiconductor device of claim 1, wherein the second silicide interface contact (Park 221b, similar to Bohr 524) penetrates into a portion of the p-type source/drain regions (Park 217b, as modified by Laser to be p-type and to include Bohr 470, 480, Bohr ¶0037, “524 … consuming … 470 and 480)(Park fig 2C).
Regarding claim 8, Park in view of Laser and Bohr teaches: The semiconductor device of claim 1, wherein the second silicide interface contact (Park 221b) includes a self-aligned silicide interface contact (Park discloses silicide layer 221b is formed via the common self-alignment process, ¶0069-0072).
Further, the claim recites “a self-aligned silicide interface contact”, which is a process claim that does not appear to impart a distinctive structural characteristic to the device, the process of forming a device is not germane to the issue of patentability of the device itself (MPEP 2113). Therefore, this limitation has not been given patentable weight.
In this instant case, “self-aligned” is a process of formation of the silicide interface contact, and does not appear to impart a distinctive structural characteristic.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al (US 20070059931 A1, hereafter Park) in view of Laser (US 20080023776 A1) and Bohr et al (US 20040262683 A1, hereafter Bohr), as applied to claim 1 above, and further in view of Weng (CN 110854200 A, English translation provided in previous office action).
Regarding claim 2, Park in view of Laser and Bohr teaches: The semiconductor device of claim 1.
Park in view of Laser and Bohr does not explicitly teach: wherein the n-type source/drain regions include embedded silicon phosphorous.
Weng, in the same field of endeavor of semiconductor device manufacturing, teaches: an n-type source/drain regions (Weng 9, ¶0014-0015) include embedded silicon phosphorous (Weng ¶0014-0015).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the n-type source/drain regions of Park in view of Laser and Bohr to include embedded silicon phosphorous, as taught by Weng, in order to reduce source/drain contact resistance (Weng ¶0023) to improve device performance (Weng Abstract).
Claims 5 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (US 20070059931 A1, hereafter Park) in view of Laser (US 20080023776 A1) and Bohr et al (US 20040262683 A1, hereafter Bohr), as applied to claims 4 or 8 above, and further in view of Chang et al (US 20040262649 A1, hereafter Chang).
Regarding claim 5, Park in view of Laser and Bohr teaches: The semiconductor device of claim 4, including the self-aligned silicide interface contact (Park 221a) and a contact via (Park 225a).
Park in view of Laser and Bohr does not teach: an intermediate layer between the self-aligned silicide interface contact and a contact via.
Chang, in the same field of endeavor of semiconductor device manufacturing, teaches: an intermediate layer (Chang 61, ¶0025, from 40) between a self-aligned silicide interface contact (Chang 62, ¶0002, “Self-aligned silicide (salicide)”, ¶0021, 0024, from 30) and a contact via (Chang 82, ¶0029)(Chang fig 1H, it appears that fig 1H mislabels 61 and 62, reversing them, see ¶0030, “top CoSi.sub.x portion 61 that is operative as a protection layer and a relatively thicker, low resistance NiSi portion 62”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of Park in view of Laser and Bohr to include the intermediate layer of Chang between the self-aligned silicide interface contact and contact via, in order to provide a protection layer for better chemical and/or plasma resistance (¶0001, 0021), and/or reduce junction leakage by reducing silicon consumption during formation (¶0037).
Regarding claim 9, Park in view of Laser and Bohr teaches: The semiconductor device of claim 8, including the self-aligned silicide interface contact (Park 221a) and a contact via (Park 225a).
Park in view of Laser and Bohr does not teach: an intermediate layer between the self-aligned silicide interface contact and a contact via.
Chang, in the same field of endeavor of semiconductor device manufacturing, teaches: an intermediate layer (Chang 61, ¶0025, from 40) between a self-aligned silicide interface contact (Chang 62, ¶0002, “Self-aligned silicide (salicide)”, ¶0021, 0024, from 30) and a contact via (Chang 82, ¶0029)(Chang fig 1H, it appears that fig 1H mislabels 61 and 62, reversing them, see ¶0030, “top CoSi.sub.x portion 61 that is operative as a protection layer and a relatively thicker, low resistance NiSi portion 62”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of Park in view of Laser and Bohr to include the intermediate layer of Chang between the self-aligned silicide interface contact and contact via, in order to provide a protection layer for better chemical and/or plasma resistance (¶0001, 0021), and/or reduce junction leakage by reducing silicon consumption during formation (¶0037).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Tsuruta et al (US 20140191327 A1, hereafter Tsuruta) in view of Park et al (US 20070059931 A1, hereafter Park).
Regarding claim 10, Tsuruta teaches: A memory device (Tsuruta fig 4) comprising:
an array of memory cells (Tsuruta “memory cell array”, ¶0044, 0046, fig 4, MCi,j-1, MCi,j, MCi,j+1);
peripheral circuitry (Tsuruta “column-side peripheral circuits”, ¶0044, CLj-1, CLj, CLj+1,) adjacent to the array of memory cells (Tsuruta fig 4), the peripheral circuitry including;
a first transistor (Tsuruta Nclj, ¶0033, 0035) having n-type source/drain regions (Tsuruta S/D, fig 2, ¶0033, 0035, “N-type source/drain regions S/D”, ¶0042) separated by a first channel (Tsuruta a region below Gate G, between two S/D, fig 2, 4, ¶0042, therefore a channel region must exist);
a second transistor (Tsuruta Pclj, ¶0033, 0035) having p-type source/drain regions (Tsuruta S/D, fig 2, ¶0033, 0035, “P-type source/drain regions S/D”, ¶0043) separated by a second channel (Tsuruta a region below Gate G, between two S/D in an n-well region, fig 2, 4, ¶0043, therefore a channel region must exist).
Tsuruta does not teach: a first silicide interface contact on the n-type source/drain regions; and
a second silicide interface contact on the p-type source/drain regions different from the first silicide interface contact, wherein one of the first silicide interface contact and the second silicide interface contact includes a flat interface with a corresponding source/drain region.
Park, in the same field of endeavor of semiconductor device manufacturing, teaches:
a first transistor (Park 218a) having first source/drain regions (Park 217a, ¶0040, 0064, 0065, n-type or p-type) separated by a first channel (Park ¶0026, “a first channel region interposed between the first source/drain regions 217a”, ¶0040, fig 2C);
a second transistor (Park 218b) having second source/drain regions (Park 217b, ¶0040, 0064, 0065, n-type or p-type) separated by a second channel (Park ¶0026, “a second channel region interposed between the second source/drain regions 217b”, ¶0041, fig 2C);
a first silicide interface contact (Park 221a, under BRI of “interface contact”, there is at least an interface in contact between 221a and 217a/225a, fig 2C, wherein 225a is a contact, ¶0038) on the first source/drain regions (Park fig 2C, ¶0038); and
a second silicide interface contact (Park 221b, under BRI of “interface contact”, there is at least an interface in contact between 221b and 217b/225b, fig 2C, wherein 225b is a contact, ¶0038) on the second source/drain regions (Park fig 2C, ¶0038) different from the first silicide interface contact (Park ¶0038, 0045, first and second silicide layers are different at least by their different thicknesses t1 and t2, fig 2C),
wherein one of the first silicide interface contact (Park 221a) and the second silicide interface contact (Park 221b) includes a flat interface with a corresponding source/drain region (Park 217a and 217b, respectively)(Park fig 2C, at least the bottom interface between 221a/217a and/or 221b/217b is flat).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the first and second transistors of Tsuruta to include the first and second interface contacts of Park on the n-type and p-type source/drain regions, respectively, in order to improve the contact resistance of the source/drain regions (Park ¶0046, 0047), and/or to optimize the performance of the n-type and/or p-type transistors (Park ¶0060).
Claims 11, 12, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Tsuruta et al (US 20140191327 A1, hereafter Tsuruta) in view of Park et al (US 20070059931 A1, hereafter Park), as applied to claim 10 above, and further in view of Doris et al (US 20070284617 A1, hereafter Doris).
Regarding claim 11, Tsuruta in view of Park teaches: The memory device of claim 10.
Tsuruta in view of Park does not teach: a silicon nitride liner over one or more of the first and second transistors.
Doris, in the same field of endeavor of semiconductor device manufacturing, teaches: a silicon nitride layer (Doris 28, 48, 52, ¶0019, 0053, 0054) over one or more of an n-type transistor (n-FET, 4, ¶0012, ¶0065) and a p-type transistor (p-FET, 2, ¶0012, ¶0065)(Doris fig 4B).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the silicon nitride layer of Doris to the peripheral circuitry of Tsuruta in view of Park, such that “a silicon nitride liner over one or more of the first and second transistors”, in order to provide tensile stress to the first transistor and compressive stress to the second transistor, thereby improving the performance of each transistor without negative affects to the other (Doris ¶0002-0004).
Regarding claim 12, Tsuruta in view of Park teaches: The memory device of claim 10.
Tsuruta in view of Park does not teach: a tensile silicon nitride liner over at least a portion of the first transistor.
Doris, in the same field of endeavor of semiconductor device manufacturing, teaches: a tensile silicon nitride layer (Doris 48, ¶0019, 0053, 0054) over at least a portion of an n-type transistor (n-FET, 4, ¶0012, ¶0065)(Doris fig 4B).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the tensile silicon nitride layer of Doris to the first transistor of Tsuruta in view of Park, such that “a tensile silicon nitride liner over at least a portion of the first transistor”, in order to provide tensile stress to the first transistor, thereby improving the performance of the first transistor without negative affects to the second transistor (Doris ¶0002-0004).
Regarding claim 14, Tsuruta in view of Park and Doris teaches: The memory device of claim 12.
Tsuruta in view of Park and Doris does not teach: a compressive silicon nitride liner over at least a portion of the second transistor.
Doris further teaches: a compressive silicon nitride layer (Doris 28, ¶0019, 0053, 0054) over at least a portion of a p-type transistor (p-FET, 2, ¶0012, ¶0065)(Doris fig 4B).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the compressive silicon nitride layer of Doris to the second transistor of Tsuruta in view of Park and Doris, such that “a compressive silicon nitride liner over at least a portion of the second transistor”, in order to provide compressive stress to the second transistor, thereby improving the performance of the second transistor without negative affects to the first transistor (Doris ¶0002-0004).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Tsuruta et al (US 20140191327 A1, hereafter Tsuruta) in view of Park et al (US 20070059931 A1, hereafter Park) and Doris et al (US 20070284617 A1, hereafter Doris), as applied to claim 12 above, and further in view of Yu et al (US 20150295085 A1, hereafter Yu).
Regarding claim 13, Tsuruta in view of Park and Doris teaches: The memory device of claim 12
Tsuruta in view of Park and Doris does not teach: dislocations in the n-type source/drain regions of the first transistor.
Yu, in the same field of endeavor of semiconductor device manufacturing, teaches: dislocations (Yu 110a, 110b, ¶0013, 0016) in an n-type source/drain regions (Yu 108a, 108b, ¶0015, “n-type doping for an NMOS transistor”) of a transistor (Yu 100, ¶0013)(Yu fig 1).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the source/drain regions of the first transistor of Tsuruta in view of Park and Doris to include the dislocations of Yu, in order to provide stress to a channel region (Yu ¶0013, 0017), thereby improving short channel effects of the transistor (Yu ¶0017).
Response to Arguments
Applicant's arguments regarding claims 10-14, filed 11/24/2025, have been fully considered but they are not persuasive.
Regarding claim 10, the Applicant argues at pages 7 and 8:
Applicant is unable to find in Park "one of the first silicide interface contact and the second silicide interface contact includes a flat interface with a corresponding source/drain region."
Examiner’s response:
The Examiner respectfully disagrees. Park fig 2C clearly shows a flat interface between an interface of 221a and 217a, and an interface of 221b and 217b. For clarity, see annotated Park fig 2C below.
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Annotated Park fig 2C
Applicant’s arguments with respect to claims 1-9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/Mounir S Amer/Primary Examiner, Art Unit 2818