DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12-15, 18-19 & 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Chow in view of Lin et al. (US Patent 9,401,331).
Regarding claim 1, Chow teaches a method of forming a semiconductor package, the method comprising:
providing a metal baseplate comprising a base section 102 and a plurality of metal posts 104, the base section being a planar pad of substantially uniform thickness, the plurality of metal posts 104 each extending up from a planar upper surface of the base section (Fig. 3a);
mounting a semiconductor die 110 on the upper surface of the base section with a main surface of the semiconductor die 110 comprising terminals (unlabeled pads) facing away from the metal baseplate (Fig. 3b);
forming an encapsulant body of electrically insulating mold compound 114 on the metal baseplate that encapsulates the semiconductor die 110 (Fig. 3e);
removing the base section thereby detaching the metal posts 104 from one another and exposing the metal posts 104 at a first surface of the encapsulant body (after removal of 102, metal posts are exposed from the bottom surface of the encapsulant body, see Fig. 3d-3e. Also see Fig. 4b-4f); and
electrically connecting the terminals of the semiconductor die 110 to the metal posts 104, and a height of the metal posts 104 being a distance between the planar upper surface of the base section and first ends of the metal posts that face away from the baseplate (see Fig. 3d-3e and Fig. 4b-4f and associated texts).
Chow is silent on wherein a thickness of the semiconductor die when mounted is greater than a height of the metal posts. However, Lin a semiconductor device, wherein a thickness of a semiconductor die 112 when mounted is greater than a height of metal posts 110 (Fig. 3f-3g and claims 14 & 19). This has the advantage of allowing for an alternative design choice to advance further miniaturization to save precious real estate on a chip. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Chow with the semiconductor die having a larger thickness than the height of the metal posts, as taught by Lin, so as to improve further miniaturization.
Regarding claim 13, the combination of Chow and Lin teaches the method of claim 12, wherein after forming the encapsulant body first ends of the metal posts that face away from the baseplate are exposed from a second surface of the encapsulant body, wherein the main surface of the semiconductor die faces the second surface of the encapsulant body and is covered by the mold compound (Chow’s Fig. 3c & Lin’s Fig. 3g).
Regarding claim 14, the combination of Chow and Lin teaches the method of claim 13, wherein the metal posts are arranged within an outer region of the encapsulant body ((106 &114)/116) and the semiconductor die is arranged within a central region of the encapsulant body, wherein the second surface of the encapsulant body extends along a first plane in the outer region, extends along a second plane that is vertically offset from the first plane in the central region, and extends along a third plane that is transverse to the first and second planes in a transition region between the central region and the outer region (Chow’s Fig. 3d-3e and Fig. 4b-4f and Lin’s Fig. 3f-3g).
Regarding claim 15, the combination of Chow and Lin teaches the method of claim 14, further comprising providing vertical connectors 112 on the terminals of the semiconductor die before forming the encapsulant body (e.g. Chow’s Fig. 3b), wherein the encapsulant body is formed such that the vertical connectors are exposed from the second surface of the encapsulant body in the central region, and wherein electrically connecting the terminals of the semiconductor die to the metal posts comprises forming conductive tracks 126/132 on the second surface of the encapsulant body that extend from the central region and across the transition region to reach the metal posts in the outer region (Chow’s Fig. 3d-3e and Fig. 4b-4f and Lin’s Fig. 3f-3g).
Regarding claim 18, the combination of Chow and Lin teaches the method of claim 15, further comprising forming an electrically insulating layer 128 on the second surface of the encapsulant body that covers the conductive tracks (e.g. Chow’s Fig. 3e).
Regarding claim 19, the combination of Chow and Lin teaches the method of claim 15, wherein, after removing the metal baseplate, second ends of the metal posts are exposed at the first surface of the encapsulant body, and wherein the method further comprises forming contact pads over the second ends of the metal posts (Chow’s Fig. 3d-3e).
Regarding claim 20, the combination of Chow and Lin teaches the method of claim 15, wherein the semiconductor die is mounted on the metal baseplate with a layer of adhesive between a rear surface terminal of the semiconductor die and the metal baseplate (Chow’s Para [0029 & 0030]), wherein after removing the metal baseplate the layer of adhesive is exposed at the first surface of the encapsulant body, and wherein the method further comprises forming a contact pad over the layer of adhesive (though not shown in the drawing, Chow teaches a layer of adhesive between rear surface of the semiconductor die 112 and the metal base plate 102 in para [0029 & 0030]. It is understood that contacts pads126 are formed over said layer of adhesive)
Regarding claim 21, the combination of Chow and Lin teaches the method of claim 12, wherein forming the encapsulant body comprises: performing a first molding step (e.g. 106) that that encapsulates the metal posts 104 and partially encapsulates the semiconductor die with the mold compound; and performing a second molding step 114 that covers the main surface of the semiconductor die with the mold compound 114 (Fig. 3b).
Regarding claim 22, the combination of Chow and Lin teaches the method of claim 12, wherein the thickness of the semiconductor die is at least 200 um, and wherein the height of each of the metal posts is no more than 250 um (Lin’s Fig. 3c and associated text). Notwithstanding, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Furthermore, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Chow and Lin as applied to claim 15 above, and in further view of Lee et al. (US Pub. 2020/0381380).
Regarding claim 16, Chow is silent on the method of claim 15, wherein the electrically insulating mold compound comprises a laser-activatable mold compound, wherein forming the conductive tracks comprises applying a laser to the laser-activatable mold compound to activate the laser-activatable mold compound in selected regions and performing a metal plating process to deposit metal in the selected regions. However, Lee teaches a semiconductor device comprising an electrically insulating mold compound 102 comprises a laser-activatable mold compound, wherein forming conductive tracks comprises applying a laser to the laser-activatable mold compound to activate the laser- activatable mold compound in selected regions and performing a metal plating process to deposit metal in the selected regions (Fig. 75A-5E. 6A-6E & 7A-7D). This has the advantage of improving formatting of conductive pads in desired/selective areas. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Chow with the use of laser-activatable mold compound, as taught by Lee, so as to form conductive pads in selective areas of the semiconductor device.
Regarding claim 17, the combination of Chow and Lee teaches the method of claim 16, wherein performing the metal plating process comprises forming a lower layer 126 of the conductive tracks by an electroless plating process and forming an upper layer of the conductive tracks 130 on the lower layer by an electroplating process (Chow’s Para [0030]).
Allowable Subject Matter
Claims 1-2, 4-11 are allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to claim 1, the prior art of record fails to teach or suggest in combination with other claim features, a method of forming a semiconductor package, the method comprising: wherein the encapsulant body is formed such that first ends of the metal posts that face away from the upper surface of the baseplate are covered by the mold compound.
Claims 2 & 4-11 are allowed as being directly or indirectly dependent of the allowed independent base claim 1.
Response to Arguments
With respect to claim 12, applicant's arguments filed 12/11/2025 have been fully considered but they are not persuasive. It appears that the limitation “mounting a semiconductor die on the upper surface of the base section with a main surface of the semiconductor die comprising terminals facing away from the metal baseplate” (note bolded portion) is contradictory to applicant’s Fig13A-13D on which the Examiner has relied to map the claim. The terminals (note unlabeled pads of the chip 108) are positioned in the same surface as the terminals/pads of Chow’s device (see Chow’s Fig. 3a-3b). There is no showing or teaching for terminals or pads on the upper surface of the chip 108. As best understood, Chow’s terminals (pads) read on said claim features. To help advance the prosecution, the examiner suggests that applicant map claim 12 to a specific drawing and provide a showing for the “terminals facing away from the metal base plate”.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOR KARIMY whose telephone number is (571)272-9006. The examiner can normally be reached Monday - Friday: 8:30 AM -5:00 PM.
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818