DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 14-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 08/25/25.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-12 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 20210408046 (Chang et al).
Concerning claim 1, Chang discloses a three-dimensional synapse device stack (Figs. 2-28D, Chang discloses a three dimensional device stack, the synapse limitation is intended use and does not change the structure of the device presented), which comprises a substrate (50) having an upper surface formed of an oxide layer (224) (Fig. 28C); a channel hole (86) disposed on the substrate in the vertical direction, provided in a form of a pillar shape, and inside of which is filled with an insulating material (102) (Fig. 16): a semiconductor body (92) disposed on the surface of the channel hole and made of a semiconductor material ([0016]): a plurality of first insulating layers (52) disposed on an outer circumferential surface of the semiconductor body ([0013] and [0027]): a plurality of sources (204) disposed on a first side surface of an outer circumferential surface of the semiconductor body ([0011] and [0013]); a plurality of drains (204) disposed on a second side surface of an outer circumferential surface of the semiconductor body opposite to the first side surface ([0011] and [0013]); a plurality of word lines (72) disposed on a third side surface of the outer peripheral surface of the semiconductor body positioned between the sources and the drains ([0013]): a plurality of insulator stacks (90) disposed between the word lines and the semiconductor body and including at least a layer for storing electric charges or causing polarization ([0018]), a source line electrode (108) disposed on a substrate in a vertical direction, provided in a form of a pillar shape, and electrically connected to the plurality of sources ([0013]); and, a drain line electrode (106) disposed on a substrate in a vertical direction, provided in a form of a pillar shape, and electrically connected to the plurality of drains ([0013]): wherein the first insulating layers and the sources are alternately stacked on the first side surface of the outer peripheral surface of the semiconductor body, and the first insulating layers and the drains are alternately stacked on the second side surface of the outer peripheral surface of the semiconductor body, and the first insulating layers and the word lines surrounded by the insulator stacks are alternately stacked on the third side surface of the outer circumferential surface of the semiconductor body (Figs. 26A-26C), and wherein the semiconductor body, the source, the dram, the insulator stack and the word line located on the same layer on the surface of the channel hole constitute a synapse device or a part thereof, and synapse devices electrically isolated from each other by the first insulating layers are stacked to form a stack structure (Figs. 24-26C).
Continuing to claim 2, Chang discloses wherein the semiconductor body is located on the surface of the channel hole, but is not provided on the side surface of the first insulating layers positioned between the stacked word Hines, so that adjacent word lines of the synapse devices stacked in a stack structure are electrically isolated from each other (Fig. 23C).
Considering claim 3, Chang discloses wherein region provided with synapse devices among the surface of the channel hole protrudes and extends toward the sources, drains, and word lines; and the semiconductor body is provided only on the protruding and extended surface of the channel hole, and is not provided on the non-protruding surface of the channel hole, so that adjacent word lines of synapse devices stacked in a stack structure are electrically isolated from each other (Fig. 1A).
Referring to claim 4, Chang discloses wherein a region where synapse device are formed among the surface of the channel hole protrudes and extends toward the sources, drains, and word lines: and the semiconductor body is located on the surface of the channel hole, but is not provided on the side surfaces of the first insulating layers positioned between the stacked word lines; so that the adjacent word lines of the synapse devices stacked in a stack structure are electrically isolated from each other (Fig. 1A).
Regarding claim 5, Chang discloses wherein a region where synapse devices are formed among the surface of the channel hole protrudes and extends toward the sources, drains, and word lines (Fig. 1A).
Pertaining to claim 6, Chang discloses wherein the insulator stack is composed of a single insulating layer or a stack structure in which a plurality of layers are stacked ([0018]); and wherein when the insulator stack is configured in a stack structure, the insulator stack comprises at least a charge storage layer and an insulating layer, at least a ferroelectric layer and an insulating layer, at least a resistance change layer and an insulating layer, or at least a phase change layer and an insulating layer ([0018]).
As to claim 7, Chang discloses which further comprises a body landing pad (116C) positioned on the oxide layer ([0067]), wherein the body landing pad is made of an electrically conductive material and is electrically connected to the semiconductor body (Fig. 28C).
Considering claim 8, Chang discloses which further comprises a source electrode landing pad (112) and a drain electrode landing pad (114) positioned in the oxide layer ([0067]), wherein the source electrode landing pad is made of an electrically conductive material and is electrically connected to the source line electrode, and the drain electrode landing pad is made of an electrically conductive material and is electrically connected to the drain line electrode ([0067]).
Continuing to claim 9, Chang disclose which further comprises an additional stack structure which shares the sources, the source line electrode, the drains and the drain Ime electrode and includes a plurality of additional word lines positioned on a fourth side of an outer circumferential surface of the semiconductor body opposite to the third side and alternately stacked with first insulating layers; and a plurality of additional insulator stacks provided between the additional word lines and the semiconductor body, wherein the semiconductor body, the source, the drain, the additional insulator stack and the additional word lime located on the same laver on the surface of the channel hole constitute an additional synapse device or a part thereof, and the synapse device and the additional synapse device located on the same layer share the source and the drain (Fig. 27).
Considering claim 10, Chang discloses a three-dimensional stackable synapse array, characterized in that the three-dimensional synapse device stacks according to claim 1 are arranged in an array form ([0006] and [0022]).
Referring to claim 11, Chang discloses wherein the three-dimensional stacked synapse array constitutes an AND-type synapse array by arranging a source line electrode and a drain line electrode connecting the three-dimensional synapse device stacks side by side, or a NOR-type synapse array by arranging the source line electrode and the drain line electrode connecting the three-dimensional synapse device stacks to cross each other ([0013]).
Regarding claim 12, Chang discloses which further comprises a three-dimensional capacitor stack having the same structure as the three-dimensional synapse device stack ([0025]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210408046 (Chang et al) in view of US 20220036931 (Lin et al).
Pertaining to claim 13, Chang discloses forming circuits that may be formed over the substrate ([0024]).
Chang does not disclose which further comprises a CMOS integrated circuit used as a peripheral circuit under the substrate. However, Lin discloses a three dimensional stacked device in which stacked memory cells may be vertically stacked over a complementary metal oxide semiconductor (CMOS) under array (CUA) ([0009]). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to form the circuits in the device of Chang as CMOS integrated circuits because of they are known in the art to be suitable for use in three dimensional stacked devices.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 10593697 disc loses a three dimensional stacked device (Fig. 12).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5.
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/VALERIE N NEWTON/ Examiner, Art Unit 2897 11/29/25
/VU A VU/ Primary Examiner, Art Unit 2897