DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment/Argument
Applicant’s arguments, see remarks, filed 09/08/2025, with respect to the objections to the drawings have been fully considered and are persuasive. The objections to the drawings have been withdrawn.
Applicant’s arguments, see remarks, filed 09/08/2025, with respect to the objection to the specification have been fully considered and are persuasive. The objection to the specification has been withdrawn.
Applicant’s arguments, see remarks, filed 09/08/2025, with respect to the objection of claim 1 have been fully considered and are persuasive. The objection of claim 1 has been withdrawn.
Applicant’s arguments, see remarks, filed 09/08/2025, with respect to the rejection(s) of claim(s) 1 under 35 U.S.C. 112 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of the amendments to claim 1 raising new issues under 35 U.S.C. 112.
Applicant's arguments filed 09/08/2025 with respect to the rejections of claims 1-10 under 35 U.S.C. 103 have been fully considered but they are not persuasive. While the cited references of US-20210149598-A1 to Choi et al. and US-20220108741-A1 to Hong et al. do not explicitly teach a synapse string, the language claim 1 uses to describe what constitutes a synapse string is taught by Choi in view of Hong, such as word lines, insulating layers and a semiconductor body. Additionally, after reviewing the claimed language and cited references a second time, the rejection has been changed to being under 35 U.S.C. 102 instead of 35 U.S.C. 103.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “a plurality of second insulating layers disposed on a surface between the first side and the second side of the outer circumferential surface of the semiconductor body”. Examiner believes this limitation is intended to claim the nitride layers depicted between a first and second channel hole in Figure 2 of the drawings. It is unclear which surface is “between the first side and the second side” that the claimed second insulating layers are disposed on, and it is unclear how the location of the nitride layers is between “the first side and the second side of the outer circumferential surface of the semiconductor body”. Correction is required for compliance with 35 U.S.C. 112(b).
Claim 1 recites the limitation "the second insulator stacks" in the second to last paragraph. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-4 and 7-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. (US-20210149598-A1 – hereinafter Choi).
Regarding claim 1, Choi teaches a three-dimensional stackable synapse string (Fig.5 BLK1; ¶0071), comprising:
a channel hole (Fig.5 113; ¶0075) provided in the form of a pillar shape (Fig.5 depicts 113 having a vertical pillar shape) in a vertical direction, the channel hole being filled with an insulating material (Fig.5 115; ¶0077);
a semiconductor body (Fig.5 114; ¶0076) disposed on a surface of the channel hole (113, 115 is disposed on 114) in the form of a thin layer;
a plurality of first insulating layers (Fig.5 112; ¶0075) disposed on an outer circumferential surface of the semiconductor body (114) in a vertical direction;
a plurality of first word lines (Fig.5 211-291: ¶0079) disposed on a first side (left side) of the outer circumferential surface of the semiconductor body (114) and alternately provided with the first insulating layers (112) disposed on the first side surface;
a plurality of second word lines (Fig.5 211-291 disposed on the opposite side of 113 and 114 from the first word lines) disposed on a second side (right side) of the outer circumferential surface of the semiconductor body (114) and alternately provided with the first insulating layers (112) disposed on the second side surface;
a plurality of first insulator stacks (Fig.5 116; ¶0080) positioned between the first word lines (211-291) and the semiconductor body (114), respectively;
a plurality of second insulating layers disposed on a surface between the first side and the second side of the outer circumferential surface of the semiconductor body, and the second insulating layers alternately stacked with the first insulating layers (Fig.5 the horizontal space between each channel hole 113 and each word line 211-291 is occupied by insulation and isolates the word lines and channel holes from one another);
a first electrode (Fig.5 331-333; ¶0083) disposed on the channel hole (113) and electrically connected to a first end (top end) of the semiconductor body (114); and
a second electrode (Fig.5 311/312; ¶0082) disposed under the channel hole (113) and electrically connected to a second end (bottom end) of the semiconductor body (114);
wherein the first word lines (211-291 left), the first insulator stacks (116 left), and the semiconductor body (114 left) constitute first synapse devices or a part thereof, and the first synapse devices stacked along the vertical direction of the channel bole (113) are connected by the semiconductor body (114) to constitute a first synapse string,
wherein the second word lines (211-291 right), the second insulator stacks, and the semiconductor body (114 right) constitute second synapse devices or a part thereof, and the second synapse devices stacked along the vertical direction of the channel hole (113) are connected by the semiconductor body (114) to constitute a second synapse string, and
wherein the second insulating layers (112 right) and the first insulating layers (112 left) disposed on the surface between the first side and the second side of the outer circumferential surface of the semiconductor body (114) constitute a device isolation unit to isolate the first synapse string (left stack) from the second synapse string (right stack).
Regarding claim 3, Choi teaches the three-dimensional stackable synapse string according to claim 1, wherein a surface of the channel hole (113) where the first synapse device and the second synapse device are formed is protruded and extended toward the word line (Fig.5 the synapse devices extend out from the channel hole 113).
Regarding claim 4, Choi teaches the three-dimensional stackable synapse string according to claim 1, wherein the first insulator stacks (116) or the second insulator stacks are composed of a single layer (Fig.5 of Choi depicts 116 as a single layer) or a stacked structure of multiple layers; and the stacked structure of multiple layers comprises at least a charge storage layer and an insulating layer, at least a ferroelectric layer and an insulating layer, at least a resistance change layer and an insulating layer, or at least a phase change layer and an insulating layer.
Regarding claim 7, Choi teaches the three-dimensional stackable synapse string according to claim 1, wherein the first synapse string and the second synapse string share the first electrode (333) and the second electrode (311/312 shared by the leftmost synapse string).
Regarding claim 8, Choi teaches the three-dimensional stackable synapse string according to claim 1, wherein the first synapse string and the second synapse string share the first electrode (333) and include a second electrode separately (Fig.5 depicts the left most and the center synapse strings both being connected to separate 312).
Regarding claim 9, Choi teaches a three-dimensional stackable synapse array, comprising:
the three-dimensional synapse device string according to claim 1, wherein the three-dimensional synapse device string is arranged in an array form (Fig.5 of Choi depicts a plurality of synapse strings arrange in array form).
Regarding claim 10, Choi teaches the three-dimensional stackable synapse array according to claim 9, further comprising:
a CMOS integrated circuit used as a peripheral circuit under a substrate (Choi teaches a CMOS memory cell, as the device comprises numerous oxides and semiconductor components).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Hong et al. (US-20220108741-A1 – hereinafter Hong).
Regarding claim 2, Choi teaches the three-dimensional stackable synapse string according to claim 1, further comprising:
a substrate (Fig.5 111; ¶0078).
Choi does not teach the substrate having an upper surface formed of an oxide layer, and the second electrode is provided on the upper surface of the oxide layer.
Hong teaches a memory device (Fig.1B 1 of Hong) having a substrate with a buried oxide layer (¶0016 of Hong).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have included an oxide layer as taught by Hong (¶0016 of Hong) on the substrate taught by Choi (111 of Choi) to arrive at the claimed invention. A practitioner would be motivated to make this modification to reduce electrical leakage through the device substrate.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J KOLB whose telephone number is (571)272-0276. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm.
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/T.J.K./ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817